1155324Simp/*-
2155324Simp * Copyright (c) 2005 M. Warner Losh.  All rights reserved.
3155324Simp *
4155324Simp * Redistribution and use in source and binary forms, with or without
5155324Simp * modification, are permitted provided that the following conditions
6155324Simp * are met:
7155324Simp * 1. Redistributions of source code must retain the above copyright
8155324Simp *    notice, this list of conditions and the following disclaimer.
9155324Simp * 2. Redistributions in binary form must reproduce the above copyright
10155324Simp *    notice, this list of conditions and the following disclaimer in the
11155324Simp *    documentation and/or other materials provided with the distribution.
12155324Simp *
13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16185265Simp * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23185265Simp * SUCH DAMAGE.
24155324Simp */
25155324Simp
26155324Simp/* $FreeBSD$ */
27155324Simp
28155324Simp#ifndef ARM_AT91_AT91STREG_H
29155324Simp#define ARM_AT91_AT91STREG_H
30155324Simp
31155324Simp#define ST_CR		0x00 /* Control register */
32155324Simp#define ST_PIMR		0x04 /* Period interval mode register */
33155324Simp#define ST_WDMR		0x08 /* Watchdog mode register */
34155324Simp#define ST_RTMR		0x0c /* Real-time mode register */
35155324Simp#define ST_SR		0x10 /* Status register */
36155324Simp#define ST_IER		0x14 /* Interrupt enable register */
37155324Simp#define ST_IDR		0x18 /* Interrupt disable register */
38155324Simp#define ST_IMR		0x1c /* Interrupt mask register */
39155324Simp#define ST_RTAR		0x20 /* Real-time alarm register */
40155324Simp#define	ST_CRTR		0x24 /* Current real-time register */
41155324Simp
42155324Simp/* ST_CR */
43155324Simp#define ST_CR_WDRST	(1U << 0) /* WDRST: Watchdog Timer Restart */
44155324Simp
45155324Simp/* ST_WDMR */
46155324Simp#define ST_WDMR_EXTEN	(1U << 17) /* EXTEN: External Signal Assert Enable */
47155324Simp#define ST_WDMR_RSTEN	(1U << 16) /* RSTEN: Reset Enable */
48155324Simp
49155324Simp/* ST_SR, ST_IER, ST_IDR, ST_IMR */
50155324Simp#define ST_SR_PITS	(1U << 0) /* PITS: Period Interval Timer Status */
51155324Simp#define ST_SR_WDOVF	(1U << 1) /* WDOVF: Watchdog Overflow */
52155324Simp#define ST_SR_RTTINC	(1U << 2) /* RTTINC: Real-time Timer Increment */
53155324Simp#define ST_SR_ALMS	(1U << 3) /* ALMS: Alarm Status */
54155324Simp
55155324Simp/* ST_CRTR */
56155324Simp#define ST_CRTR_MASK	0xfffff /* 20-bit counter */
57155324Simp
58238376Simpvoid at91_st_delay(int n);
59238376Simpvoid at91_st_cpu_reset(void);
60238376Simp
61155324Simp#endif /* ARM_AT91_AT91STREG_H */
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