1/*-
2 * Copyright (c) 2005 M. Warner Losh.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26/* $FreeBSD$ */
27
28#ifndef ARM_AT91_AT91STREG_H
29#define ARM_AT91_AT91STREG_H
30
31#define ST_CR		0x00 /* Control register */
32#define ST_PIMR		0x04 /* Period interval mode register */
33#define ST_WDMR		0x08 /* Watchdog mode register */
34#define ST_RTMR		0x0c /* Real-time mode register */
35#define ST_SR		0x10 /* Status register */
36#define ST_IER		0x14 /* Interrupt enable register */
37#define ST_IDR		0x18 /* Interrupt disable register */
38#define ST_IMR		0x1c /* Interrupt mask register */
39#define ST_RTAR		0x20 /* Real-time alarm register */
40#define	ST_CRTR		0x24 /* Current real-time register */
41
42/* ST_CR */
43#define ST_CR_WDRST	(1U << 0) /* WDRST: Watchdog Timer Restart */
44
45/* ST_WDMR */
46#define ST_WDMR_EXTEN	(1U << 17) /* EXTEN: External Signal Assert Enable */
47#define ST_WDMR_RSTEN	(1U << 16) /* RSTEN: Reset Enable */
48
49/* ST_SR, ST_IER, ST_IDR, ST_IMR */
50#define ST_SR_PITS	(1U << 0) /* PITS: Period Interval Timer Status */
51#define ST_SR_WDOVF	(1U << 1) /* WDOVF: Watchdog Overflow */
52#define ST_SR_RTTINC	(1U << 2) /* RTTINC: Real-time Timer Increment */
53#define ST_SR_ALMS	(1U << 3) /* ALMS: Alarm Status */
54
55/* ST_CRTR */
56#define ST_CRTR_MASK	0xfffff /* 20-bit counter */
57
58void at91_st_delay(int n);
59void at91_st_cpu_reset(void);
60
61#endif /* ARM_AT91_AT91STREG_H */
62