at91_rstreg.h revision 213496 
1108983Simp/*-
2108983Simp * Copyright (c) 2009 Greg Ansley.  All rights reserved.
3108983Simp *
4108983Simp * Redistribution and use in source and binary forms, with or without
5108983Simp * modification, are permitted provided that the following conditions
6108983Simp * are met:
7108983Simp * 1. Redistributions of source code must retain the above copyright
8108983Simp *    notice, this list of conditions and the following disclaimer.
9108983Simp * 2. Redistributions in binary form must reproduce the above copyright
10108983Simp *    notice, this list of conditions and the following disclaimer in the
11108983Simp *    documentation and/or other materials provided with the distribution.
12108983Simp *
13108983Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14108983Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15108983Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16108983Simp * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17108983Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18108983Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19108983Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20130151Sschweikh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21134867Sglebius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22139027Sbrueffer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23139027Sbrueffer * SUCH DAMAGE.
24139027Sbrueffer */
25108983Simp
26139027Sbrueffer/* $FreeBSD: head/sys/arm/at91/at91_rstreg.h 213496 2010-10-06 22:25:21Z cognet $ */
27139027Sbrueffer
28139027Sbrueffer#ifndef ARM_AT91_AT91RSTREG_H
29108983Simp#define ARM_AT91_AT91RSTREG_H
30108983Simp
31108983Simp#define	RST_CR		0x0	/* Control Register */
32108983Simp#define	RST_SR		0x4	/* Status Register */
33108983Simp#define	RST_MR		0x8	/* Mode Register */
34108983Simp
35108983Simp/* RST_CR */
36126905Scperciva#define	RST_CR_PROCRST		(1<<0)
37108983Simp#define	RST_CR_PERRST		(1<<2)
38108983Simp#define	RST_CR_EXTRST		(1<<3)
39108983Simp#define	RST_CR_KEY		(0xa5<<24)
40108983Simp
41108983Simp/* RST_SR */
42108983Simp#define	RST_SR_SRCMP		(1<<17)	/* Software Reset in progress */
43108983Simp#define	RST_SR_NRSTL		(1<<16)	/* NRST pin level at MCK */
44108983Simp#define	RST_SR_URSTS		(1<<0)	/* NRST pin has been active */
45108983Simp
46108983Simp#define	RST_SR_RST_POW		(0<<8)	/* General (Power On) reset */
47108983Simp#define	RST_SR_RST_WAKE		(1<<8)	/* Wake-up reset */
48108983Simp#define	RST_SR_RST_WDT		(2<<8)	/* Watchdog reset */
49108983Simp#define	RST_SR_RST_SOFT		(3<<8)	/* Software  reset */
50108983Simp#define	RST_SR_RST_USR		(4<<8)	/* User (External) reset */
51139281Sbrueffer#define	RST_SR_RST_MASK		(7<<8)	/* User (External) reset */
52108983Simp
53108983Simp/* RST_MR */
54108983Simp#define	RST_MR_URSTEN		(1<<0)	/* User reset enable */
55108983Simp#define	RST_MR_URSIEN		(1<<4)	/* User interrupt enable */
56108983Simp#define	RST_MR_ERSTL(x)		((x)<<8) /* External reset length */
57108983Simp#define	RST_MR_KEY		(0xa5<<24)
58108983Simp
59108983Simp#endif /* ARM_AT91_AT91RSTREG_H */
60139281Sbrueffer