1228753Smm/*- 2228753Smm * Copyright (c) 2009 Greg Ansley. All rights reserved. 3228753Smm * 4228753Smm * Redistribution and use in source and binary forms, with or without 5228753Smm * modification, are permitted provided that the following conditions 6228753Smm * are met: 7228753Smm * 1. Redistributions of source code must retain the above copyright 8228753Smm * notice, this list of conditions and the following disclaimer. 9228753Smm * 2. Redistributions in binary form must reproduce the above copyright 10228753Smm * notice, this list of conditions and the following disclaimer in the 11228753Smm * documentation and/or other materials provided with the distribution. 12228753Smm * 13228753Smm * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14228753Smm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15228753Smm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16228753Smm * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17228753Smm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18228753Smm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19228753Smm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20228753Smm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21228753Smm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22228753Smm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23228753Smm * SUCH DAMAGE. 24228753Smm */ 25228753Smm 26228753Smm/* $FreeBSD$ */ 27228753Smm 28228753Smm#ifndef ARM_AT91_AT91_RSTREG_H 29228753Smm#define ARM_AT91_AT91_RSTREG_H 30228753Smm 31228753Smm#define RST_CR 0x0 /* Control Register */ 32228753Smm#define RST_SR 0x4 /* Status Register */ 33228753Smm#define RST_MR 0x8 /* Mode Register */ 34228753Smm 35228753Smm/* RST_CR */ 36228753Smm#define RST_CR_PROCRST (1<<0) 37228753Smm#define RST_CR_PERRST (1<<2) 38228753Smm#define RST_CR_EXTRST (1<<3) 39228753Smm#define RST_CR_KEY (0xa5<<24) 40228753Smm 41228753Smm/* RST_SR */ 42228753Smm#define RST_SR_SRCMP (1<<17) /* Software Reset in progress */ 43228753Smm#define RST_SR_NRSTL (1<<16) /* NRST pin level at MCK */ 44228753Smm#define RST_SR_URSTS (1<<0) /* NRST pin has been active */ 45228753Smm 46228753Smm#define RST_SR_RST_POW (0<<8) /* General (Power On) reset */ 47228753Smm#define RST_SR_RST_WAKE (1<<8) /* Wake-up reset */ 48228753Smm#define RST_SR_RST_WDT (2<<8) /* Watchdog reset */ 49228753Smm#define RST_SR_RST_SOFT (3<<8) /* Software reset */ 50228753Smm#define RST_SR_RST_USR (4<<8) /* User (External) reset */ 51228753Smm#define RST_SR_RST_MASK (7<<8) /* User (External) reset */ 52228753Smm 53228753Smm/* RST_MR */ 54228753Smm#define RST_MR_URSTEN (1<<0) /* User reset enable */ 55228753Smm#define RST_MR_URSIEN (1<<4) /* User interrupt enable */ 56228753Smm#define RST_MR_ERSTL(x) ((x)<<8) /* External reset length */ 57228753Smm#define RST_MR_KEY (0xa5<<24) 58228753Smm 59228753Smm#ifndef __ASSEMBLER__ 60228753Smmvoid at91_rst_cpu_reset(void); 61228753Smm#endif 62228753Smm 63228753Smm#endif /* ARM_AT91_AT91_RSTREG_H */ 64228753Smm