at91_pmcreg.h revision 185265
1/*- 2 * Copyright (c) 2005 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* $FreeBSD: head/sys/arm/at91/at91_pmcreg.h 185265 2008-11-25 00:13:26Z imp $ */ 27 28#ifndef ARM_AT91_AT91_PMCREG_H 29#define ARM_AT91_AT91_PMCREG_H 30 31/* Registers */ 32#define PMC_SCER 0x00 /* System Clock Enable Register */ 33#define PMC_SCDR 0x04 /* System Clock Disable Register */ 34#define PMC_SCSR 0x08 /* System Clock Status Register */ 35 /* 0x0c reserved */ 36#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ 37#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ 38#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 39 /* 0x1c reserved */ 40#define CKGR_MOR 0x20 /* Main Oscillator Register */ 41#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */ 42#define CKGR_PLLAR 0x28 /* PLL A Register */ 43#define CKGR_PLLBR 0x2c /* PLL B Register */ 44#define PMC_MCKR 0x30 /* Master Clock Register */ 45 /* 0x34 reserved */ 46 /* 0x38 reserved */ 47 /* 0x3c reserved */ 48#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */ 49#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */ 50#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */ 51#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */ 52 /* 0x50 reserved */ 53 /* 0x54 reserved */ 54 /* 0x58 reserved */ 55 /* 0x5c reserved */ 56#define PMC_IER 0x60 /* Interrupt Enable Register */ 57#define PMC_IDR 0x64 /* Interrupt Disable Register */ 58#define PMC_SR 0x68 /* Status Register */ 59#define PMC_IMR 0x6c /* Interrupt Mask Register */ 60 61/* PMC System Clock Enable Register */ 62/* PMC System Clock Disable Register */ 63/* PMC System Clock StatusRegister */ 64#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */ 65#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */ 66#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */ 67#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */ 68#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */ 69#define PMC_SCER_PCK1 (1UL << 10) /* PCK1: Programmable Clock out en */ 70#define PMC_SCER_PCK2 (1UL << 11) /* PCK2: Programmable Clock out en */ 71#define PMC_SCER_PCK3 (1UL << 12) /* PCK3: Programmable Clock out en */ 72 73/* PMC Peripheral Clock Enable Register */ 74/* PMC Peripheral Clock Disable Register */ 75/* PMC Peripheral Clock Status Register */ 76/* Each bit here is 1 << peripheral number to enable/disable/status */ 77 78/* PMC Clock Generator Main Oscillator Register */ 79#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */ 80#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */ 81#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */ 82 83/* PMC Clock Generator Main Clock Frequency Register */ 84#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */ 85#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */ 86 87/* PMC Interrupt Enable Register */ 88/* PMC Interrupt Disable Register */ 89/* PMC Status Register */ 90/* PMC Interrupt Mask Register */ 91#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */ 92#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */ 93#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */ 94#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */ 95#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */ 96#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */ 97#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */ 98#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */ 99 100/* 101 * PLL input frequency spec sheet says it must be between 1MHz and 32MHz, 102 * but it works down as low as 100kHz, a frequency necessary for some 103 * output frequencies to work. 104 */ 105#define PMC_PLL_MIN_IN_FREQ 100000 106#define PMC_PLL_MAX_IN_FREQ 32000000 107 108/* 109 * PLL Max output frequency is 240MHz. The errata says 180MHz is the max 110 * for some revisions of this part. Be more permissive and optimistic. 111 */ 112#define PMC_PLL_MAX_OUT_FREQ 240000000 113 114#define PMC_PLL_MULT_MIN 2 115#define PMC_PLL_MULT_MAX 2048 116 117#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */ 118 119#define PMC_PLL_FAST_THRESH 155000000 120 121#endif /* ARM_AT91_AT91_PMCREG_H */ 122