at91_pmcreg.h revision 239167
19751Smdoerr/*- 29751Smdoerr * Copyright (c) 2005 M. Warner Losh. All rights reserved. 310049Sgoetz * 49751Smdoerr * Redistribution and use in source and binary forms, with or without 59751Smdoerr * modification, are permitted provided that the following conditions 69751Smdoerr * are met: 79751Smdoerr * 1. Redistributions of source code must retain the above copyright 89751Smdoerr * notice, this list of conditions and the following disclaimer. 99751Smdoerr * 2. Redistributions in binary form must reproduce the above copyright 109751Smdoerr * notice, this list of conditions and the following disclaimer in the 119751Smdoerr * documentation and/or other materials provided with the distribution. 129751Smdoerr * 139751Smdoerr * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 149751Smdoerr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 159751Smdoerr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 169751Smdoerr * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 179751Smdoerr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 189751Smdoerr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 199751Smdoerr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 209751Smdoerr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 219751Smdoerr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 229751Smdoerr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 239751Smdoerr * SUCH DAMAGE. 249751Smdoerr */ 259751Smdoerr 269751Smdoerr/* $FreeBSD: head/sys/arm/at91/at91_pmcreg.h 239167 2012-08-10 04:47:20Z imp $ */ 279751Smdoerr 289751Smdoerr#ifndef ARM_AT91_AT91_PMCREG_H 299751Smdoerr#define ARM_AT91_AT91_PMCREG_H 309751Smdoerr 319751Smdoerr/* Registers */ 329751Smdoerr#define PMC_SCER 0x00 /* System Clock Enable Register */ 339751Smdoerr#define PMC_SCDR 0x04 /* System Clock Disable Register */ 349751Smdoerr#define PMC_SCSR 0x08 /* System Clock Status Register */ 359751Smdoerr /* 0x0c reserved */ 369751Smdoerr#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ 379751Smdoerr#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ 389751Smdoerr#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 399751Smdoerr#define CKGR_UCKR 0x1c /* UTMI Clock Configuration Register */ 409751Smdoerr#define CKGR_MOR 0x20 /* Main Oscillator Register */ 419751Smdoerr#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */ 429751Smdoerr#define CKGR_PLLAR 0x28 /* PLL A Register */ 439751Smdoerr#define CKGR_PLLBR 0x2c /* PLL B Register */ 449751Smdoerr#define PMC_MCKR 0x30 /* Master Clock Register */ 459751Smdoerr /* 0x34 reserved */ 469751Smdoerr#define PMC_USB 0x38 /* USB Clock Register */ 479751Smdoerr /* 0x3c reserved */ 489751Smdoerr#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */ 499751Smdoerr#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */ 509751Smdoerr#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */ 519751Smdoerr#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */ 529751Smdoerr /* 0x50 reserved */ 539751Smdoerr /* 0x54 reserved */ 549751Smdoerr /* 0x58 reserved */ 559751Smdoerr /* 0x5c reserved */ 569751Smdoerr#define PMC_IER 0x60 /* Interrupt Enable Register */ 579751Smdoerr#define PMC_IDR 0x64 /* Interrupt Disable Register */ 589751Smdoerr#define PMC_SR 0x68 /* Status Register */ 599751Smdoerr#define PMC_IMR 0x6c /* Interrupt Mask Register */ 609751Smdoerr /* 0x70 reserved */ 619751Smdoerr /* 0x74 reserved */ 629751Smdoerr /* 0x78 reserved */ 639751Smdoerr /* 0x7c reserved */ 649751Smdoerr#define PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ 659751Smdoerr 669751Smdoerr/* PMC System Clock Enable Register */ 679751Smdoerr/* PMC System Clock Disable Register */ 689751Smdoerr/* PMC System Clock StatusRegister */ 699751Smdoerr#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */ 709751Smdoerr#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */ 719751Smdoerr#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */ 729751Smdoerr#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */ 739751Smdoerr#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */ 749751Smdoerr#define PMC_SCER_PCK1 (1UL << 9) /* PCK1: Programmable Clock out en */ 759751Smdoerr#define PMC_SCER_PCK2 (1UL << 10) /* PCK2: Programmable Clock out en */ 769751Smdoerr#define PMC_SCER_PCK3 (1UL << 11) /* PCK3: Programmable Clock out en */ 779751Smdoerr#define PMC_SCER_UHP_SAM9 (1UL << 6) /* UHP: USB Host Port Clock Enable */ 789751Smdoerr#define PMC_SCER_UDP_SAM9 (1UL << 7) /* UDP: USB Device Port Clock Enable */ 799751Smdoerr 809751Smdoerr/* PMC Peripheral Clock Enable Register */ 819751Smdoerr/* PMC Peripheral Clock Disable Register */ 829751Smdoerr/* PMC Peripheral Clock Status Register */ 839751Smdoerr/* Each bit here is 1 << peripheral number to enable/disable/status */ 849751Smdoerr 859751Smdoerr/* PMC UTMI Clock Configuration Register */ 869751Smdoerr#define CKGR_UCKR_BIASEN (1UL << 24) 879751Smdoerr#define CKGR_UCKR_UPLLEN (1UL << 16) 889751Smdoerr 899751Smdoerr/* PMC Clock Generator Main Oscillator Register */ 909751Smdoerr#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */ 919751Smdoerr#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */ 929751Smdoerr#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */ 939751Smdoerr 949751Smdoerr/* PMC Clock Generator Main Clock Frequency Register */ 959751Smdoerr#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */ 969751Smdoerr#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */ 979751Smdoerr 989751Smdoerr/* PMC Clock Generator Master Clock Register */ 999751Smdoerr#define PMC_MCKR_PDIV (1 << 12) /* SAM9G20 Only */ 1009751Smdoerr#define PMC_MCKR_PLLADIV2 (1 << 12) /* SAM9G45 Only */ 1019751Smdoerr#define PMC_MCKR_CSS_MASK (3 << 0) 1029751Smdoerr#define PMC_MCKR_MDIV_MASK (3 << 8) 1039751Smdoerr#define PMC_MCKR_PRES_MASK (7 << 2) 1049751Smdoerr 1059751Smdoerr/* PMC USB Clock Register */ 1069751Smdoerr#define PMC_USB_USBDIV(n) (((n) & 0x0F) << 8) 1079751Smdoerr#define PMC_USB_USBS (1 << 0) 1089751Smdoerr 1099751Smdoerr/* PMC Interrupt Enable Register */ 1109751Smdoerr/* PMC Interrupt Disable Register */ 1119751Smdoerr/* PMC Status Register */ 1129751Smdoerr/* PMC Interrupt Mask Register */ 1139751Smdoerr#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */ 1149751Smdoerr#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */ 1159751Smdoerr#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */ 1169751Smdoerr#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */ 1179751Smdoerr#define PMC_IER_LOCKU (1UL << 6) /* UPLL Locked */ 1189751Smdoerr#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */ 1199751Smdoerr#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */ 1209751Smdoerr#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */ 1219751Smdoerr#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */ 1229751Smdoerr 1239751Smdoerr/* 1249751Smdoerr * PLL input frequency spec sheet says it must be between 1MHz and 32MHz, 1259751Smdoerr * but it works down as low as 100kHz, a frequency necessary for some 1269751Smdoerr * output frequencies to work. 1279751Smdoerr */ 1289751Smdoerr#define PMC_PLL_MIN_IN_FREQ 100000 1299751Smdoerr#define PMC_PLL_MAX_IN_FREQ 32000000 1309751Smdoerr 1319751Smdoerr/* 1329751Smdoerr * PLL Max output frequency is 240MHz. The errata says 180MHz is the max 1339751Smdoerr * for some revisions of this part. Be more permissive and optimistic. 1349751Smdoerr */ 1359751Smdoerr#define PMC_PLL_MAX_OUT_FREQ 240000000 1369751Smdoerr 1379751Smdoerr#define PMC_PLL_MULT_MIN 2 1389751Smdoerr#define PMC_PLL_MULT_MAX 2048 1399751Smdoerr 1409751Smdoerr#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */ 1419751Smdoerr 1429751Smdoerr#define PMC_PLL_FAST_THRESH 155000000 1439751Smdoerr 1449751Smdoerr#endif /* ARM_AT91_AT91_PMCREG_H */ 1459751Smdoerr