sys_machdep.c revision 263036 
1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the University nor the names of its contributors
14 *    may be used to endorse or promote products derived from this software
15 *    without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 *	from: @(#)sys_machdep.c	5.5 (Berkeley) 1/19/91
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/arm/sys_machdep.c 263036 2014-03-11 17:08:45Z imp $");
34
35#include "opt_capsicum.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/capability.h>
40#include <sys/proc.h>
41#include <sys/sysproto.h>
42#include <sys/syscall.h>
43#include <sys/sysent.h>
44
45#include <machine/sysarch.h>
46
47#ifndef _SYS_SYSPROTO_H_
48struct sysarch_args {
49	int op;
50	char *parms;
51};
52#endif
53
54/* Prototypes */
55static int arm32_sync_icache (struct thread *, void *);
56static int arm32_drain_writebuf(struct thread *, void *);
57
58static int
59arm32_sync_icache(struct thread *td, void *args)
60{
61	struct arm_sync_icache_args ua;
62	int error;
63
64	if ((error = copyin(args, &ua, sizeof(ua))) != 0)
65		return (error);
66
67	cpu_icache_sync_range(ua.addr, ua.len);
68
69	td->td_retval[0] = 0;
70	return (0);
71}
72
73static int
74arm32_drain_writebuf(struct thread *td, void *args)
75{
76	/* No args. */
77
78	td->td_retval[0] = 0;
79	cpu_drain_writebuf();
80	return (0);
81}
82
83static int
84arm32_set_tp(struct thread *td, void *args)
85{
86
87	if (td != curthread)
88		td->td_md.md_tp = (register_t)args;
89	else
90#ifndef ARM_TP_ADDRESS
91		set_tls(args);
92#else
93		*(register_t *)ARM_TP_ADDRESS = (register_t)args;
94#endif
95	return (0);
96}
97
98static int
99arm32_get_tp(struct thread *td, void *args)
100{
101
102	if (td != curthread)
103		td->td_retval[0] = td->td_md.md_tp;
104	else
105#ifndef ARM_TP_ADDRESS
106		td->td_retval[0] = (register_t)get_tls();
107#else
108		td->td_retval[0] = *(register_t *)ARM_TP_ADDRESS;
109#endif
110	return (0);
111}
112
113int
114sysarch(td, uap)
115	struct thread *td;
116	register struct sysarch_args *uap;
117{
118	int error;
119
120#ifdef CAPABILITY_MODE
121	/*
122	 * When adding new operations, add a new case statement here to
123	 * explicitly indicate whether or not the operation is safe to
124	 * perform in capability mode.
125	 */
126	if (IN_CAPABILITY_MODE(td)) {
127		switch (uap->op) {
128		case ARM_SYNC_ICACHE:
129		case ARM_DRAIN_WRITEBUF:
130		case ARM_SET_TP:
131		case ARM_GET_TP:
132			break;
133
134		default:
135#ifdef KTRACE
136			if (KTRPOINT(td, KTR_CAPFAIL))
137				ktrcapfail(CAPFAIL_SYSCALL, NULL, NULL);
138#endif
139			return (ECAPMODE);
140		}
141	}
142#endif
143
144	switch (uap->op) {
145	case ARM_SYNC_ICACHE:
146		error = arm32_sync_icache(td, uap->parms);
147		break;
148	case ARM_DRAIN_WRITEBUF:
149		error = arm32_drain_writebuf(td, uap->parms);
150		break;
151	case ARM_SET_TP:
152		error = arm32_set_tp(td, uap->parms);
153		break;
154	case ARM_GET_TP:
155		error = arm32_get_tp(td, uap->parms);
156		break;
157	default:
158		error = EINVAL;
159		break;
160	}
161	return (error);
162}
163