swtch.S revision 138856
1/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2 3/* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37/* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 * 79 */ 80 81#include "assym.s" 82 83#include <machine/asm.h> 84#include <machine/asmacros.h> 85#include <machine/armreg.h> 86__FBSDID("$FreeBSD: head/sys/arm/arm/swtch.S 138856 2004-12-14 18:45:05Z cognet $"); 87 88 89/* 90 * New experimental definitions of IRQdisable and IRQenable 91 * These keep FIQ's enabled since FIQ's are special. 92 */ 93 94#define DOMAIN_CLIENT 0x01 95#define IRQdisable \ 96 mrs r14, cpsr ; \ 97 orr r14, r14, #(I32_bit) ; \ 98 msr cpsr_c, r14 ; \ 99 100#define IRQenable \ 101 mrs r14, cpsr ; \ 102 bic r14, r14, #(I32_bit) ; \ 103 msr cpsr_c, r14 ; \ 104 105/* 106 * These are used for switching the translation table/DACR. 107 * Since the vector page can be invalid for a short time, we must 108 * disable both regular IRQs *and* FIQs. 109 * 110 * XXX: This is not necessary if the vector table is relocated. 111 */ 112#define IRQdisableALL \ 113 mrs r14, cpsr ; \ 114 orr r14, r14, #(I32_bit | F32_bit) ; \ 115 msr cpsr_c, r14 116 117#define IRQenableALL \ 118 mrs r14, cpsr ; \ 119 bic r14, r14, #(I32_bit | F32_bit) ; \ 120 msr cpsr_c, r14 121 122.Lcurpcb: 123 .word _C_LABEL(__pcpu) + PC_CURPCB 124.Lcpufuncs: 125 .word _C_LABEL(cpufuncs) 126.Lblock_userspace_access: 127 .word _C_LABEL(block_userspace_access) 128.Lcpu_do_powersave: 129 .word _C_LABEL(cpu_do_powersave) 130ENTRY(cpu_throw) 131 mov r5, r1 132 133 /* 134 * r5 = newtd 135 */ 136 137 ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 138 139 /* Switch to lwp0 context */ 140 141 ldr r9, .Lcpufuncs 142 mov lr, pc 143 ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 144 ldr r0, [r7, #(PCB_PL1VEC)] 145 ldr r1, [r7, #(PCB_DACR)] 146 /* 147 * r0 = Pointer to L1 slot for vector_page (or NULL) 148 * r1 = lwp0's DACR 149 * r5 = lwp0 150 * r6 = exit func 151 * r7 = lwp0's PCB 152 * r9 = cpufuncs 153 */ 154 155 /* 156 * Ensure the vector table is accessible by fixing up lwp0's L1 157 */ 158 cmp r0, #0 /* No need to fixup vector table? */ 159 ldrne r3, [r0] /* But if yes, fetch current value */ 160 ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 161 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 162 cmpne r3, r2 /* Stuffing the same value? */ 163 strne r2, [r0] /* Store if not. */ 164 165#ifdef PMAP_INCLUDE_PTE_SYNC 166 /* 167 * Need to sync the cache to make sure that last store is 168 * visible to the MMU. 169 */ 170 movne r1, #4 171 movne lr, pc 172 ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 173#endif /* PMAP_INCLUDE_PTE_SYNC */ 174 175 /* 176 * Note: We don't do the same optimisation as cpu_switch() with 177 * respect to avoiding flushing the TLB if we're switching to 178 * the same L1 since this process' VM space may be about to go 179 * away, so we don't want *any* turds left in the TLB. 180 */ 181 182 /* Switch the memory to the new process */ 183 ldr r0, [r7, #(PCB_PAGEDIR)] 184 mov lr, pc 185 ldr pc, [r9, #CF_CONTEXT_SWITCH] 186 187 /* Restore all the save registers */ 188#ifndef __XSCALE__ 189 add r1, r7, #PCB_R8 190 ldmia r1, {r8-r13} 191#else 192 ldr r8, [r7, #(PCB_R8)] 193 ldr r9, [r7, #(PCB_R9)] 194 ldr r10, [r7, #(PCB_R10)] 195 ldr r11, [r7, #(PCB_R11)] 196 ldr r12, [r7, #(PCB_R12)] 197 ldr r13, [r7, #(PCB_SP)] 198#endif 199 200 /* We have a new curthread now so make a note it */ 201 ldr r6, .Lcurthread 202 str r5, [r6] 203 204 /* Hook in a new pcb */ 205 ldr r6, .Lcurpcb 206 str r7, [r6] 207 208 ldmfd sp!, {r4-r7, pc} 209 210ENTRY(cpu_switch) 211 stmfd sp!, {r4-r7, lr} 212 213.Lswitch_resume: 214 /* rem: r0 = old lwp */ 215 /* rem: interrupts are disabled */ 216 217#ifdef MULTIPROCESSOR 218 /* XXX use curcpu() */ 219 ldr r2, .Lcpu_info_store 220 str r2, [r6, #(L_CPU)] 221#endif 222 223 /* Process is now on a processor. */ 224 225 /* We have a new curthread now so make a note it */ 226 ldr r7, .Lcurthread 227 str r1, [r7] 228 229 /* Hook in a new pcb */ 230 ldr r7, .Lcurpcb 231 ldr r2, [r1, #TD_PCB] 232 str r2, [r7] 233 234 /* rem: r1 = new process */ 235 /* rem: interrupts are enabled */ 236 237 /* Stage two : Save old context */ 238 239 /* Get the user structure for the old lwp. */ 240 ldr r2, [r0, #(TD_PCB)] 241 242 /* Save all the registers in the old lwp's pcb */ 243#ifndef __XSCALE__ 244 add r7, r2, #(PCB_R8) 245 stmia r7, {r8-r13} 246#else 247 strd r8, [r2, #(PCB_R8)] 248 strd r10, [r2, #(PCB_R10)] 249 strd r12, [r2, #(PCB_R12)] 250#endif 251 252 /* 253 * NOTE: We can now use r8-r13 until it is time to restore 254 * them for the new process. 255 */ 256 257 258 /* Get the user structure for the new process in r9 */ 259 ldr r9, [r1, #(TD_PCB)] 260 261 /* r1 now free! */ 262 263 mrs r3, cpsr 264 /* 265 * We can do that, since 266 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 267 */ 268 orr r8, r3, #(PSR_UND32_MODE) 269 msr cpsr_c, r8 270 271 str sp, [r2, #(PCB_UND_SP)] 272 273 msr cpsr_c, r3 /* Restore the old mode */ 274 /* rem: r8 = old PCB */ 275 /* rem: r9 = new PCB */ 276 /* rem: interrupts are enabled */ 277 278 /* What else needs to be saved Only FPA stuff when that is supported */ 279 280 /* Third phase : restore saved context */ 281 282 /* rem: r8 = old PCB */ 283 /* rem: r9 = new PCB */ 284 /* rem: interrupts are enabled */ 285 286 ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */ 287 mov r2, #DOMAIN_CLIENT 288 cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 289 beq .Lcs_context_switched /* Yup. Don't flush cache */ 290 mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 291 /* 292 * Get the new L1 table pointer into r11. If we're switching to 293 * an LWP with the same address space as the outgoing one, we can 294 * skip the cache purge and the TTB load. 295 * 296 * To avoid data dep stalls that would happen anyway, we try 297 * and get some useful work done in the mean time. 298 */ 299 mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 300 ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 301 302 303 teq r10, r11 /* Same L1? */ 304 cmpeq r0, r5 /* Same DACR? */ 305 beq .Lcs_context_switched /* yes! */ 306 307 /* 308 * Definately need to flush the cache. 309 */ 310 311 ldr r1, .Lcpufuncs 312 mov lr, pc 313 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 314.Lcs_cache_purge_skipped: 315 /* rem: r4 = &block_userspace_access */ 316 /* rem: r6 = new lwp */ 317 /* rem: r9 = new PCB */ 318 /* rem: r10 = old L1 */ 319 /* rem: r11 = new L1 */ 320 321 mov r2, #0x00000000 322 ldr r7, [r9, #(PCB_PL1VEC)] 323 324 /* 325 * Ensure the vector table is accessible by fixing up the L1 326 */ 327 cmp r7, #0 /* No need to fixup vector table? */ 328 ldrne r2, [r7] /* But if yes, fetch current value */ 329 ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 330 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 331 cmpne r2, r0 /* Stuffing the same value? */ 332#ifndef PMAP_INCLUDE_PTE_SYNC 333 strne r0, [r7] /* Nope, update it */ 334#else 335 beq .Lcs_same_vector 336 str r0, [r7] /* Otherwise, update it */ 337 338 /* 339 * Need to sync the cache to make sure that last store is 340 * visible to the MMU. 341 */ 342 ldr r2, .Lcpufuncs 343 mov r0, r7 344 mov r1, #4 345 mov lr, pc 346 ldr pc, [r2, #CF_DCACHE_WB_RANGE] 347 348.Lcs_same_vector: 349#endif /* PMAP_INCLUDE_PTE_SYNC */ 350 351 cmp r10, r11 /* Switching to the same L1? */ 352 ldr r10, .Lcpufuncs 353 beq .Lcs_same_l1 /* Yup. */ 354 /* 355 * Do a full context switch, including full TLB flush. 356 */ 357 mov r0, r11 358 mov lr, pc 359 ldr pc, [r10, #CF_CONTEXT_SWITCH] 360 361 b .Lcs_context_switched 362 363 /* 364 * We're switching to a different process in the same L1. 365 * In this situation, we only need to flush the TLB for the 366 * vector_page mapping, and even then only if r7 is non-NULL. 367 */ 368.Lcs_same_l1: 369 cmp r7, #0 370 movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 371 movne lr, pc 372 ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 373 /* 374 * We can do that, since 375 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 376 */ 377 378.Lcs_context_switched: 379 380 /* XXXSCW: Safe to re-enable FIQs here */ 381 382 /* rem: r9 = new PCB */ 383 384 mrs r3, cpsr 385 /* 386 * We can do that, since 387 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 388 */ 389 orr r2, r3, #(PSR_UND32_MODE) 390 msr cpsr_c, r2 391 392 ldr sp, [r9, #(PCB_UND_SP)] 393 394 msr cpsr_c, r3 /* Restore the old mode */ 395 /* Restore all the save registers */ 396#ifndef __XSCALE__ 397 add r7, r9, #PCB_R8 398 ldmia r7, {r8-r13} 399 sub r7, r7, #PCB_R8 /* restore PCB pointer */ 400#else 401 mov r7, r9 402 ldr r8, [r7, #(PCB_R8)] 403 ldr r9, [r7, #(PCB_R9)] 404 ldr r10, [r7, #(PCB_R10)] 405 ldr r11, [r7, #(PCB_R11)] 406 ldr r12, [r7, #(PCB_R12)] 407 ldr r13, [r7, #(PCB_SP)] 408#endif 409 410 /* rem: r6 = new lwp */ 411 /* rem: r7 = new pcb */ 412 413#ifdef ARMFPE 414 add r0, r7, #(USER_SIZE) & 0x00ff 415 add r0, r0, #(USER_SIZE) & 0xff00 416 bl _C_LABEL(arm_fpe_core_changecontext) 417#endif 418 419 /* rem: r5 = new lwp's proc */ 420 /* rem: r6 = new lwp */ 421 /* rem: r7 = new PCB */ 422 423.Lswitch_return: 424 425 /* 426 * Pull the registers that got pushed when either savectx() or 427 * cpu_switch() was called and return. 428 */ 429 ldmfd sp!, {r4-r7, pc} 430#ifdef DIAGNOSTIC 431.Lswitch_bogons: 432 adr r0, .Lswitch_panic_str 433 bl _C_LABEL(panic) 4341: nop 435 b 1b 436 437.Lswitch_panic_str: 438 .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n" 439#endif 440ENTRY(savectx) 441 RET 442ENTRY(fork_trampoline) 443 mov r1, r5 444 mov r2, sp 445 mov r0, r4 446 mov fp, #0 447 bl _C_LABEL(fork_exit) 448 /* Kill irq"s */ 449 mrs r0, cpsr 450 orr r0, r0, #(I32_bit) 451 msr cpsr_c, r0 452 PULLFRAME 453 454 movs pc, lr /* Exit */ 455 456AST_LOCALS 457