swtch-v6.S revision 137341
1/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2 3/* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37/* 38 * Copyright (c) 1994-1998 Mark Brinicombe. 39 * Copyright (c) 1994 Brini. 40 * All rights reserved. 41 * 42 * This code is derived from software written for Brini by Mark Brinicombe 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Brini. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * RiscBSD kernel project 72 * 73 * cpuswitch.S 74 * 75 * cpu switching functions 76 * 77 * Created : 15/10/94 78 * 79 */ 80 81#include "assym.s" 82 83#include <machine/asm.h> 84#include <machine/asmacros.h> 85#include <machine/armreg.h> 86__FBSDID("$FreeBSD: head/sys/arm/arm/swtch.S 137341 2004-11-07 16:51:33Z cognet $"); 87 88 89/* 90 * New experimental definitions of IRQdisable and IRQenable 91 * These keep FIQ's enabled since FIQ's are special. 92 */ 93 94#define DOMAIN_CLIENT 0x01 95#define IRQdisable \ 96 mrs r14, cpsr ; \ 97 orr r14, r14, #(I32_bit) ; \ 98 msr cpsr_c, r14 ; \ 99 100#define IRQenable \ 101 mrs r14, cpsr ; \ 102 bic r14, r14, #(I32_bit) ; \ 103 msr cpsr_c, r14 ; \ 104 105/* 106 * These are used for switching the translation table/DACR. 107 * Since the vector page can be invalid for a short time, we must 108 * disable both regular IRQs *and* FIQs. 109 * 110 * XXX: This is not necessary if the vector table is relocated. 111 */ 112#define IRQdisableALL \ 113 mrs r14, cpsr ; \ 114 orr r14, r14, #(I32_bit | F32_bit) ; \ 115 msr cpsr_c, r14 116 117#define IRQenableALL \ 118 mrs r14, cpsr ; \ 119 bic r14, r14, #(I32_bit | F32_bit) ; \ 120 msr cpsr_c, r14 121 122.Lcurpcb: 123 .word _C_LABEL(__pcpu) + PC_CURPCB 124.Lcpufuncs: 125 .word _C_LABEL(cpufuncs) 126.Lblock_userspace_access: 127 .word _C_LABEL(block_userspace_access) 128.Lcpu_do_powersave: 129 .word _C_LABEL(cpu_do_powersave) 130ENTRY(cpu_throw) 131 mov r4, r0 132 mov r5, r1 133 134 /* 135 * r4 = oldtd 136 * r5 = newtd 137 */ 138 139 ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 140 141 /* Switch to lwp0 context */ 142 143 ldr r9, .Lcpufuncs 144 mov lr, pc 145 ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 146 ldr r0, [r7, #(PCB_PL1VEC)] 147 ldr r1, [r7, #(PCB_DACR)] 148 /* 149 * r0 = Pointer to L1 slot for vector_page (or NULL) 150 * r1 = lwp0's DACR 151 * r4 = lwp we're switching from 152 * r5 = lwp0 153 * r6 = exit func 154 * r7 = lwp0's PCB 155 * r9 = cpufuncs 156 */ 157 158 /* 159 * Ensure the vector table is accessible by fixing up lwp0's L1 160 */ 161 cmp r0, #0 /* No need to fixup vector table? */ 162 ldrne r3, [r0] /* But if yes, fetch current value */ 163 ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 164 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 165 cmpne r3, r2 /* Stuffing the same value? */ 166 strne r2, [r0] /* Store if not. */ 167 168#ifdef PMAP_INCLUDE_PTE_SYNC 169 /* 170 * Need to sync the cache to make sure that last store is 171 * visible to the MMU. 172 */ 173 movne r1, #4 174 movne lr, pc 175 ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 176#endif /* PMAP_INCLUDE_PTE_SYNC */ 177 178 /* 179 * Note: We don't do the same optimisation as cpu_switch() with 180 * respect to avoiding flushing the TLB if we're switching to 181 * the same L1 since this process' VM space may be about to go 182 * away, so we don't want *any* turds left in the TLB. 183 */ 184 185 /* Switch the memory to the new process */ 186 ldr r0, [r7, #(PCB_PAGEDIR)] 187 mov lr, pc 188 ldr pc, [r9, #CF_CONTEXT_SWITCH] 189 190 /* Restore all the save registers */ 191#ifndef __XSCALE__ 192 add r1, r7, #PCB_R8 193 ldmia r1, {r8-r13} 194#else 195 ldr r8, [r7, #(PCB_R8)] 196 ldr r9, [r7, #(PCB_R9)] 197 ldr r10, [r7, #(PCB_R10)] 198 ldr r11, [r7, #(PCB_R11)] 199 ldr r12, [r7, #(PCB_R12)] 200 ldr r13, [r7, #(PCB_SP)] 201#endif 202 203 mov r0, #0x00000000 /* r5 = old lwp = NULL */ 204 mov r1, r5 205 b .Lswitch_resume 206 207ENTRY(cpu_switch) 208 stmfd sp!, {r4-r7, lr} 209 210.Lswitch_resume: 211 /* rem: r0 = old lwp */ 212 /* rem: interrupts are disabled */ 213 214#ifdef MULTIPROCESSOR 215 /* XXX use curcpu() */ 216 ldr r2, .Lcpu_info_store 217 str r2, [r6, #(L_CPU)] 218#endif 219 220 /* Process is now on a processor. */ 221 222 /* We have a new curthread now so make a note it */ 223 ldr r7, .Lcurthread 224 str r1, [r7] 225 226 /* Hook in a new pcb */ 227 ldr r7, .Lcurpcb 228 ldr r2, [r1, #TD_PCB] 229 str r2, [r7] 230 231 232 /* 233 * If the old lwp on entry to cpu_switch was zero then the 234 * process that called it was exiting. This means that we do 235 * not need to save the current context. Instead we can jump 236 * straight to restoring the context for the new process. 237 */ 238 teq r0, #0x00000000 239 beq .Lswitch_return 240 241 /* rem: r1 = new process */ 242 /* rem: interrupts are enabled */ 243 244 /* Stage two : Save old context */ 245 246 /* Get the user structure for the old lwp. */ 247 ldr r2, [r0, #(TD_PCB)] 248 249 /* Save all the registers in the old lwp's pcb */ 250#ifndef __XSCALE__ 251 add r7, r2, #(PCB_R8) 252 stmia r7, {r8-r13} 253#else 254 strd r8, [r2, #(PCB_R8)] 255 strd r10, [r2, #(PCB_R10)] 256 strd r12, [r2, #(PCB_R12)] 257#endif 258 259 /* 260 * NOTE: We can now use r8-r13 until it is time to restore 261 * them for the new process. 262 */ 263 264 /* Remember the old PCB. */ 265 mov r8, r2 266 267 268 /* Get the user structure for the new process in r9 */ 269 ldr r9, [r1, #(TD_PCB)] 270 271 /* r1 now free! */ 272 273 /* 274 * This can be optimised... We know we want to go from SVC32 275 * mode to UND32 mode 276 */ 277 mrs r3, cpsr 278 bic r2, r3, #(PSR_MODE) 279 orr r2, r2, #(PSR_UND32_MODE) 280 msr cpsr_c, r2 281 282 str sp, [r8, #(PCB_UND_SP)] 283 284 msr cpsr_c, r3 /* Restore the old mode */ 285 /* rem: r8 = old PCB */ 286 /* rem: r9 = new PCB */ 287 /* rem: interrupts are enabled */ 288 289 /* What else needs to be saved Only FPA stuff when that is supported */ 290 291 /* Third phase : restore saved context */ 292 293 /* rem: r8 = old PCB */ 294 /* rem: r9 = new PCB */ 295 /* rem: interrupts are enabled */ 296 297 /* 298 * Get the new L1 table pointer into r11. If we're switching to 299 * an LWP with the same address space as the outgoing one, we can 300 * skip the cache purge and the TTB load. 301 * 302 * To avoid data dep stalls that would happen anyway, we try 303 * and get some useful work done in the mean time. 304 */ 305 ldr r10, [r8, #(PCB_PAGEDIR)] /* r10 = old L1 */ 306 ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 307 308 309 310 ldr r0, [r8, #(PCB_DACR)] /* r0 = old DACR */ 311 ldr r5, [r9, #(PCB_DACR)] /* r1 = new DACR */ 312 313 teq r10, r11 /* Same L1? */ 314 cmpeq r0, r5 /* Same DACR? */ 315 beq .Lcs_context_switched /* yes! */ 316 ldr r4, .Lblock_userspace_access 317 318 mov r2, #DOMAIN_CLIENT 319 cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 320 321 beq .Lcs_cache_purge_skipped /* Yup. Don't flush cache */ 322 323 /* 324 * Definately need to flush the cache. 325 */ 326 327 /* 328 * Don't allow user space access between the purge and the switch. 329 */ 330 mov r2, #0x00000001 331 str r2, [r4] 332 333 ldr r1, .Lcpufuncs 334 mov lr, pc 335 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 336.Lcs_cache_purge_skipped: 337 /* rem: r4 = &block_userspace_access */ 338 /* rem: r6 = new lwp */ 339 /* rem: r9 = new PCB */ 340 /* rem: r10 = old L1 */ 341 /* rem: r11 = new L1 */ 342 343 mov r2, #0x00000000 344 ldr r7, [r9, #(PCB_PL1VEC)] 345 346 /* 347 * Interrupts are disabled so we can allow user space accesses again 348 * as none will occur until interrupts are re-enabled after the 349 * switch. 350 */ 351 str r2, [r4] 352 353 /* 354 * Ensure the vector table is accessible by fixing up the L1 355 */ 356 cmp r7, #0 /* No need to fixup vector table? */ 357 ldrne r2, [r7] /* But if yes, fetch current value */ 358 ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 359 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 360 cmpne r2, r0 /* Stuffing the same value? */ 361#ifndef PMAP_INCLUDE_PTE_SYNC 362 strne r0, [r7] /* Nope, update it */ 363#else 364 beq .Lcs_same_vector 365 str r0, [r7] /* Otherwise, update it */ 366 367 /* 368 * Need to sync the cache to make sure that last store is 369 * visible to the MMU. 370 */ 371 ldr r2, .Lcpufuncs 372 mov r0, r7 373 mov r1, #4 374 mov lr, pc 375 ldr pc, [r2, #CF_DCACHE_WB_RANGE] 376 377.Lcs_same_vector: 378#endif /* PMAP_INCLUDE_PTE_SYNC */ 379 380 cmp r10, r11 /* Switching to the same L1? */ 381 ldr r10, .Lcpufuncs 382 beq .Lcs_same_l1 /* Yup. */ 383 /* 384 * Do a full context switch, including full TLB flush. 385 */ 386 mov r0, r11 387 mov lr, pc 388 ldr pc, [r10, #CF_CONTEXT_SWITCH] 389 390 b .Lcs_context_switched 391 392 /* 393 * We're switching to a different process in the same L1. 394 * In this situation, we only need to flush the TLB for the 395 * vector_page mapping, and even then only if r7 is non-NULL. 396 */ 397.Lcs_same_l1: 398 cmp r7, #0 399 movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 400 movne lr, pc 401 ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 402 403.Lcs_context_switched: 404 405 /* XXXSCW: Safe to re-enable FIQs here */ 406 407 /* rem: r9 = new PCB */ 408 409 /* 410 * This can be optimised... We know we want to go from SVC32 411 * mode to UND32 mode 412 */ 413 mrs r3, cpsr 414 bic r2, r3, #(PSR_MODE) 415 orr r2, r2, #(PSR_UND32_MODE) 416 msr cpsr_c, r2 417 418 ldr sp, [r9, #(PCB_UND_SP)] 419 420 msr cpsr_c, r3 /* Restore the old mode */ 421 /* Restore all the save registers */ 422#ifndef __XSCALE__ 423 add r7, r9, #PCB_R8 424 ldmia r7, {r8-r13} 425 sub r7, r7, #PCB_R8 /* restore PCB pointer */ 426#else 427 mov r7, r9 428 ldr r8, [r7, #(PCB_R8)] 429 ldr r9, [r7, #(PCB_R9)] 430 ldr r10, [r7, #(PCB_R10)] 431 ldr r11, [r7, #(PCB_R11)] 432 ldr r12, [r7, #(PCB_R12)] 433 ldr r13, [r7, #(PCB_SP)] 434#endif 435 436 /* rem: r6 = new lwp */ 437 /* rem: r7 = new pcb */ 438 439#ifdef ARMFPE 440 add r0, r7, #(USER_SIZE) & 0x00ff 441 add r0, r0, #(USER_SIZE) & 0xff00 442 bl _C_LABEL(arm_fpe_core_changecontext) 443#endif 444 445 /* rem: r5 = new lwp's proc */ 446 /* rem: r6 = new lwp */ 447 /* rem: r7 = new PCB */ 448 449.Lswitch_return: 450 451 /* 452 * Pull the registers that got pushed when either savectx() or 453 * cpu_switch() was called and return. 454 */ 455 ldmfd sp!, {r4-r7, pc} 456#ifdef DIAGNOSTIC 457.Lswitch_bogons: 458 adr r0, .Lswitch_panic_str 459 bl _C_LABEL(panic) 4601: nop 461 b 1b 462 463.Lswitch_panic_str: 464 .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n" 465#endif 466ENTRY(savectx) 467 mov pc, lr 468ENTRY(fork_trampoline) 469 mov r1, r5 470 mov r2, sp 471 mov r0, r4 472 bl _C_LABEL(fork_exit) 473 /* Kill irq"s */ 474 mrs r0, cpsr 475 orr r0, r0, #(I32_bit) 476 msr cpsr_c, r0 477 PULLFRAME 478 479 movs pc, lr /* Exit */ 480 481AST_LOCALS 482