swtch-v6.S revision 239268
1129198Scognet/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37139735Simp/*- 38129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 39129198Scognet * Copyright (c) 1994 Brini. 40129198Scognet * All rights reserved. 41129198Scognet * 42129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 43129198Scognet * 44129198Scognet * Redistribution and use in source and binary forms, with or without 45129198Scognet * modification, are permitted provided that the following conditions 46129198Scognet * are met: 47129198Scognet * 1. Redistributions of source code must retain the above copyright 48129198Scognet * notice, this list of conditions and the following disclaimer. 49129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 50129198Scognet * notice, this list of conditions and the following disclaimer in the 51129198Scognet * documentation and/or other materials provided with the distribution. 52129198Scognet * 3. All advertising materials mentioning features or use of this software 53129198Scognet * must display the following acknowledgement: 54129198Scognet * This product includes software developed by Brini. 55129198Scognet * 4. The name of the company nor the name of the author may be used to 56129198Scognet * endorse or promote products derived from this software without specific 57129198Scognet * prior written permission. 58129198Scognet * 59129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69129198Scognet * SUCH DAMAGE. 70129198Scognet * 71129198Scognet * RiscBSD kernel project 72129198Scognet * 73129198Scognet * cpuswitch.S 74129198Scognet * 75129198Scognet * cpu switching functions 76129198Scognet * 77129198Scognet * Created : 15/10/94 78129198Scognet * 79129198Scognet */ 80129198Scognet 81137274Scognet#include "assym.s" 82137274Scognet 83129198Scognet#include <machine/asm.h> 84129198Scognet#include <machine/asmacros.h> 85129198Scognet#include <machine/armreg.h> 86129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/swtch.S 239268 2012-08-15 03:03:03Z gonzo $"); 87129198Scognet 88129198Scognet#define DOMAIN_CLIENT 0x01 89129198Scognet 90239268Sgonzo#ifdef _ARM_ARCH_6 91239268Sgonzo#define GET_PCPU(tmp) \ 92239268Sgonzo mrc p15, 0, tmp, c13, c0, 4; 93239268Sgonzo#else 94239268Sgonzo.Lcurpcpu: 95239268Sgonzo .word _C_LABEL(__pcpu) 96129198Scognet 97239268Sgonzo#define GET_PCPU(tmp) \ 98239268Sgonzo ldr tmp, .Lcurpcpu 99239268Sgonzo#endif 100129198Scognet 101129198Scognet.Lcpufuncs: 102129198Scognet .word _C_LABEL(cpufuncs) 103171780Scognet.Lblocked_lock: 104171780Scognet .word _C_LABEL(blocked_lock) 105239268Sgonzo 106135655ScognetENTRY(cpu_throw) 107135655Scognet mov r5, r1 108129198Scognet 109135655Scognet /* 110239268Sgonzo * r0 = oldtd 111137274Scognet * r5 = newtd 112135655Scognet */ 113129198Scognet 114239268Sgonzo GET_PCPU(r7) 115239268Sgonzo 116239268Sgonzo#ifdef ARM_VFP_SUPPORT 117239268Sgonzo /* 118239268Sgonzo * vfp_discard will clear pcpu->pc_vfpcthread, and modify 119239268Sgonzo * and modify the control as needed. 120239268Sgonzo */ 121239268Sgonzo ldr r4, [r7, #(PC_VFPCTHREAD)] /* this thread using vfp? */ 122239268Sgonzo cmp r0, r4 123239268Sgonzo bne 3f 124239268Sgonzo bl _C_LABEL(vfp_discard) /* yes, shut down vfp */ 125239268Sgonzo3: 126239268Sgonzo#endif /* ARM_VFP_SUPPORT */ 127239268Sgonzo 128137274Scognet ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 129239268Sgonzo 130135655Scognet /* Switch to lwp0 context */ 131135655Scognet 132135655Scognet ldr r9, .Lcpufuncs 133239268Sgonzo#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) 134135655Scognet mov lr, pc 135135655Scognet ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 136239268Sgonzo#endif 137135655Scognet ldr r0, [r7, #(PCB_PL1VEC)] 138135655Scognet ldr r1, [r7, #(PCB_DACR)] 139135655Scognet /* 140135655Scognet * r0 = Pointer to L1 slot for vector_page (or NULL) 141135655Scognet * r1 = lwp0's DACR 142135655Scognet * r5 = lwp0 143135655Scognet * r6 = exit func 144135655Scognet * r7 = lwp0's PCB 145135655Scognet * r9 = cpufuncs 146135655Scognet */ 147135655Scognet 148135655Scognet /* 149135655Scognet * Ensure the vector table is accessible by fixing up lwp0's L1 150135655Scognet */ 151135655Scognet cmp r0, #0 /* No need to fixup vector table? */ 152135655Scognet ldrne r3, [r0] /* But if yes, fetch current value */ 153135655Scognet ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 154135655Scognet mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 155135655Scognet cmpne r3, r2 /* Stuffing the same value? */ 156135655Scognet strne r2, [r0] /* Store if not. */ 157135655Scognet 158135655Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 159135655Scognet /* 160135655Scognet * Need to sync the cache to make sure that last store is 161135655Scognet * visible to the MMU. 162135655Scognet */ 163135655Scognet movne r1, #4 164135655Scognet movne lr, pc 165135655Scognet ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 166135655Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 167135655Scognet 168135655Scognet /* 169135655Scognet * Note: We don't do the same optimisation as cpu_switch() with 170135655Scognet * respect to avoiding flushing the TLB if we're switching to 171135655Scognet * the same L1 since this process' VM space may be about to go 172135655Scognet * away, so we don't want *any* turds left in the TLB. 173135655Scognet */ 174135655Scognet 175135655Scognet /* Switch the memory to the new process */ 176135655Scognet ldr r0, [r7, #(PCB_PAGEDIR)] 177135655Scognet mov lr, pc 178135655Scognet ldr pc, [r9, #CF_CONTEXT_SWITCH] 179135655Scognet 180135655Scognet /* Restore all the save registers */ 181172614Scognet#ifndef _ARM_ARCH_5E 182135655Scognet add r1, r7, #PCB_R8 183135655Scognet ldmia r1, {r8-r13} 184135655Scognet#else 185135655Scognet ldr r8, [r7, #(PCB_R8)] 186135655Scognet ldr r9, [r7, #(PCB_R9)] 187135655Scognet ldr r10, [r7, #(PCB_R10)] 188135655Scognet ldr r11, [r7, #(PCB_R11)] 189135655Scognet ldr r12, [r7, #(PCB_R12)] 190135655Scognet ldr r13, [r7, #(PCB_SP)] 191135655Scognet#endif 192135655Scognet 193138751Scognet /* We have a new curthread now so make a note it */ 194239268Sgonzo GET_CURTHREAD_PTR(r6) 195138751Scognet str r5, [r6] 196135655Scognet 197142570Scognet /* Set the new tp */ 198142955Scognet ldr r6, [r5, #(TD_MD + MD_TP)] 199239268Sgonzo#ifdef ARM_TP_ADDRESS 200188540Scognet ldr r4, =ARM_TP_ADDRESS 201188540Scognet str r6, [r4] 202188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_START)] 203188540Scognet str r6, [r4, #4] /* ARM_RAS_START */ 204188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_END)] 205188581Scognet str r6, [r4, #8] /* ARM_RAS_END */ 206239268Sgonzo#else 207239268Sgonzo mcr p15, 0, r6, c13, c0, 3 208239268Sgonzo#endif 209138751Scognet /* Hook in a new pcb */ 210239268Sgonzo GET_PCPU(r6) 211239268Sgonzo str r7, [r6, #PC_CURPCB] 212138751Scognet 213138856Scognet ldmfd sp!, {r4-r7, pc} 214138751Scognet 215129198ScognetENTRY(cpu_switch) 216129198Scognet stmfd sp!, {r4-r7, lr} 217171780Scognet mov r6, r2 /* Save the mutex */ 218129198Scognet 219135655Scognet.Lswitch_resume: 220137274Scognet /* rem: r0 = old lwp */ 221129198Scognet /* rem: interrupts are disabled */ 222129198Scognet 223129198Scognet /* Process is now on a processor. */ 224135655Scognet /* We have a new curthread now so make a note it */ 225239268Sgonzo GET_CURTHREAD_PTR(r7) 226137274Scognet str r1, [r7] 227129198Scognet 228129198Scognet /* Hook in a new pcb */ 229239268Sgonzo GET_PCPU(r7) 230137274Scognet ldr r2, [r1, #TD_PCB] 231239268Sgonzo str r2, [r7, #PC_CURPCB] 232129198Scognet 233137274Scognet /* rem: r1 = new process */ 234129198Scognet /* rem: interrupts are enabled */ 235129198Scognet 236129198Scognet /* Stage two : Save old context */ 237129198Scognet 238171780Scognet /* Get the user structure for the old thread. */ 239137274Scognet ldr r2, [r0, #(TD_PCB)] 240171780Scognet mov r4, r0 /* Save the old thread. */ 241129198Scognet 242171780Scognet /* Save all the registers in the old thread's pcb */ 243172614Scognet#ifndef _ARM_ARCH_5E 244137274Scognet add r7, r2, #(PCB_R8) 245129198Scognet stmia r7, {r8-r13} 246129198Scognet#else 247137274Scognet strd r8, [r2, #(PCB_R8)] 248137274Scognet strd r10, [r2, #(PCB_R10)] 249137274Scognet strd r12, [r2, #(PCB_R12)] 250129198Scognet#endif 251181144Scognet str pc, [r2, #(PCB_PC)] 252236991Simp 253129198Scognet /* 254129198Scognet * NOTE: We can now use r8-r13 until it is time to restore 255129198Scognet * them for the new process. 256129198Scognet */ 257239268Sgonzo#ifdef ARM_TP_ADDRESS 258142570Scognet /* Store the old tp */ 259175982Sraj ldr r3, =ARM_TP_ADDRESS 260188540Scognet ldr r9, [r3] 261142570Scognet str r9, [r0, #(TD_MD + MD_TP)] 262188540Scognet ldr r9, [r3, #4] 263188540Scognet str r9, [r0, #(TD_MD + MD_RAS_START)] 264188540Scognet ldr r9, [r3, #8] 265188540Scognet str r9, [r0, #(TD_MD + MD_RAS_END)] 266129198Scognet 267142570Scognet /* Set the new tp */ 268142570Scognet ldr r9, [r1, #(TD_MD + MD_TP)] 269188540Scognet str r9, [r3] 270188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_START)] 271188540Scognet str r9, [r3, #4] 272188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_END)] 273188540Scognet str r9, [r3, #8] 274239268Sgonzo#else 275239268Sgonzo /* Store the old tp */ 276239268Sgonzo mrc p15, 0, r9, c13, c0, 3 277239268Sgonzo str r9, [r0, #(TD_MD + MD_TP)] 278129198Scognet 279239268Sgonzo /* Set the new tp */ 280239268Sgonzo ldr r9, [r1, #(TD_MD + MD_TP)] 281239268Sgonzo mcr p15, 0, r9, c13, c0, 3 282239268Sgonzo#endif 283239268Sgonzo 284129198Scognet /* Get the user structure for the new process in r9 */ 285137274Scognet ldr r9, [r1, #(TD_PCB)] 286129198Scognet 287138751Scognet mrs r3, cpsr 288129198Scognet /* 289236991Simp * We can do that, since 290138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 291129198Scognet */ 292138751Scognet orr r8, r3, #(PSR_UND32_MODE) 293138751Scognet msr cpsr_c, r8 294129198Scognet 295138751Scognet str sp, [r2, #(PCB_UND_SP)] 296129198Scognet 297129198Scognet msr cpsr_c, r3 /* Restore the old mode */ 298239268Sgonzo /* rem: r2 = old PCB */ 299129198Scognet /* rem: r9 = new PCB */ 300129198Scognet /* rem: interrupts are enabled */ 301129198Scognet 302239268Sgonzo#ifdef ARM_VFP_SUPPORT 303239268Sgonzo /* 304239268Sgonzo * vfp_store will clear pcpu->pc_vfpcthread, save 305239268Sgonzo * registers and state, and modify the control as needed. 306239268Sgonzo * a future exception will bounce the backup settings in the fp unit. 307239268Sgonzo * XXX vfp_store can't change r4 308239268Sgonzo */ 309239268Sgonzo GET_PCPU(r7) 310239268Sgonzo ldr r8, [r7, #(PC_VFPCTHREAD)] 311239268Sgonzo cmp r4, r8 /* old thread used vfp? */ 312239268Sgonzo bne 1f /* no, don't save */ 313239268Sgonzo cmp r1, r4 /* same thread ? */ 314239268Sgonzo beq 1f /* yes, skip vfp store */ 315239268Sgonzo#ifdef SMP 316239268Sgonzo ldr r8, [r7, #(PC_CPU)] /* last used on this cpu? */ 317239268Sgonzo ldr r3, [r2, #(PCB_VFPCPU)] 318239268Sgonzo cmp r8, r3 /* last cpu to use these registers? */ 319239268Sgonzo bne 1f /* no. these values are stale */ 320239268Sgonzo#endif 321239268Sgonzo add r0, r2, #(PCB_VFPSTATE) 322239268Sgonzo bl _C_LABEL(vfp_store) 323239268Sgonzo1: 324239268Sgonzo#endif /* ARM_VFP_SUPPORT */ 325129198Scognet 326239268Sgonzo /* r1 now free! */ 327239268Sgonzo 328129198Scognet /* Third phase : restore saved context */ 329129198Scognet 330239268Sgonzo /* rem: r2 = old PCB */ 331129198Scognet /* rem: r9 = new PCB */ 332129198Scognet /* rem: interrupts are enabled */ 333129198Scognet 334138414Scognet ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */ 335138414Scognet mov r2, #DOMAIN_CLIENT 336138414Scognet cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 337138414Scognet beq .Lcs_context_switched /* Yup. Don't flush cache */ 338138414Scognet mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 339129198Scognet /* 340129198Scognet * Get the new L1 table pointer into r11. If we're switching to 341129198Scognet * an LWP with the same address space as the outgoing one, we can 342129198Scognet * skip the cache purge and the TTB load. 343129198Scognet * 344129198Scognet * To avoid data dep stalls that would happen anyway, we try 345129198Scognet * and get some useful work done in the mean time. 346129198Scognet */ 347138414Scognet mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 348129198Scognet ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 349129198Scognet 350129198Scognet 351129198Scognet teq r10, r11 /* Same L1? */ 352137274Scognet cmpeq r0, r5 /* Same DACR? */ 353129198Scognet beq .Lcs_context_switched /* yes! */ 354129198Scognet 355239268Sgonzo#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) 356129198Scognet /* 357129198Scognet * Definately need to flush the cache. 358129198Scognet */ 359129198Scognet 360129198Scognet ldr r1, .Lcpufuncs 361129198Scognet mov lr, pc 362129198Scognet ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 363239268Sgonzo#endif 364129198Scognet.Lcs_cache_purge_skipped: 365171780Scognet /* rem: r6 = lock */ 366129198Scognet /* rem: r9 = new PCB */ 367129198Scognet /* rem: r10 = old L1 */ 368129198Scognet /* rem: r11 = new L1 */ 369129198Scognet 370129198Scognet mov r2, #0x00000000 371129198Scognet ldr r7, [r9, #(PCB_PL1VEC)] 372129198Scognet 373129198Scognet /* 374129198Scognet * Ensure the vector table is accessible by fixing up the L1 375129198Scognet */ 376129198Scognet cmp r7, #0 /* No need to fixup vector table? */ 377129198Scognet ldrne r2, [r7] /* But if yes, fetch current value */ 378129198Scognet ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 379137274Scognet mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 380129198Scognet cmpne r2, r0 /* Stuffing the same value? */ 381135655Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 382129198Scognet strne r0, [r7] /* Nope, update it */ 383129198Scognet#else 384129198Scognet beq .Lcs_same_vector 385129198Scognet str r0, [r7] /* Otherwise, update it */ 386129198Scognet 387129198Scognet /* 388129198Scognet * Need to sync the cache to make sure that last store is 389129198Scognet * visible to the MMU. 390129198Scognet */ 391129198Scognet ldr r2, .Lcpufuncs 392129198Scognet mov r0, r7 393129198Scognet mov r1, #4 394129198Scognet mov lr, pc 395129198Scognet ldr pc, [r2, #CF_DCACHE_WB_RANGE] 396129198Scognet 397129198Scognet.Lcs_same_vector: 398129198Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 399129198Scognet 400129198Scognet cmp r10, r11 /* Switching to the same L1? */ 401129198Scognet ldr r10, .Lcpufuncs 402129198Scognet beq .Lcs_same_l1 /* Yup. */ 403129198Scognet /* 404129198Scognet * Do a full context switch, including full TLB flush. 405129198Scognet */ 406129198Scognet mov r0, r11 407129198Scognet mov lr, pc 408129198Scognet ldr pc, [r10, #CF_CONTEXT_SWITCH] 409129198Scognet 410129198Scognet b .Lcs_context_switched 411129198Scognet 412129198Scognet /* 413129198Scognet * We're switching to a different process in the same L1. 414129198Scognet * In this situation, we only need to flush the TLB for the 415129198Scognet * vector_page mapping, and even then only if r7 is non-NULL. 416129198Scognet */ 417129198Scognet.Lcs_same_l1: 418129198Scognet cmp r7, #0 419129198Scognet movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 420129198Scognet movne lr, pc 421129198Scognet ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 422138751Scognet /* 423236991Simp * We can do that, since 424138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 425138751Scognet */ 426129198Scognet 427129198Scognet.Lcs_context_switched: 428129198Scognet 429171780Scognet /* Release the old thread */ 430171780Scognet str r6, [r4, #TD_LOCK] 431171780Scognet ldr r6, .Lblocked_lock 432239268Sgonzo GET_CURTHREAD_PTR(r3) 433171780Scognet 434171780Scognet1: 435171780Scognet ldr r4, [r3, #TD_LOCK] 436171780Scognet cmp r4, r6 437171780Scognet beq 1b 438171780Scognet 439129198Scognet /* XXXSCW: Safe to re-enable FIQs here */ 440129198Scognet 441129198Scognet /* rem: r9 = new PCB */ 442129198Scognet 443138751Scognet mrs r3, cpsr 444129198Scognet /* 445236991Simp * We can do that, since 446138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 447129198Scognet */ 448138751Scognet orr r2, r3, #(PSR_UND32_MODE) 449138751Scognet msr cpsr_c, r2 450129198Scognet 451129198Scognet ldr sp, [r9, #(PCB_UND_SP)] 452129198Scognet 453129198Scognet msr cpsr_c, r3 /* Restore the old mode */ 454129198Scognet /* Restore all the save registers */ 455172614Scognet#ifndef _ARM_ARCH_5E 456129198Scognet add r7, r9, #PCB_R8 457129198Scognet ldmia r7, {r8-r13} 458129198Scognet sub r7, r7, #PCB_R8 /* restore PCB pointer */ 459129198Scognet#else 460129198Scognet mov r7, r9 461129198Scognet ldr r8, [r7, #(PCB_R8)] 462129198Scognet ldr r9, [r7, #(PCB_R9)] 463129198Scognet ldr r10, [r7, #(PCB_R10)] 464129198Scognet ldr r11, [r7, #(PCB_R11)] 465129198Scognet ldr r12, [r7, #(PCB_R12)] 466129198Scognet ldr r13, [r7, #(PCB_SP)] 467129198Scognet#endif 468129198Scognet 469171780Scognet /* rem: r6 = lock */ 470129198Scognet /* rem: r7 = new pcb */ 471129198Scognet 472129198Scognet#ifdef ARMFPE 473129198Scognet add r0, r7, #(USER_SIZE) & 0x00ff 474236991Simp add r0, r0, #(USER_SIZE) & 0xff00 475129198Scognet bl _C_LABEL(arm_fpe_core_changecontext) 476129198Scognet#endif 477129198Scognet 478129198Scognet /* rem: r5 = new lwp's proc */ 479171780Scognet /* rem: r6 = lock */ 480129198Scognet /* rem: r7 = new PCB */ 481129198Scognet 482129198Scognet.Lswitch_return: 483129198Scognet 484129198Scognet /* 485129198Scognet * Pull the registers that got pushed when either savectx() or 486129198Scognet * cpu_switch() was called and return. 487129198Scognet */ 488129198Scognet ldmfd sp!, {r4-r7, pc} 489129198Scognet#ifdef DIAGNOSTIC 490129198Scognet.Lswitch_bogons: 491129198Scognet adr r0, .Lswitch_panic_str 492129198Scognet bl _C_LABEL(panic) 493129198Scognet1: nop 494129198Scognet b 1b 495129198Scognet 496129198Scognet.Lswitch_panic_str: 497129198Scognet .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n" 498129198Scognet#endif 499129198ScognetENTRY(savectx) 500150856Scognet stmfd sp!, {r4-r7, lr} 501150856Scognet /* 502150856Scognet * r0 = pcb 503150856Scognet */ 504150856Scognet /* Store all the registers in the process's pcb */ 505150856Scognet add r2, r0, #(PCB_R8) 506150856Scognet stmia r2, {r8-r13} 507239268Sgonzo#ifdef ARM_VFP_SUPPORT 508239268Sgonzo /* 509239268Sgonzo * vfp_store will clear pcpu->pc_vfpcthread, save 510239268Sgonzo * registers and state, and modify the control as needed. 511239268Sgonzo * a future exception will bounce the backup settings in the fp unit. 512239268Sgonzo */ 513239268Sgonzo GET_PCPU(r7) 514239268Sgonzo ldr r4, [r7, #(PC_VFPCTHREAD)] /* vfp thread */ 515239268Sgonzo ldr r2, [r7, #(PC_CURTHREAD)] /* current thread */ 516239268Sgonzo cmp r4, r2 517239268Sgonzo bne 1f 518239268Sgonzo#ifdef SMP 519239268Sgonzo ldr r2, [r7, #(PC_CPU)] /* last used on this cpu? */ 520239268Sgonzo ldr r3, [r0, #(PCB_VFPCPU)] 521239268Sgonzo cmp r2, r3 522239268Sgonzo bne 1f /* no. these values are stale */ 523239268Sgonzo#endif 524239268Sgonzo add r0, r0, #(PCB_VFPSTATE) 525239268Sgonzo bl _C_LABEL(vfp_store) 526239268Sgonzo1: 527239268Sgonzo#endif /* ARM_VFP_SUPPORT */ 528150856Scognet ldmfd sp!, {r4-r7, pc} 529150856Scognet 530129198ScognetENTRY(fork_trampoline) 531129198Scognet mov r1, r5 532129198Scognet mov r2, sp 533129198Scognet mov r0, r4 534137976Scognet mov fp, #0 535129198Scognet bl _C_LABEL(fork_exit) 536135655Scognet /* Kill irq"s */ 537135655Scognet mrs r0, cpsr 538157616Scognet orr r0, r0, #(I32_bit|F32_bit) 539135655Scognet msr cpsr_c, r0 540146596Scognet DO_AST 541129198Scognet PULLFRAME 542129198Scognet 543129198Scognet movs pc, lr /* Exit */ 544129198Scognet 545135655ScognetAST_LOCALS 546