mp_machdep.c revision 283366
1/*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/arm/arm/mp_machdep.c 283366 2015-05-24 12:20:11Z andrew $"); 28#include <sys/param.h> 29#include <sys/systm.h> 30#include <sys/bus.h> 31#include <sys/kernel.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/proc.h> 35#include <sys/pcpu.h> 36#include <sys/sched.h> 37#include <sys/smp.h> 38#include <sys/ktr.h> 39#include <sys/malloc.h> 40 41#include <vm/vm.h> 42#include <vm/vm_extern.h> 43#include <vm/vm_kern.h> 44#include <vm/pmap.h> 45 46#include <machine/armreg.h> 47#include <machine/cpu.h> 48#include <machine/cpufunc.h> 49#include <machine/smp.h> 50#include <machine/pcb.h> 51#include <machine/pmap.h> 52#include <machine/pte.h> 53#include <machine/physmem.h> 54#include <machine/intr.h> 55#include <machine/vmparam.h> 56#ifdef VFP 57#include <machine/vfp.h> 58#endif 59#ifdef CPU_MV_PJ4B 60#include <arm/mv/mvwin.h> 61#include <dev/fdt/fdt_common.h> 62#endif 63 64#include "opt_smp.h" 65 66extern struct pcpu __pcpu[]; 67/* used to hold the AP's until we are ready to release them */ 68struct mtx ap_boot_mtx; 69struct pcb stoppcbs[MAXCPU]; 70 71/* # of Applications processors */ 72volatile int mp_naps; 73 74/* Set to 1 once we're ready to let the APs out of the pen. */ 75volatile int aps_ready = 0; 76 77static int ipi_handler(void *arg); 78void set_stackptrs(int cpu); 79 80/* Temporary variables for init_secondary() */ 81void *dpcpu[MAXCPU - 1]; 82 83/* Determine if we running MP machine */ 84int 85cpu_mp_probe(void) 86{ 87 CPU_SETOF(0, &all_cpus); 88 89 return (platform_mp_probe()); 90} 91 92/* Start Application Processor via platform specific function */ 93static int 94check_ap(void) 95{ 96 uint32_t ms; 97 98 for (ms = 0; ms < 2000; ++ms) { 99 if ((mp_naps + 1) == mp_ncpus) 100 return (0); /* success */ 101 else 102 DELAY(1000); 103 } 104 105 return (-2); 106} 107 108extern unsigned char _end[]; 109 110/* Initialize and fire up non-boot processors */ 111void 112cpu_mp_start(void) 113{ 114 int error, i; 115 116 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 117 118 /* Reserve memory for application processors */ 119 for(i = 0; i < (mp_ncpus - 1); i++) 120 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 121 M_WAITOK | M_ZERO); 122 123 cpu_idcache_wbinv_all(); 124 cpu_l2cache_wbinv_all(); 125 cpu_idcache_wbinv_all(); 126 127 /* Initialize boot code and start up processors */ 128 platform_mp_start_ap(); 129 130 /* Check if ap's started properly */ 131 error = check_ap(); 132 if (error) 133 printf("WARNING: Some AP's failed to start\n"); 134 else 135 for (i = 1; i < mp_ncpus; i++) 136 CPU_SET(i, &all_cpus); 137 138} 139 140/* Introduce rest of cores to the world */ 141void 142cpu_mp_announce(void) 143{ 144 145} 146 147extern vm_paddr_t pmap_pa; 148void 149init_secondary(int cpu) 150{ 151 struct pcpu *pc; 152 uint32_t loop_counter; 153 int start = 0, end = 0; 154 155#ifdef ARM_NEW_PMAP 156 pmap_set_tex(); 157 reinit_mmu(pmap_kern_ttb, (1<<6) | (1<< 0), (1<<6) | (1<< 0)); 158 cpu_setup(); 159 160 /* Provide stack pointers for other processor modes. */ 161 set_stackptrs(cpu); 162 163 enable_interrupts(PSR_A); 164#else /* ARM_NEW_PMAP */ 165 cpu_setup(); 166 setttb(pmap_pa); 167 cpu_tlb_flushID(); 168#endif /* ARM_NEW_PMAP */ 169 pc = &__pcpu[cpu]; 170 171 /* 172 * pcpu_init() updates queue, so it should not be executed in parallel 173 * on several cores 174 */ 175 while(mp_naps < (cpu - 1)) 176 ; 177 178 pcpu_init(pc, cpu, sizeof(struct pcpu)); 179 dpcpu_init(dpcpu[cpu - 1], cpu); 180#ifndef ARM_NEW_PMAP 181 /* Provide stack pointers for other processor modes. */ 182 set_stackptrs(cpu); 183#endif 184 /* Signal our startup to BSP */ 185 atomic_add_rel_32(&mp_naps, 1); 186 187 /* Spin until the BSP releases the APs */ 188 while (!atomic_load_acq_int(&aps_ready)) { 189#if __ARM_ARCH >= 7 190 __asm __volatile("wfe"); 191#endif 192 } 193 194 /* Initialize curthread */ 195 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 196 pc->pc_curthread = pc->pc_idlethread; 197 pc->pc_curpcb = pc->pc_idlethread->td_pcb; 198 set_curthread(pc->pc_idlethread); 199#ifdef VFP 200 pc->pc_cpu = cpu; 201 202 vfp_init(); 203#endif 204 205 mtx_lock_spin(&ap_boot_mtx); 206 207 atomic_add_rel_32(&smp_cpus, 1); 208 209 if (smp_cpus == mp_ncpus) { 210 /* enable IPI's, tlb shootdown, freezes etc */ 211 atomic_store_rel_int(&smp_started, 1); 212 } 213 214 mtx_unlock_spin(&ap_boot_mtx); 215 216 /* Enable ipi */ 217#ifdef IPI_IRQ_START 218 start = IPI_IRQ_START; 219#ifdef IPI_IRQ_END 220 end = IPI_IRQ_END; 221#else 222 end = IPI_IRQ_START; 223#endif 224#endif 225 226 for (int i = start; i <= end; i++) 227 arm_unmask_irq(i); 228 enable_interrupts(PSR_I); 229 230 loop_counter = 0; 231 while (smp_started == 0) { 232 DELAY(100); 233 loop_counter++; 234 if (loop_counter == 1000) 235 CTR0(KTR_SMP, "AP still wait for smp_started"); 236 } 237 /* Start per-CPU event timers. */ 238 cpu_initclocks_ap(); 239 240 CTR0(KTR_SMP, "go into scheduler"); 241 platform_mp_init_secondary(); 242 243 /* Enter the scheduler */ 244 sched_throw(NULL); 245 246 panic("scheduler returned us to %s", __func__); 247 /* NOTREACHED */ 248} 249 250static int 251ipi_handler(void *arg) 252{ 253 u_int cpu, ipi; 254 255 cpu = PCPU_GET(cpuid); 256 257 ipi = pic_ipi_read((int)arg); 258 259 while ((ipi != 0x3ff)) { 260 switch (ipi) { 261 case IPI_RENDEZVOUS: 262 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 263 smp_rendezvous_action(); 264 break; 265 266 case IPI_AST: 267 CTR0(KTR_SMP, "IPI_AST"); 268 break; 269 270 case IPI_STOP: 271 /* 272 * IPI_STOP_HARD is mapped to IPI_STOP so it is not 273 * necessary to add it in the switch. 274 */ 275 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 276 277 savectx(&stoppcbs[cpu]); 278 279 /* 280 * CPUs are stopped when entering the debugger and at 281 * system shutdown, both events which can precede a 282 * panic dump. For the dump to be correct, all caches 283 * must be flushed and invalidated, but on ARM there's 284 * no way to broadcast a wbinv_all to other cores. 285 * Instead, we have each core do the local wbinv_all as 286 * part of stopping the core. The core requesting the 287 * stop will do the l2 cache flush after all other cores 288 * have done their l1 flushes and stopped. 289 */ 290 cpu_idcache_wbinv_all(); 291 292 /* Indicate we are stopped */ 293 CPU_SET_ATOMIC(cpu, &stopped_cpus); 294 295 /* Wait for restart */ 296 while (!CPU_ISSET(cpu, &started_cpus)) 297 cpu_spinwait(); 298 299 CPU_CLR_ATOMIC(cpu, &started_cpus); 300 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 301 CTR0(KTR_SMP, "IPI_STOP (restart)"); 302 break; 303 case IPI_PREEMPT: 304 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 305 sched_preempt(curthread); 306 break; 307 case IPI_HARDCLOCK: 308 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 309 hardclockintr(); 310 break; 311 case IPI_TLB: 312 CTR1(KTR_SMP, "%s: IPI_TLB", __func__); 313 cpufuncs.cf_tlb_flushID(); 314 break; 315 default: 316 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu); 317 } 318 319 pic_ipi_clear(ipi); 320 ipi = pic_ipi_read(-1); 321 } 322 323 return (FILTER_HANDLED); 324} 325 326static void 327release_aps(void *dummy __unused) 328{ 329 uint32_t loop_counter; 330 int start = 0, end = 0; 331 332 if (mp_ncpus == 1) 333 return; 334#ifdef IPI_IRQ_START 335 start = IPI_IRQ_START; 336#ifdef IPI_IRQ_END 337 end = IPI_IRQ_END; 338#else 339 end = IPI_IRQ_START; 340#endif 341#endif 342 343 for (int i = start; i <= end; i++) { 344 /* 345 * IPI handler 346 */ 347 /* 348 * Use 0xdeadbeef as the argument value for irq 0, 349 * if we used 0, the intr code will give the trap frame 350 * pointer instead. 351 */ 352 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i, 353 INTR_TYPE_MISC | INTR_EXCL, NULL); 354 355 /* Enable ipi */ 356 arm_unmask_irq(i); 357 } 358 atomic_store_rel_int(&aps_ready, 1); 359 /* Wake the other threads up */ 360#if __ARM_ARCH >= 7 361 armv7_sev(); 362#endif 363 364 printf("Release APs\n"); 365 366 for (loop_counter = 0; loop_counter < 2000; loop_counter++) { 367 if (smp_started) 368 return; 369 DELAY(1000); 370 } 371 printf("AP's not started\n"); 372} 373 374SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 375 376struct cpu_group * 377cpu_topo(void) 378{ 379 380 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); 381} 382 383void 384cpu_mp_setmaxid(void) 385{ 386 387 platform_mp_setmaxid(); 388} 389 390/* Sending IPI */ 391void 392ipi_all_but_self(u_int ipi) 393{ 394 cpuset_t other_cpus; 395 396 other_cpus = all_cpus; 397 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 398 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 399 platform_ipi_send(other_cpus, ipi); 400} 401 402void 403ipi_cpu(int cpu, u_int ipi) 404{ 405 cpuset_t cpus; 406 407 CPU_ZERO(&cpus); 408 CPU_SET(cpu, &cpus); 409 410 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); 411 platform_ipi_send(cpus, ipi); 412} 413 414void 415ipi_selected(cpuset_t cpus, u_int ipi) 416{ 417 418 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 419 platform_ipi_send(cpus, ipi); 420} 421 422void 423tlb_broadcast(int ipi) 424{ 425 426 if (smp_started) 427 ipi_all_but_self(ipi); 428} 429