mp_machdep.c revision 271398
1/*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/arm/arm/mp_machdep.c 271398 2014-09-10 15:25:15Z andrew $"); 28#include <sys/param.h> 29#include <sys/systm.h> 30#include <sys/bus.h> 31#include <sys/kernel.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/proc.h> 35#include <sys/pcpu.h> 36#include <sys/sched.h> 37#include <sys/smp.h> 38#include <sys/ktr.h> 39#include <sys/malloc.h> 40 41#include <vm/vm.h> 42#include <vm/vm_extern.h> 43#include <vm/vm_kern.h> 44#include <vm/pmap.h> 45 46#include <machine/armreg.h> 47#include <machine/cpu.h> 48#include <machine/cpufunc.h> 49#include <machine/smp.h> 50#include <machine/pcb.h> 51#include <machine/pte.h> 52#include <machine/physmem.h> 53#include <machine/intr.h> 54#include <machine/vmparam.h> 55#ifdef VFP 56#include <machine/vfp.h> 57#endif 58#ifdef CPU_MV_PJ4B 59#include <arm/mv/mvwin.h> 60#include <dev/fdt/fdt_common.h> 61#endif 62 63#include "opt_smp.h" 64 65void *temp_pagetable; 66extern struct pcpu __pcpu[]; 67/* used to hold the AP's until we are ready to release them */ 68struct mtx ap_boot_mtx; 69struct pcb stoppcbs[MAXCPU]; 70 71/* # of Applications processors */ 72volatile int mp_naps; 73 74/* Set to 1 once we're ready to let the APs out of the pen. */ 75volatile int aps_ready = 0; 76 77static int ipi_handler(void *arg); 78void set_stackptrs(int cpu); 79 80/* Temporary variables for init_secondary() */ 81void *dpcpu[MAXCPU - 1]; 82 83/* Determine if we running MP machine */ 84int 85cpu_mp_probe(void) 86{ 87 CPU_SETOF(0, &all_cpus); 88 89 return (platform_mp_probe()); 90} 91 92/* Start Application Processor via platform specific function */ 93static int 94check_ap(void) 95{ 96 uint32_t ms; 97 98 for (ms = 0; ms < 2000; ++ms) { 99 if ((mp_naps + 1) == mp_ncpus) 100 return (0); /* success */ 101 else 102 DELAY(1000); 103 } 104 105 return (-2); 106} 107 108extern unsigned char _end[]; 109 110/* Initialize and fire up non-boot processors */ 111void 112cpu_mp_start(void) 113{ 114 int error, i; 115 vm_offset_t temp_pagetable_va; 116 vm_paddr_t addr, addr_end; 117 118 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 119 120 /* Reserve memory for application processors */ 121 for(i = 0; i < (mp_ncpus - 1); i++) 122 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 123 M_WAITOK | M_ZERO); 124 temp_pagetable_va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, 125 M_TEMP, 0, 0x0, 0xffffffff, L1_TABLE_SIZE, 0); 126 addr = arm_physmem_kernaddr; 127 addr_end = (vm_offset_t)&_end - KERNVIRTADDR + arm_physmem_kernaddr; 128 addr_end &= ~L1_S_OFFSET; 129 addr_end += L1_S_SIZE; 130 bzero((void *)temp_pagetable_va, L1_TABLE_SIZE); 131 for (addr = arm_physmem_kernaddr; addr <= addr_end; addr += L1_S_SIZE) { 132 ((int *)(temp_pagetable_va))[addr >> L1_S_SHIFT] = 133 L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; 134 ((int *)(temp_pagetable_va))[(addr - 135 arm_physmem_kernaddr + KERNVIRTADDR) >> L1_S_SHIFT] = 136 L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; 137 } 138 139#if defined(CPU_MV_PJ4B) 140 /* Add ARMADAXP registers required for snoop filter initialization */ 141 ((int *)(temp_pagetable_va))[MV_BASE >> L1_S_SHIFT] = 142 L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|fdt_immr_pa; 143#endif 144 145 temp_pagetable = (void*)(vtophys(temp_pagetable_va)); 146 cpu_idcache_wbinv_all(); 147 cpu_l2cache_wbinv_all(); 148 149 /* Initialize boot code and start up processors */ 150 platform_mp_start_ap(); 151 152 /* Check if ap's started properly */ 153 error = check_ap(); 154 if (error) 155 printf("WARNING: Some AP's failed to start\n"); 156 else 157 for (i = 1; i < mp_ncpus; i++) 158 CPU_SET(i, &all_cpus); 159 160 contigfree((void *)temp_pagetable_va, L1_TABLE_SIZE, M_TEMP); 161} 162 163/* Introduce rest of cores to the world */ 164void 165cpu_mp_announce(void) 166{ 167 168} 169 170extern vm_paddr_t pmap_pa; 171void 172init_secondary(int cpu) 173{ 174 struct pcpu *pc; 175 uint32_t loop_counter; 176 int start = 0, end = 0; 177 178 cpu_idcache_inv_all(); 179 180 cpu_setup(NULL); 181 setttb(pmap_pa); 182 cpu_tlb_flushID(); 183 184 pc = &__pcpu[cpu]; 185 186 /* 187 * pcpu_init() updates queue, so it should not be executed in parallel 188 * on several cores 189 */ 190 while(mp_naps < (cpu - 1)) 191 ; 192 193 pcpu_init(pc, cpu, sizeof(struct pcpu)); 194 dpcpu_init(dpcpu[cpu - 1], cpu); 195 196 /* Provide stack pointers for other processor modes. */ 197 set_stackptrs(cpu); 198 199 /* Signal our startup to BSP */ 200 atomic_add_rel_32(&mp_naps, 1); 201 202 /* Spin until the BSP releases the APs */ 203 while (!aps_ready) 204 ; 205 206 /* Initialize curthread */ 207 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 208 pc->pc_curthread = pc->pc_idlethread; 209 pc->pc_curpcb = pc->pc_idlethread->td_pcb; 210 set_curthread(pc->pc_idlethread); 211#ifdef VFP 212 pc->pc_cpu = cpu; 213 214 vfp_init(); 215#endif 216 217 mtx_lock_spin(&ap_boot_mtx); 218 219 atomic_add_rel_32(&smp_cpus, 1); 220 221 if (smp_cpus == mp_ncpus) { 222 /* enable IPI's, tlb shootdown, freezes etc */ 223 atomic_store_rel_int(&smp_started, 1); 224 } 225 226 mtx_unlock_spin(&ap_boot_mtx); 227 228 /* Enable ipi */ 229#ifdef IPI_IRQ_START 230 start = IPI_IRQ_START; 231#ifdef IPI_IRQ_END 232 end = IPI_IRQ_END; 233#else 234 end = IPI_IRQ_START; 235#endif 236#endif 237 238 for (int i = start; i <= end; i++) 239 arm_unmask_irq(i); 240 enable_interrupts(PSR_I); 241 242 loop_counter = 0; 243 while (smp_started == 0) { 244 DELAY(100); 245 loop_counter++; 246 if (loop_counter == 1000) 247 CTR0(KTR_SMP, "AP still wait for smp_started"); 248 } 249 /* Start per-CPU event timers. */ 250 cpu_initclocks_ap(); 251 252 CTR0(KTR_SMP, "go into scheduler"); 253 platform_mp_init_secondary(); 254 255 /* Enter the scheduler */ 256 sched_throw(NULL); 257 258 panic("scheduler returned us to %s", __func__); 259 /* NOTREACHED */ 260} 261 262static int 263ipi_handler(void *arg) 264{ 265 u_int cpu, ipi; 266 267 cpu = PCPU_GET(cpuid); 268 269 ipi = pic_ipi_get((int)arg); 270 271 while ((ipi != 0x3ff)) { 272 switch (ipi) { 273 case IPI_RENDEZVOUS: 274 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 275 smp_rendezvous_action(); 276 break; 277 278 case IPI_AST: 279 CTR0(KTR_SMP, "IPI_AST"); 280 break; 281 282 case IPI_STOP: 283 /* 284 * IPI_STOP_HARD is mapped to IPI_STOP so it is not 285 * necessary to add it in the switch. 286 */ 287 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 288 289 savectx(&stoppcbs[cpu]); 290 291 /* 292 * CPUs are stopped when entering the debugger and at 293 * system shutdown, both events which can precede a 294 * panic dump. For the dump to be correct, all caches 295 * must be flushed and invalidated, but on ARM there's 296 * no way to broadcast a wbinv_all to other cores. 297 * Instead, we have each core do the local wbinv_all as 298 * part of stopping the core. The core requesting the 299 * stop will do the l2 cache flush after all other cores 300 * have done their l1 flushes and stopped. 301 */ 302 cpu_idcache_wbinv_all(); 303 304 /* Indicate we are stopped */ 305 CPU_SET_ATOMIC(cpu, &stopped_cpus); 306 307 /* Wait for restart */ 308 while (!CPU_ISSET(cpu, &started_cpus)) 309 cpu_spinwait(); 310 311 CPU_CLR_ATOMIC(cpu, &started_cpus); 312 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 313 CTR0(KTR_SMP, "IPI_STOP (restart)"); 314 break; 315 case IPI_PREEMPT: 316 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 317 sched_preempt(curthread); 318 break; 319 case IPI_HARDCLOCK: 320 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 321 hardclockintr(); 322 break; 323 case IPI_TLB: 324 CTR1(KTR_SMP, "%s: IPI_TLB", __func__); 325 cpufuncs.cf_tlb_flushID(); 326 break; 327 default: 328 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu); 329 } 330 331 pic_ipi_clear(ipi); 332 ipi = pic_ipi_get(-1); 333 } 334 335 return (FILTER_HANDLED); 336} 337 338static void 339release_aps(void *dummy __unused) 340{ 341 uint32_t loop_counter; 342 int start = 0, end = 0; 343 344 if (mp_ncpus == 1) 345 return; 346#ifdef IPI_IRQ_START 347 start = IPI_IRQ_START; 348#ifdef IPI_IRQ_END 349 end = IPI_IRQ_END; 350#else 351 end = IPI_IRQ_START; 352#endif 353#endif 354 355 for (int i = start; i <= end; i++) { 356 /* 357 * IPI handler 358 */ 359 /* 360 * Use 0xdeadbeef as the argument value for irq 0, 361 * if we used 0, the intr code will give the trap frame 362 * pointer instead. 363 */ 364 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i, 365 INTR_TYPE_MISC | INTR_EXCL, NULL); 366 367 /* Enable ipi */ 368 arm_unmask_irq(i); 369 } 370 atomic_store_rel_int(&aps_ready, 1); 371 372 printf("Release APs\n"); 373 374 for (loop_counter = 0; loop_counter < 2000; loop_counter++) { 375 if (smp_started) 376 return; 377 DELAY(1000); 378 } 379 printf("AP's not started\n"); 380} 381 382SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 383 384struct cpu_group * 385cpu_topo(void) 386{ 387 388 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); 389} 390 391void 392cpu_mp_setmaxid(void) 393{ 394 395 platform_mp_setmaxid(); 396} 397 398/* Sending IPI */ 399void 400ipi_all_but_self(u_int ipi) 401{ 402 cpuset_t other_cpus; 403 404 other_cpus = all_cpus; 405 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 406 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 407 platform_ipi_send(other_cpus, ipi); 408} 409 410void 411ipi_cpu(int cpu, u_int ipi) 412{ 413 cpuset_t cpus; 414 415 CPU_ZERO(&cpus); 416 CPU_SET(cpu, &cpus); 417 418 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); 419 platform_ipi_send(cpus, ipi); 420} 421 422void 423ipi_selected(cpuset_t cpus, u_int ipi) 424{ 425 426 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 427 platform_ipi_send(cpus, ipi); 428} 429 430void 431tlb_broadcast(int ipi) 432{ 433 434 if (smp_started) 435 ipi_all_but_self(ipi); 436} 437