mp_machdep.c revision 265024
1/*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/arm/arm/mp_machdep.c 265024 2014-04-27 20:16:51Z ian $"); 28#include <sys/param.h> 29#include <sys/systm.h> 30#include <sys/bus.h> 31#include <sys/kernel.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/proc.h> 35#include <sys/pcpu.h> 36#include <sys/sched.h> 37#include <sys/smp.h> 38#include <sys/ktr.h> 39#include <sys/malloc.h> 40 41#include <vm/vm.h> 42#include <vm/vm_extern.h> 43#include <vm/vm_kern.h> 44#include <vm/pmap.h> 45 46#include <machine/cpu.h> 47#include <machine/cpufunc.h> 48#include <machine/smp.h> 49#include <machine/pcb.h> 50#include <machine/pte.h> 51#include <machine/physmem.h> 52#include <machine/intr.h> 53#include <machine/vmparam.h> 54#ifdef VFP 55#include <machine/vfp.h> 56#endif 57#ifdef CPU_MV_PJ4B 58#include <arm/mv/mvwin.h> 59#include <dev/fdt/fdt_common.h> 60#endif 61 62#include "opt_smp.h" 63 64void *temp_pagetable; 65extern struct pcpu __pcpu[]; 66/* used to hold the AP's until we are ready to release them */ 67struct mtx ap_boot_mtx; 68struct pcb stoppcbs[MAXCPU]; 69 70/* # of Applications processors */ 71volatile int mp_naps; 72 73/* Set to 1 once we're ready to let the APs out of the pen. */ 74volatile int aps_ready = 0; 75 76static int ipi_handler(void *arg); 77void set_stackptrs(int cpu); 78 79/* Temporary variables for init_secondary() */ 80void *dpcpu[MAXCPU - 1]; 81 82/* Determine if we running MP machine */ 83int 84cpu_mp_probe(void) 85{ 86 CPU_SETOF(0, &all_cpus); 87 88 return (platform_mp_probe()); 89} 90 91/* Start Application Processor via platform specific function */ 92static int 93check_ap(void) 94{ 95 uint32_t ms; 96 97 for (ms = 0; ms < 2000; ++ms) { 98 if ((mp_naps + 1) == mp_ncpus) 99 return (0); /* success */ 100 else 101 DELAY(1000); 102 } 103 104 return (-2); 105} 106 107extern unsigned char _end[]; 108 109/* Initialize and fire up non-boot processors */ 110void 111cpu_mp_start(void) 112{ 113 int error, i; 114 vm_offset_t temp_pagetable_va; 115 vm_paddr_t addr, addr_end; 116 117 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 118 119 /* Reserve memory for application processors */ 120 for(i = 0; i < (mp_ncpus - 1); i++) 121 dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 122 M_WAITOK | M_ZERO); 123 temp_pagetable_va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, 124 M_TEMP, 0, 0x0, 0xffffffff, L1_TABLE_SIZE, 0); 125 addr = arm_physmem_kernaddr; 126 addr_end = (vm_offset_t)&_end - KERNVIRTADDR + arm_physmem_kernaddr; 127 addr_end &= ~L1_S_OFFSET; 128 addr_end += L1_S_SIZE; 129 bzero((void *)temp_pagetable_va, L1_TABLE_SIZE); 130 for (addr = arm_physmem_kernaddr; addr <= addr_end; addr += L1_S_SIZE) { 131 ((int *)(temp_pagetable_va))[addr >> L1_S_SHIFT] = 132 L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; 133 ((int *)(temp_pagetable_va))[(addr - 134 arm_physmem_kernaddr + KERNVIRTADDR) >> L1_S_SHIFT] = 135 L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; 136 } 137 138#if defined(CPU_MV_PJ4B) 139 /* Add ARMADAXP registers required for snoop filter initialization */ 140 ((int *)(temp_pagetable_va))[MV_BASE >> L1_S_SHIFT] = 141 L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|fdt_immr_pa; 142#endif 143 144 temp_pagetable = (void*)(vtophys(temp_pagetable_va)); 145 cpu_idcache_wbinv_all(); 146 cpu_l2cache_wbinv_all(); 147 148 /* Initialize boot code and start up processors */ 149 platform_mp_start_ap(); 150 151 /* Check if ap's started properly */ 152 error = check_ap(); 153 if (error) 154 printf("WARNING: Some AP's failed to start\n"); 155 else 156 for (i = 1; i < mp_ncpus; i++) 157 CPU_SET(i, &all_cpus); 158 159 contigfree((void *)temp_pagetable_va, L1_TABLE_SIZE, M_TEMP); 160} 161 162/* Introduce rest of cores to the world */ 163void 164cpu_mp_announce(void) 165{ 166 167} 168 169extern vm_paddr_t pmap_pa; 170void 171init_secondary(int cpu) 172{ 173 struct pcpu *pc; 174 uint32_t loop_counter; 175 int start = 0, end = 0; 176 177 cpu_idcache_inv_all(); 178 179 cpu_setup(NULL); 180 setttb(pmap_pa); 181 cpu_tlb_flushID(); 182 183 pc = &__pcpu[cpu]; 184 185 /* 186 * pcpu_init() updates queue, so it should not be executed in parallel 187 * on several cores 188 */ 189 while(mp_naps < (cpu - 1)) 190 ; 191 192 pcpu_init(pc, cpu, sizeof(struct pcpu)); 193 dpcpu_init(dpcpu[cpu - 1], cpu); 194 195 /* Provide stack pointers for other processor modes. */ 196 set_stackptrs(cpu); 197 198 /* Signal our startup to BSP */ 199 atomic_add_rel_32(&mp_naps, 1); 200 201 /* Spin until the BSP releases the APs */ 202 while (!aps_ready) 203 ; 204 205 /* Initialize curthread */ 206 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 207 pc->pc_curthread = pc->pc_idlethread; 208 pc->pc_curpcb = pc->pc_idlethread->td_pcb; 209 set_curthread(pc->pc_idlethread); 210#ifdef VFP 211 pc->pc_cpu = cpu; 212 213 vfp_init(); 214#endif 215 216 mtx_lock_spin(&ap_boot_mtx); 217 218 atomic_add_rel_32(&smp_cpus, 1); 219 220 if (smp_cpus == mp_ncpus) { 221 /* enable IPI's, tlb shootdown, freezes etc */ 222 atomic_store_rel_int(&smp_started, 1); 223 } 224 225 mtx_unlock_spin(&ap_boot_mtx); 226 227 /* Enable ipi */ 228#ifdef IPI_IRQ_START 229 start = IPI_IRQ_START; 230#ifdef IPI_IRQ_END 231 end = IPI_IRQ_END; 232#else 233 end = IPI_IRQ_START; 234#endif 235#endif 236 237 for (int i = start; i <= end; i++) 238 arm_unmask_irq(i); 239 enable_interrupts(I32_bit); 240 241 loop_counter = 0; 242 while (smp_started == 0) { 243 DELAY(100); 244 loop_counter++; 245 if (loop_counter == 1000) 246 CTR0(KTR_SMP, "AP still wait for smp_started"); 247 } 248 /* Start per-CPU event timers. */ 249 cpu_initclocks_ap(); 250 251 CTR0(KTR_SMP, "go into scheduler"); 252 platform_mp_init_secondary(); 253 254 /* Enter the scheduler */ 255 sched_throw(NULL); 256 257 panic("scheduler returned us to %s", __func__); 258 /* NOTREACHED */ 259} 260 261static int 262ipi_handler(void *arg) 263{ 264 u_int cpu, ipi; 265 266 cpu = PCPU_GET(cpuid); 267 268 ipi = pic_ipi_get((int)arg); 269 270 while ((ipi != 0x3ff)) { 271 switch (ipi) { 272 case IPI_RENDEZVOUS: 273 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 274 smp_rendezvous_action(); 275 break; 276 277 case IPI_AST: 278 CTR0(KTR_SMP, "IPI_AST"); 279 break; 280 281 case IPI_STOP: 282 /* 283 * IPI_STOP_HARD is mapped to IPI_STOP so it is not 284 * necessary to add it in the switch. 285 */ 286 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 287 288 savectx(&stoppcbs[cpu]); 289 290 /* 291 * CPUs are stopped when entering the debugger and at 292 * system shutdown, both events which can precede a 293 * panic dump. For the dump to be correct, all caches 294 * must be flushed and invalidated, but on ARM there's 295 * no way to broadcast a wbinv_all to other cores. 296 * Instead, we have each core do the local wbinv_all as 297 * part of stopping the core. The core requesting the 298 * stop will do the l2 cache flush after all other cores 299 * have done their l1 flushes and stopped. 300 */ 301 cpu_idcache_wbinv_all(); 302 303 /* Indicate we are stopped */ 304 CPU_SET_ATOMIC(cpu, &stopped_cpus); 305 306 /* Wait for restart */ 307 while (!CPU_ISSET(cpu, &started_cpus)) 308 cpu_spinwait(); 309 310 CPU_CLR_ATOMIC(cpu, &started_cpus); 311 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 312 CTR0(KTR_SMP, "IPI_STOP (restart)"); 313 break; 314 case IPI_PREEMPT: 315 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 316 sched_preempt(curthread); 317 break; 318 case IPI_HARDCLOCK: 319 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 320 hardclockintr(); 321 break; 322 case IPI_TLB: 323 CTR1(KTR_SMP, "%s: IPI_TLB", __func__); 324 cpufuncs.cf_tlb_flushID(); 325 break; 326 default: 327 panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu); 328 } 329 330 pic_ipi_clear(ipi); 331 ipi = pic_ipi_get(-1); 332 } 333 334 return (FILTER_HANDLED); 335} 336 337static void 338release_aps(void *dummy __unused) 339{ 340 uint32_t loop_counter; 341 int start = 0, end = 0; 342 343 if (mp_ncpus == 1) 344 return; 345#ifdef IPI_IRQ_START 346 start = IPI_IRQ_START; 347#ifdef IPI_IRQ_END 348 end = IPI_IRQ_END; 349#else 350 end = IPI_IRQ_START; 351#endif 352#endif 353 354 for (int i = start; i <= end; i++) { 355 /* 356 * IPI handler 357 */ 358 /* 359 * Use 0xdeadbeef as the argument value for irq 0, 360 * if we used 0, the intr code will give the trap frame 361 * pointer instead. 362 */ 363 arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i, 364 INTR_TYPE_MISC | INTR_EXCL, NULL); 365 366 /* Enable ipi */ 367 arm_unmask_irq(i); 368 } 369 atomic_store_rel_int(&aps_ready, 1); 370 371 printf("Release APs\n"); 372 373 for (loop_counter = 0; loop_counter < 2000; loop_counter++) { 374 if (smp_started) 375 return; 376 DELAY(1000); 377 } 378 printf("AP's not started\n"); 379} 380 381SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 382 383struct cpu_group * 384cpu_topo(void) 385{ 386 387 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); 388} 389 390void 391cpu_mp_setmaxid(void) 392{ 393 394 platform_mp_setmaxid(); 395} 396 397/* Sending IPI */ 398void 399ipi_all_but_self(u_int ipi) 400{ 401 cpuset_t other_cpus; 402 403 other_cpus = all_cpus; 404 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 405 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 406 platform_ipi_send(other_cpus, ipi); 407} 408 409void 410ipi_cpu(int cpu, u_int ipi) 411{ 412 cpuset_t cpus; 413 414 CPU_ZERO(&cpus); 415 CPU_SET(cpu, &cpus); 416 417 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); 418 platform_ipi_send(cpus, ipi); 419} 420 421void 422ipi_selected(cpuset_t cpus, u_int ipi) 423{ 424 425 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 426 platform_ipi_send(cpus, ipi); 427} 428 429void 430tlb_broadcast(int ipi) 431{ 432 433 if (smp_started) 434 ipi_all_but_self(ipi); 435} 436