1129198Scognet/* $NetBSD: arm32_machdep.c,v 1.44 2004/03/24 15:34:47 atatat Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 2004 Olivier Houchard 5129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 6129198Scognet * Copyright (c) 1994 Brini. 7129198Scognet * All rights reserved. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 18315059Smmel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19315059Smmel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20315059Smmel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21315059Smmel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22315059Smmel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23315059Smmel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24315059Smmel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28129198Scognet * SUCH DAMAGE. 29129198Scognet */ 30129198Scognet 31177883Simp#include "opt_ddb.h" 32177883Simp 33129198Scognet#include <sys/cdefs.h> 34129198Scognet__FBSDID("$FreeBSD: stable/11/sys/arm/arm/machdep_kdb.c 341491 2018-12-04 19:07:10Z markj $"); 35129198Scognet 36129198Scognet#include <sys/param.h> 37141378Snjl#include <sys/proc.h> 38129198Scognet#include <sys/systm.h> 39129198Scognet 40141378Snjl#include <machine/cpu.h> 41141378Snjl#include <machine/reg.h> 42129198Scognet 43272098Sroyger#ifdef DDB 44272098Sroyger#include <ddb/ddb.h> 45272098Sroyger 46282547Szbb#if __ARM_ARCH >= 6 47282547Szbb 48282547SzbbDB_SHOW_COMMAND(cp15, db_show_cp15) 49282547Szbb{ 50282547Szbb u_int reg; 51282547Szbb 52282547Szbb reg = cp15_midr_get(); 53282547Szbb db_printf("Cpu ID: 0x%08x\n", reg); 54282547Szbb reg = cp15_ctr_get(); 55282547Szbb db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 56282547Szbb 57282547Szbb reg = cp15_sctlr_get(); 58282547Szbb db_printf("Ctrl: 0x%08x\n",reg); 59282547Szbb reg = cp15_actlr_get(); 60282547Szbb db_printf("Aux Ctrl: 0x%08x\n",reg); 61282547Szbb 62282547Szbb reg = cp15_id_pfr0_get(); 63282547Szbb db_printf("Processor Feat 0: 0x%08x\n", reg); 64282547Szbb reg = cp15_id_pfr1_get(); 65282547Szbb db_printf("Processor Feat 1: 0x%08x\n", reg); 66282547Szbb reg = cp15_id_dfr0_get(); 67282547Szbb db_printf("Debug Feat 0: 0x%08x\n", reg); 68282547Szbb reg = cp15_id_afr0_get(); 69282547Szbb db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 70282547Szbb reg = cp15_id_mmfr0_get(); 71282547Szbb db_printf("Memory Model Feat 0: 0x%08x\n", reg); 72282547Szbb reg = cp15_id_mmfr1_get(); 73282547Szbb db_printf("Memory Model Feat 1: 0x%08x\n", reg); 74282547Szbb reg = cp15_id_mmfr2_get(); 75282547Szbb db_printf("Memory Model Feat 2: 0x%08x\n", reg); 76282547Szbb reg = cp15_id_mmfr3_get(); 77282547Szbb db_printf("Memory Model Feat 3: 0x%08x\n", reg); 78282547Szbb reg = cp15_ttbr_get(); 79282547Szbb db_printf("TTB0: 0x%08x\n", reg); 80282547Szbb} 81282547Szbb 82282547SzbbDB_SHOW_COMMAND(vtop, db_show_vtop) 83282547Szbb{ 84282547Szbb u_int reg; 85282547Szbb 86282547Szbb if (have_addr) { 87282547Szbb cp15_ats1cpr_set(addr); 88282547Szbb reg = cp15_par_get(); 89282547Szbb db_printf("Physical address reg: 0x%08x\n",reg); 90282547Szbb } else 91282547Szbb db_printf("show vtop <virt_addr>\n"); 92282547Szbb} 93282547Szbb#endif /* __ARM_ARCH >= 6 */ 94282547Szbb#endif /* DDB */ 95282547Szbb 96141237Snjlint 97129198Scognetfill_regs(struct thread *td, struct reg *regs) 98129198Scognet{ 99129198Scognet struct trapframe *tf = td->td_frame; 100129198Scognet bcopy(&tf->tf_r0, regs->r, sizeof(regs->r)); 101129198Scognet regs->r_sp = tf->tf_usr_sp; 102129198Scognet regs->r_lr = tf->tf_usr_lr; 103129198Scognet regs->r_pc = tf->tf_pc; 104129198Scognet regs->r_cpsr = tf->tf_spsr; 105129198Scognet return (0); 106129198Scognet} 107341491Smarkj 108129198Scognetint 109129198Scognetfill_fpregs(struct thread *td, struct fpreg *regs) 110129198Scognet{ 111129198Scognet bzero(regs, sizeof(*regs)); 112129198Scognet return (0); 113129198Scognet} 114129198Scognet 115129198Scognetint 116129198Scognetset_regs(struct thread *td, struct reg *regs) 117129198Scognet{ 118129198Scognet struct trapframe *tf = td->td_frame; 119283366Sandrew 120137215Scognet bcopy(regs->r, &tf->tf_r0, sizeof(regs->r)); 121129198Scognet tf->tf_usr_sp = regs->r_sp; 122129198Scognet tf->tf_usr_lr = regs->r_lr; 123129198Scognet tf->tf_pc = regs->r_pc; 124129198Scognet tf->tf_spsr &= ~PSR_FLAGS; 125129198Scognet tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS; 126283366Sandrew return (0); 127129198Scognet} 128129198Scognet 129129198Scognetint 130129198Scognetset_fpregs(struct thread *td, struct fpreg *regs) 131129198Scognet{ 132129198Scognet return (0); 133129198Scognet} 134129198Scognet 135129198Scognetint 136129198Scognetfill_dbregs(struct thread *td, struct dbreg *regs) 137129198Scognet{ 138341491Smarkj 139341491Smarkj bzero(regs, sizeof(*regs)); 140129198Scognet return (0); 141129198Scognet} 142341491Smarkj 143129198Scognetint 144129198Scognetset_dbregs(struct thread *td, struct dbreg *regs) 145129198Scognet{ 146129198Scognet return (0); 147129198Scognet} 148