machdep_intr.c revision 297230
1292426Sadrian/* $NetBSD: intr.c,v 1.12 2003/07/15 00:24:41 lukem Exp $ */ 2292426Sadrian 3292426Sadrian/*- 4292426Sadrian * Copyright (c) 2004 Olivier Houchard. 5292426Sadrian * Copyright (c) 1994-1998 Mark Brinicombe. 6292426Sadrian * All rights reserved. 7292426Sadrian * 8292426Sadrian * Redistribution and use in source and binary forms, with or without 9292426Sadrian * modification, are permitted provided that the following conditions 10292426Sadrian * are met: 11292426Sadrian * 1. Redistributions of source code must retain the above copyright 12292426Sadrian * notice, this list of conditions and the following disclaimer. 13292426Sadrian * 2. Redistributions in binary form must reproduce the above copyright 14292426Sadrian * notice, this list of conditions and the following disclaimer in the 15292426Sadrian * documentation and/or other materials provided with the distribution. 16292426Sadrian * 3. All advertising materials mentioning features or use of this software 17292426Sadrian * must display the following acknowledgement: 18292426Sadrian * This product includes software developed by Mark Brinicombe 19292426Sadrian * for the NetBSD Project. 20292426Sadrian * 4. The name of the company nor the name of the author may be used to 21292426Sadrian * endorse or promote products derived from this software without specific 22292426Sadrian * prior written permission. 23292426Sadrian * 24292426Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25292426Sadrian * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26292426Sadrian * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27292426Sadrian * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28292426Sadrian * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29292426Sadrian * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30292426Sadrian * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31292426Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32292426Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33292426Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34292426Sadrian * SUCH DAMAGE. 35292426Sadrian * 36292426Sadrian * Soft interrupt and other generic interrupt functions. 37292426Sadrian */ 38292426Sadrian 39292426Sadrian#include "opt_platform.h" 40292426Sadrian 41292426Sadrian#include <sys/cdefs.h> 42292426Sadrian__FBSDID("$FreeBSD: head/sys/arm/arm/machdep_intr.c 297230 2016-03-24 09:55:11Z skra $"); 43292426Sadrian 44292426Sadrian#include <sys/param.h> 45292426Sadrian#include <sys/systm.h> 46292426Sadrian#include <sys/syslog.h> 47292426Sadrian#include <sys/kernel.h> 48292426Sadrian#include <sys/malloc.h> 49292426Sadrian#include <sys/proc.h> 50292426Sadrian#include <sys/bus.h> 51292426Sadrian#include <sys/interrupt.h> 52292426Sadrian#include <sys/conf.h> 53292426Sadrian#include <sys/pmc.h> 54292426Sadrian#include <sys/pmckern.h> 55296138Sskra#include <sys/smp.h> 56292426Sadrian 57292426Sadrian#include <machine/atomic.h> 58292426Sadrian#include <machine/bus.h> 59292426Sadrian#include <machine/intr.h> 60292426Sadrian#include <machine/cpu.h> 61296138Sskra#include <machine/smp.h> 62292426Sadrian 63296138Sskra#ifdef ARM_INTRNG 64296138Sskra#include "pic_if.h" 65296138Sskra 66296138Sskra#ifdef SMP 67297230Sskra#define INTR_IPI_NAMELEN (MAXCOMLEN + 1) 68297230Sskra 69297230Sskrastruct intr_ipi { 70297230Sskra intr_ipi_handler_t * ii_handler; 71297230Sskra void * ii_handler_arg; 72297230Sskra intr_ipi_send_t * ii_send; 73297230Sskra void * ii_send_arg; 74297230Sskra char ii_name[INTR_IPI_NAMELEN]; 75297230Sskra u_long * ii_count; 76297230Sskra}; 77297230Sskra 78297230Sskrastatic struct intr_ipi ipi_sources[INTR_IPI_COUNT]; 79297230Sskrau_int ipi_next_num; 80296138Sskra#endif 81296138Sskra#endif 82296138Sskra 83292426Sadrian/* 84292426Sadrian * arm_irq_memory_barrier() 85292426Sadrian * 86292426Sadrian * Ensure all writes to device memory have reached devices before proceeding. 87292426Sadrian * 88292426Sadrian * This is intended to be called from the post-filter and post-thread routines 89292426Sadrian * of an interrupt controller implementation. A peripheral device driver should 90292426Sadrian * use bus_space_barrier() if it needs to ensure a write has reached the 91292426Sadrian * hardware for some reason other than clearing interrupt conditions. 92292426Sadrian * 93292426Sadrian * The need for this function arises from the ARM weak memory ordering model. 94292426Sadrian * Writes to locations mapped with the Device attribute bypass any caches, but 95292426Sadrian * are buffered. Multiple writes to the same device will be observed by that 96292426Sadrian * device in the order issued by the cpu. Writes to different devices may 97292426Sadrian * appear at those devices in a different order than issued by the cpu. That 98292426Sadrian * is, if the cpu writes to device A then device B, the write to device B could 99292426Sadrian * complete before the write to device A. 100292426Sadrian * 101292426Sadrian * Consider a typical device interrupt handler which services the interrupt and 102292426Sadrian * writes to a device status-acknowledge register to clear the interrupt before 103292426Sadrian * returning. That write is posted to the L2 controller which "immediately" 104292426Sadrian * places it in a store buffer and automatically drains that buffer. This can 105292426Sadrian * be less immediate than you'd think... There may be no free slots in the store 106292426Sadrian * buffers, so an existing buffer has to be drained first to make room. The 107292426Sadrian * target bus may be busy with other traffic (such as DMA for various devices), 108292426Sadrian * delaying the drain of the store buffer for some indeterminate time. While 109292426Sadrian * all this delay is happening, execution proceeds on the CPU, unwinding its way 110292426Sadrian * out of the interrupt call stack to the point where the interrupt driver code 111292426Sadrian * is ready to EOI and unmask the interrupt. The interrupt controller may be 112292426Sadrian * accessed via a faster bus than the hardware whose handler just ran; the write 113292426Sadrian * to unmask and EOI the interrupt may complete quickly while the device write 114292426Sadrian * to ack and clear the interrupt source is still lingering in a store buffer 115292426Sadrian * waiting for access to a slower bus. With the interrupt unmasked at the 116292426Sadrian * interrupt controller but still active at the device, as soon as interrupts 117292426Sadrian * are enabled on the core the device re-interrupts immediately: now you've got 118292426Sadrian * a spurious interrupt on your hands. 119292426Sadrian * 120292426Sadrian * The right way to fix this problem is for every device driver to use the 121292426Sadrian * proper bus_space_barrier() calls in its interrupt handler. For ARM a single 122292426Sadrian * barrier call at the end of the handler would work. This would have to be 123292426Sadrian * done to every driver in the system, not just arm-specific drivers. 124292426Sadrian * 125292426Sadrian * Another potential fix is to map all device memory as Strongly-Ordered rather 126292426Sadrian * than Device memory, which takes the store buffers out of the picture. This 127292426Sadrian * has a pretty big impact on overall system performance, because each strongly 128292426Sadrian * ordered memory access causes all L2 store buffers to be drained. 129292426Sadrian * 130292426Sadrian * A compromise solution is to have the interrupt controller implementation call 131292426Sadrian * this function to establish a barrier between writes to the interrupt-source 132292426Sadrian * device and writes to the interrupt controller device. 133292426Sadrian * 134292426Sadrian * This takes the interrupt number as an argument, and currently doesn't use it. 135292426Sadrian * The plan is that maybe some day there is a way to flag certain interrupts as 136292426Sadrian * "memory barrier safe" and we can avoid this overhead with them. 137292426Sadrian */ 138292426Sadrianvoid 139292426Sadrianarm_irq_memory_barrier(uintptr_t irq) 140292426Sadrian{ 141292426Sadrian 142292426Sadrian dsb(); 143292426Sadrian cpu_l2cache_drain_writebuf(); 144292426Sadrian} 145292426Sadrian 146296138Sskra#ifdef ARM_INTRNG 147296138Sskra#ifdef SMP 148297230Sskrastatic inline struct intr_ipi * 149296138Sskraintr_ipi_lookup(u_int ipi) 150296138Sskra{ 151296138Sskra 152296138Sskra if (ipi >= INTR_IPI_COUNT) 153296138Sskra panic("%s: no such IPI %u", __func__, ipi); 154296138Sskra 155296138Sskra return (&ipi_sources[ipi]); 156296138Sskra} 157296138Sskra 158296138Sskravoid 159297230Sskraintr_ipi_dispatch(u_int ipi, struct trapframe *tf) 160296138Sskra{ 161296138Sskra void *arg; 162297230Sskra struct intr_ipi *ii; 163296138Sskra 164297230Sskra ii = intr_ipi_lookup(ipi); 165297230Sskra if (ii->ii_count == NULL) 166297230Sskra panic("%s: not setup IPI %u", __func__, ipi); 167296138Sskra 168297230Sskra intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid)); 169296138Sskra 170296138Sskra /* 171296138Sskra * Supply ipi filter with trapframe argument 172296138Sskra * if none is registered. 173296138Sskra */ 174297230Sskra arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf; 175297230Sskra ii->ii_handler(arg); 176296138Sskra} 177296138Sskra 178297230Sskravoid 179297230Sskraintr_ipi_send(cpuset_t cpus, u_int ipi) 180296138Sskra{ 181297230Sskra struct intr_ipi *ii; 182296138Sskra 183297230Sskra ii = intr_ipi_lookup(ipi); 184297230Sskra if (ii->ii_count == NULL) 185297230Sskra panic("%s: not setup IPI %u", __func__, ipi); 186296138Sskra 187297230Sskra ii->ii_send(ii->ii_send_arg, cpus); 188297230Sskra} 189296138Sskra 190297230Sskravoid 191297230Sskraintr_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, 192297230Sskra void *h_arg, intr_ipi_send_t *send, void *s_arg) 193297230Sskra{ 194297230Sskra struct intr_ipi *ii; 195296138Sskra 196297230Sskra ii = intr_ipi_lookup(ipi); 197297230Sskra 198297230Sskra KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi)); 199297230Sskra KASSERT(send != NULL, ("%s: ipi %u no sender", __func__, ipi)); 200297230Sskra KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi)); 201297230Sskra 202297230Sskra ii->ii_handler = hand; 203297230Sskra ii->ii_handler_arg = h_arg; 204297230Sskra ii->ii_send = send; 205297230Sskra ii->ii_send_arg = s_arg; 206297230Sskra strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN); 207297230Sskra ii->ii_count = intr_ipi_setup_counters(name); 208296138Sskra} 209296138Sskra 210296138Sskra/* 211297230Sskra * Send IPI thru interrupt controller. 212297230Sskra */ 213297230Sskrastatic void 214297230Sskrapic_ipi_send(void *arg, cpuset_t cpus) 215297230Sskra{ 216297230Sskra 217297230Sskra KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); 218297230Sskra PIC_IPI_SEND(intr_irq_root_dev, arg, cpus); 219297230Sskra} 220297230Sskra 221297230Sskra/* 222297230Sskra * Setup IPI handler on interrupt controller. 223296138Sskra * 224296138Sskra * Not SMP coherent. 225296138Sskra */ 226296138Sskraint 227297230Sskraintr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, 228297230Sskra void *arg) 229296138Sskra{ 230297230Sskra int error; 231296138Sskra struct intr_irqsrc *isrc; 232296138Sskra 233297230Sskra KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); 234296138Sskra 235297230Sskra isrc = intr_isrc_alloc(INTR_ISRCT_NAMESPACE, 0); 236297230Sskra isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI; 237297230Sskra isrc->isrc_nspc_num = ipi_next_num; 238296138Sskra 239297230Sskra error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, isrc); 240297230Sskra if (error != 0) 241297230Sskra return (error); 242296138Sskra 243297230Sskra ipi_next_num++; 244297230Sskra 245297230Sskra isrc->isrc_dev = intr_irq_root_dev; 246296138Sskra isrc->isrc_handlers = 1; 247297230Sskra intr_ipi_setup(ipi, name, hand, arg, pic_ipi_send, isrc); 248296138Sskra return (0); 249296138Sskra} 250296138Sskra#endif 251296138Sskra#endif 252