1292426Sadrian/*- 2297539Sskra * Copyright (c) 2015-2016 Svatopluk Kraus 3297539Sskra * Copyright (c) 2015-2016 Michal Meloun 4292426Sadrian * All rights reserved. 5292426Sadrian * 6292426Sadrian * Redistribution and use in source and binary forms, with or without 7292426Sadrian * modification, are permitted provided that the following conditions 8292426Sadrian * are met: 9292426Sadrian * 1. Redistributions of source code must retain the above copyright 10292426Sadrian * notice, this list of conditions and the following disclaimer. 11292426Sadrian * 2. Redistributions in binary form must reproduce the above copyright 12292426Sadrian * notice, this list of conditions and the following disclaimer in the 13292426Sadrian * documentation and/or other materials provided with the distribution. 14292426Sadrian * 15297539Sskra * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16297539Sskra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17297539Sskra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18297539Sskra * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19297539Sskra * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20297539Sskra * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21297539Sskra * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22292426Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23292426Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24292426Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25292426Sadrian * SUCH DAMAGE. 26292426Sadrian */ 27292426Sadrian 28292426Sadrian#include "opt_platform.h" 29292426Sadrian 30292426Sadrian#include <sys/cdefs.h> 31292426Sadrian__FBSDID("$FreeBSD$"); 32292426Sadrian 33292426Sadrian#include <sys/param.h> 34292426Sadrian#include <sys/systm.h> 35292426Sadrian#include <sys/syslog.h> 36292426Sadrian#include <sys/kernel.h> 37292426Sadrian#include <sys/malloc.h> 38292426Sadrian#include <sys/proc.h> 39292426Sadrian#include <sys/bus.h> 40292426Sadrian#include <sys/interrupt.h> 41292426Sadrian#include <sys/conf.h> 42292426Sadrian#include <sys/pmc.h> 43292426Sadrian#include <sys/pmckern.h> 44296138Sskra#include <sys/smp.h> 45292426Sadrian 46292426Sadrian#include <machine/atomic.h> 47292426Sadrian#include <machine/bus.h> 48292426Sadrian#include <machine/intr.h> 49292426Sadrian#include <machine/cpu.h> 50296138Sskra#include <machine/smp.h> 51292426Sadrian 52298068Sandrew#ifdef INTRNG 53296138Sskra#include "pic_if.h" 54296138Sskra 55296138Sskra#ifdef SMP 56297230Sskra#define INTR_IPI_NAMELEN (MAXCOMLEN + 1) 57297230Sskra 58297230Sskrastruct intr_ipi { 59297230Sskra intr_ipi_handler_t * ii_handler; 60297230Sskra void * ii_handler_arg; 61297230Sskra intr_ipi_send_t * ii_send; 62297230Sskra void * ii_send_arg; 63297230Sskra char ii_name[INTR_IPI_NAMELEN]; 64297230Sskra u_long * ii_count; 65297230Sskra}; 66297230Sskra 67297230Sskrastatic struct intr_ipi ipi_sources[INTR_IPI_COUNT]; 68296138Sskra#endif 69296138Sskra#endif 70296138Sskra 71292426Sadrian/* 72292426Sadrian * arm_irq_memory_barrier() 73292426Sadrian * 74292426Sadrian * Ensure all writes to device memory have reached devices before proceeding. 75292426Sadrian * 76292426Sadrian * This is intended to be called from the post-filter and post-thread routines 77292426Sadrian * of an interrupt controller implementation. A peripheral device driver should 78292426Sadrian * use bus_space_barrier() if it needs to ensure a write has reached the 79292426Sadrian * hardware for some reason other than clearing interrupt conditions. 80292426Sadrian * 81292426Sadrian * The need for this function arises from the ARM weak memory ordering model. 82292426Sadrian * Writes to locations mapped with the Device attribute bypass any caches, but 83292426Sadrian * are buffered. Multiple writes to the same device will be observed by that 84292426Sadrian * device in the order issued by the cpu. Writes to different devices may 85292426Sadrian * appear at those devices in a different order than issued by the cpu. That 86292426Sadrian * is, if the cpu writes to device A then device B, the write to device B could 87292426Sadrian * complete before the write to device A. 88292426Sadrian * 89292426Sadrian * Consider a typical device interrupt handler which services the interrupt and 90292426Sadrian * writes to a device status-acknowledge register to clear the interrupt before 91292426Sadrian * returning. That write is posted to the L2 controller which "immediately" 92292426Sadrian * places it in a store buffer and automatically drains that buffer. This can 93292426Sadrian * be less immediate than you'd think... There may be no free slots in the store 94292426Sadrian * buffers, so an existing buffer has to be drained first to make room. The 95292426Sadrian * target bus may be busy with other traffic (such as DMA for various devices), 96292426Sadrian * delaying the drain of the store buffer for some indeterminate time. While 97292426Sadrian * all this delay is happening, execution proceeds on the CPU, unwinding its way 98292426Sadrian * out of the interrupt call stack to the point where the interrupt driver code 99292426Sadrian * is ready to EOI and unmask the interrupt. The interrupt controller may be 100292426Sadrian * accessed via a faster bus than the hardware whose handler just ran; the write 101292426Sadrian * to unmask and EOI the interrupt may complete quickly while the device write 102292426Sadrian * to ack and clear the interrupt source is still lingering in a store buffer 103292426Sadrian * waiting for access to a slower bus. With the interrupt unmasked at the 104292426Sadrian * interrupt controller but still active at the device, as soon as interrupts 105292426Sadrian * are enabled on the core the device re-interrupts immediately: now you've got 106292426Sadrian * a spurious interrupt on your hands. 107292426Sadrian * 108292426Sadrian * The right way to fix this problem is for every device driver to use the 109292426Sadrian * proper bus_space_barrier() calls in its interrupt handler. For ARM a single 110292426Sadrian * barrier call at the end of the handler would work. This would have to be 111292426Sadrian * done to every driver in the system, not just arm-specific drivers. 112292426Sadrian * 113292426Sadrian * Another potential fix is to map all device memory as Strongly-Ordered rather 114292426Sadrian * than Device memory, which takes the store buffers out of the picture. This 115292426Sadrian * has a pretty big impact on overall system performance, because each strongly 116292426Sadrian * ordered memory access causes all L2 store buffers to be drained. 117292426Sadrian * 118292426Sadrian * A compromise solution is to have the interrupt controller implementation call 119292426Sadrian * this function to establish a barrier between writes to the interrupt-source 120292426Sadrian * device and writes to the interrupt controller device. 121292426Sadrian * 122292426Sadrian * This takes the interrupt number as an argument, and currently doesn't use it. 123292426Sadrian * The plan is that maybe some day there is a way to flag certain interrupts as 124292426Sadrian * "memory barrier safe" and we can avoid this overhead with them. 125292426Sadrian */ 126292426Sadrianvoid 127292426Sadrianarm_irq_memory_barrier(uintptr_t irq) 128292426Sadrian{ 129292426Sadrian 130292426Sadrian dsb(); 131292426Sadrian cpu_l2cache_drain_writebuf(); 132292426Sadrian} 133292426Sadrian 134298068Sandrew#ifdef INTRNG 135296138Sskra#ifdef SMP 136297230Sskrastatic inline struct intr_ipi * 137296138Sskraintr_ipi_lookup(u_int ipi) 138296138Sskra{ 139296138Sskra 140296138Sskra if (ipi >= INTR_IPI_COUNT) 141296138Sskra panic("%s: no such IPI %u", __func__, ipi); 142296138Sskra 143296138Sskra return (&ipi_sources[ipi]); 144296138Sskra} 145296138Sskra 146296138Sskravoid 147297230Sskraintr_ipi_dispatch(u_int ipi, struct trapframe *tf) 148296138Sskra{ 149296138Sskra void *arg; 150297230Sskra struct intr_ipi *ii; 151296138Sskra 152297230Sskra ii = intr_ipi_lookup(ipi); 153297230Sskra if (ii->ii_count == NULL) 154297230Sskra panic("%s: not setup IPI %u", __func__, ipi); 155296138Sskra 156297230Sskra intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid)); 157296138Sskra 158296138Sskra /* 159296138Sskra * Supply ipi filter with trapframe argument 160296138Sskra * if none is registered. 161296138Sskra */ 162297230Sskra arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf; 163297230Sskra ii->ii_handler(arg); 164296138Sskra} 165296138Sskra 166297230Sskravoid 167297230Sskraintr_ipi_send(cpuset_t cpus, u_int ipi) 168296138Sskra{ 169297230Sskra struct intr_ipi *ii; 170296138Sskra 171297230Sskra ii = intr_ipi_lookup(ipi); 172297230Sskra if (ii->ii_count == NULL) 173297230Sskra panic("%s: not setup IPI %u", __func__, ipi); 174296138Sskra 175297539Sskra ii->ii_send(ii->ii_send_arg, cpus, ipi); 176297230Sskra} 177296138Sskra 178297230Sskravoid 179297230Sskraintr_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, 180297230Sskra void *h_arg, intr_ipi_send_t *send, void *s_arg) 181297230Sskra{ 182297230Sskra struct intr_ipi *ii; 183296138Sskra 184297230Sskra ii = intr_ipi_lookup(ipi); 185297230Sskra 186297230Sskra KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi)); 187297230Sskra KASSERT(send != NULL, ("%s: ipi %u no sender", __func__, ipi)); 188297230Sskra KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi)); 189297230Sskra 190297230Sskra ii->ii_handler = hand; 191297230Sskra ii->ii_handler_arg = h_arg; 192297230Sskra ii->ii_send = send; 193297230Sskra ii->ii_send_arg = s_arg; 194297230Sskra strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN); 195297230Sskra ii->ii_count = intr_ipi_setup_counters(name); 196296138Sskra} 197296138Sskra 198296138Sskra/* 199297230Sskra * Send IPI thru interrupt controller. 200297230Sskra */ 201297230Sskrastatic void 202297539Sskrapic_ipi_send(void *arg, cpuset_t cpus, u_int ipi) 203297230Sskra{ 204297230Sskra 205297230Sskra KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); 206297539Sskra PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi); 207297230Sskra} 208297230Sskra 209297230Sskra/* 210297230Sskra * Setup IPI handler on interrupt controller. 211296138Sskra * 212296138Sskra * Not SMP coherent. 213296138Sskra */ 214296138Sskraint 215297230Sskraintr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, 216297230Sskra void *arg) 217296138Sskra{ 218297230Sskra int error; 219296138Sskra struct intr_irqsrc *isrc; 220296138Sskra 221297230Sskra KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); 222296138Sskra 223297539Sskra error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc); 224297230Sskra if (error != 0) 225297230Sskra return (error); 226296138Sskra 227297539Sskra isrc->isrc_handlers++; 228297230Sskra intr_ipi_setup(ipi, name, hand, arg, pic_ipi_send, isrc); 229296138Sskra return (0); 230296138Sskra} 231296138Sskra#endif 232296138Sskra#endif 233