cpufunc_asm_armv6.S revision 280813
1239701Sgonzo/* $NetBSD: cpufunc_asm_armv6.S,v 1.4 2010/12/10 02:06:22 bsh Exp $ */ 2239701Sgonzo 3239701Sgonzo/* 4239701Sgonzo * Copyright (c) 2002, 2005 ARM Limited 5239701Sgonzo * Portions Copyright (c) 2007 Microsoft 6239701Sgonzo * All rights reserved. 7239701Sgonzo * 8239701Sgonzo * Redistribution and use in source and binary forms, with or without 9239701Sgonzo * modification, are permitted provided that the following conditions 10239701Sgonzo * are met: 11239701Sgonzo * 1. Redistributions of source code must retain the above copyright 12239701Sgonzo * notice, this list of conditions and the following disclaimer. 13239701Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 14239701Sgonzo * notice, this list of conditions and the following disclaimer in the 15239701Sgonzo * documentation and/or other materials provided with the distribution. 16239701Sgonzo * 3. The name of the company may not be used to endorse or promote 17239701Sgonzo * products derived from this software without specific prior written 18239701Sgonzo * permission. 19239701Sgonzo * 20239701Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 21239701Sgonzo * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 22239701Sgonzo * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23239701Sgonzo * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 24239701Sgonzo * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25239701Sgonzo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26239701Sgonzo * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27239701Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28239701Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29239701Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30239701Sgonzo * SUCH DAMAGE. 31239701Sgonzo * 32239701Sgonzo * ARMv6 assembly functions for manipulating caches. 33239701Sgonzo * These routines can be used by any core that supports the mcrr address 34239701Sgonzo * range operations. 35239701Sgonzo */ 36239701Sgonzo 37239701Sgonzo/* 38239701Sgonzo * $FreeBSD: head/sys/arm/arm/cpufunc_asm_armv6.S 280813 2015-03-29 18:44:15Z andrew $ 39239701Sgonzo */ 40239701Sgonzo 41239701Sgonzo#include <machine/asm.h> 42239701Sgonzo 43239701Sgonzo .arch armv6 44239701Sgonzo 45239701Sgonzo/* 46239701Sgonzo * Functions to set the MMU Translation Table Base register 47239701Sgonzo * 48239701Sgonzo * We need to clean and flush the cache as it uses virtual 49239701Sgonzo * addresses that are about to change. 50239701Sgonzo */ 51239701SgonzoENTRY(armv6_setttb) 52239701Sgonzo mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 53239701Sgonzo 54239701Sgonzo mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 55239701Sgonzo 56239701Sgonzo mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 57239701Sgonzo RET 58248361SandrewEND(armv6_setttb) 59239701Sgonzo 60239701Sgonzo/* 61239701Sgonzo * Cache operations. 62239701Sgonzo */ 63239701Sgonzo 64239701Sgonzo/* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */ 65239701SgonzoENTRY(armv6_dcache_wb_range) 66239701Sgonzo add r1, r1, r0 67239701Sgonzo sub r1, r1, #1 68239701Sgonzo mcrr p15, 0, r1, r0, c12 /* clean D cache range */ 69239701Sgonzo mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 70239701Sgonzo RET 71248361SandrewEND(armv6_dcache_wb_range) 72239701Sgonzo 73239701Sgonzo/* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */ 74239701SgonzoENTRY(armv6_dcache_wbinv_range) 75239701Sgonzo add r1, r1, r0 76239701Sgonzo sub r1, r1, #1 77239701Sgonzo mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */ 78239701Sgonzo mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 79239701Sgonzo RET 80248361SandrewEND(armv6_dcache_wbinv_range) 81239701Sgonzo 82239701Sgonzo/* 83239701Sgonzo * Note, we must not invalidate everything. If the range is too big we 84239701Sgonzo * must use wb-inv of the entire cache. 85239701Sgonzo * 86239701Sgonzo * LINTSTUB: void armv6_dcache_inv_range(vaddr_t, vsize_t); 87239701Sgonzo */ 88239701SgonzoENTRY(armv6_dcache_inv_range) 89239701Sgonzo add r1, r1, r0 90239701Sgonzo sub r1, r1, #1 91239701Sgonzo mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */ 92239701Sgonzo mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 93239701Sgonzo RET 94248361SandrewEND(armv6_dcache_inv_range) 95239701Sgonzo 96239701Sgonzo/* LINTSTUB: void armv6_idcache_wbinv_all(void); */ 97239701SgonzoENTRY_NP(armv6_idcache_wbinv_all) 98239701Sgonzo /* 99239701Sgonzo * We assume that the code here can never be out of sync with the 100239701Sgonzo * dcache, so that we can safely flush the Icache and fall through 101239701Sgonzo * into the Dcache purging code. 102239701Sgonzo */ 103239701Sgonzo mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 104239701Sgonzo 105280813Sandrew /* Purge Dcache. */ 106239701Sgonzo mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ 107239701Sgonzo mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 108239701Sgonzo RET 109248361SandrewEND(armv6_idcache_wbinv_all) 110248361Sandrew 111262420SianENTRY(armv6_idcache_inv_all) 112262420Sian mov r0, #0 113262420Sian mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */ 114262420Sian RET 115262420SianEND(armv6_idcache_inv_all) 116262420Sian 117