cpufunc_asm_arm9.S revision 276596
1152723Scognet/* $NetBSD: cpufunc_asm_arm9.S,v 1.3 2004/01/26 15:54:16 rearnsha Exp $ */ 2129198Scognet 3152723Scognet/* 4152723Scognet * Copyright (c) 2001, 2004 ARM Limited 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Redistribution and use in source and binary forms, with or without 8129198Scognet * modification, are permitted provided that the following conditions 9129198Scognet * are met: 10129198Scognet * 1. Redistributions of source code must retain the above copyright 11129198Scognet * notice, this list of conditions and the following disclaimer. 12129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer in the 14129198Scognet * documentation and/or other materials provided with the distribution. 15129198Scognet * 3. The name of the company may not be used to endorse or promote 16129198Scognet * products derived from this software without specific prior written 17129198Scognet * permission. 18129198Scognet * 19129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29129198Scognet * SUCH DAMAGE. 30129198Scognet * 31129198Scognet * ARM9 assembly functions for CPU / MMU / TLB specific operations 32129198Scognet */ 33236991Simp 34129198Scognet#include <machine/asm.h> 35129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/cpufunc_asm_arm9.S 276596 2015-01-02 23:46:26Z ian $"); 36129198Scognet 37129198Scognet/* 38129198Scognet * Functions to set the MMU Translation Table Base register 39129198Scognet * 40129198Scognet * We need to clean and flush the cache as it uses virtual 41129198Scognet * addresses that are about to change. 42129198Scognet */ 43129198ScognetENTRY(arm9_setttb) 44152723Scognet stmfd sp!, {r0, lr} 45152723Scognet bl _C_LABEL(arm9_idcache_wbinv_all) 46152723Scognet ldmfd sp!, {r0, lr} 47129198Scognet 48129198Scognet mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 49129198Scognet 50129198Scognet mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 51152723Scognet mov pc, lr 52248361SandrewEND(arm9_setttb) 53129198Scognet 54129198Scognet/* 55129198Scognet * TLB functions 56129198Scognet */ 57129198ScognetENTRY(arm9_tlb_flushID_SE) 58129198Scognet mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 59129198Scognet mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 60152723Scognet mov pc, lr 61248361SandrewEND(arm9_tlb_flushID_SE) 62129198Scognet 63129198Scognet/* 64152723Scognet * Cache operations. For the entire cache we use the set/index 65152723Scognet * operations. 66129198Scognet */ 67152723Scognet s_max .req r0 68152723Scognet i_max .req r1 69152723Scognet s_inc .req r2 70152723Scognet i_inc .req r3 71129198Scognet 72152723ScognetENTRY_NP(arm9_icache_sync_range) 73152723Scognet ldr ip, .Larm9_line_size 74152723Scognet cmp r1, #0x4000 75152723Scognet bcs .Larm9_icache_sync_all 76152723Scognet ldr ip, [ip] 77152723Scognet sub r3, ip, #1 78152723Scognet and r2, r0, r3 79152723Scognet add r1, r1, r2 80152723Scognet bic r0, r0, r3 81152723Scognet.Larm9_sync_next: 82152723Scognet mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 83152723Scognet mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 84152723Scognet add r0, r0, ip 85152723Scognet subs r1, r1, ip 86246001Sian bhi .Larm9_sync_next 87152723Scognet mov pc, lr 88248361SandrewEND(arm9_icache_sync_range) 89129198Scognet 90152723ScognetENTRY_NP(arm9_icache_sync_all) 91152723Scognet.Larm9_icache_sync_all: 92152723Scognet /* 93152723Scognet * We assume that the code here can never be out of sync with the 94152723Scognet * dcache, so that we can safely flush the Icache and fall through 95152723Scognet * into the Dcache cleaning code. 96152723Scognet */ 97152723Scognet mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 98152723Scognet /* Fall through to clean Dcache. */ 99129198Scognet 100152723Scognet.Larm9_dcache_wb: 101152723Scognet ldr ip, .Larm9_cache_data 102152723Scognet ldmia ip, {s_max, i_max, s_inc, i_inc} 103152723Scognet.Lnext_set: 104152723Scognet orr ip, s_max, i_max 105152723Scognet.Lnext_index: 106152723Scognet mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 107246001Sian subs ip, ip, i_inc 108246001Sian bhs .Lnext_index /* Next index */ 109152723Scognet subs s_max, s_max, s_inc 110246001Sian bhs .Lnext_set /* Next set */ 111152723Scognet mov pc, lr 112248361SandrewEND(arm9_icache_sync_all) 113129198Scognet 114152723Scognet.Larm9_line_size: 115152723Scognet .word _C_LABEL(arm_pdcache_line_size) 116129198Scognet 117152723ScognetENTRY(arm9_dcache_wb_range) 118152723Scognet ldr ip, .Larm9_line_size 119152723Scognet cmp r1, #0x4000 120152723Scognet bcs .Larm9_dcache_wb 121152723Scognet ldr ip, [ip] 122152723Scognet sub r3, ip, #1 123152723Scognet and r2, r0, r3 124152723Scognet add r1, r1, r2 125152723Scognet bic r0, r0, r3 126152723Scognet.Larm9_wb_next: 127152723Scognet mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 128152723Scognet add r0, r0, ip 129152723Scognet subs r1, r1, ip 130246001Sian bhi .Larm9_wb_next 131152723Scognet mov pc, lr 132248361SandrewEND(arm9_dcache_wb_range) 133152723Scognet 134152723ScognetENTRY(arm9_dcache_wbinv_range) 135152723Scognet ldr ip, .Larm9_line_size 136152723Scognet cmp r1, #0x4000 137152723Scognet bcs .Larm9_dcache_wbinv_all 138152723Scognet ldr ip, [ip] 139152723Scognet sub r3, ip, #1 140152723Scognet and r2, r0, r3 141152723Scognet add r1, r1, r2 142152723Scognet bic r0, r0, r3 143152723Scognet.Larm9_wbinv_next: 144152723Scognet mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ 145152723Scognet add r0, r0, ip 146152723Scognet subs r1, r1, ip 147246001Sian bhi .Larm9_wbinv_next 148152723Scognet mov pc, lr 149248361SandrewEND(arm9_dcache_wbinv_range) 150152723Scognet 151129198Scognet/* 152152723Scognet * Note, we must not invalidate everything. If the range is too big we 153152723Scognet * must use wb-inv of the entire cache. 154129198Scognet */ 155152723ScognetENTRY(arm9_dcache_inv_range) 156152723Scognet ldr ip, .Larm9_line_size 157152723Scognet cmp r1, #0x4000 158152723Scognet bcs .Larm9_dcache_wbinv_all 159152723Scognet ldr ip, [ip] 160152723Scognet sub r3, ip, #1 161152723Scognet and r2, r0, r3 162152723Scognet add r1, r1, r2 163152723Scognet bic r0, r0, r3 164152723Scognet.Larm9_inv_next: 165152723Scognet mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */ 166152723Scognet add r0, r0, ip 167152723Scognet subs r1, r1, ip 168246001Sian bhi .Larm9_inv_next 169152723Scognet mov pc, lr 170248361SandrewEND(arm9_dcache_inv_range) 171129198Scognet 172152723ScognetENTRY(arm9_idcache_wbinv_range) 173152723Scognet ldr ip, .Larm9_line_size 174152723Scognet cmp r1, #0x4000 175152723Scognet bcs .Larm9_idcache_wbinv_all 176152723Scognet ldr ip, [ip] 177152723Scognet sub r3, ip, #1 178152723Scognet and r2, r0, r3 179152723Scognet add r1, r1, r2 180152723Scognet bic r0, r0, r3 181152723Scognet.Larm9_id_wbinv_next: 182152723Scognet mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 183152723Scognet mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ 184152723Scognet add r0, r0, ip 185152723Scognet subs r1, r1, ip 186246001Sian bhi .Larm9_id_wbinv_next 187152723Scognet mov pc, lr 188248361SandrewEND(arm9_idcache_wbinv_range) 189129198Scognet 190152723ScognetENTRY_NP(arm9_idcache_wbinv_all) 191152723Scognet.Larm9_idcache_wbinv_all: 192152723Scognet /* 193152723Scognet * We assume that the code here can never be out of sync with the 194152723Scognet * dcache, so that we can safely flush the Icache and fall through 195152723Scognet * into the Dcache purging code. 196152723Scognet */ 197167761Skevlo mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 198152723Scognet /* Fall through */ 199129198Scognet 200269390SianEENTRY(arm9_dcache_wbinv_all) 201152723Scognet.Larm9_dcache_wbinv_all: 202152723Scognet ldr ip, .Larm9_cache_data 203152723Scognet ldmia ip, {s_max, i_max, s_inc, i_inc} 204152723Scognet.Lnext_set_inv: 205152723Scognet orr ip, s_max, i_max 206152723Scognet.Lnext_index_inv: 207152723Scognet mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */ 208246001Sian subs ip, ip, i_inc 209246001Sian bhs .Lnext_index_inv /* Next index */ 210152723Scognet subs s_max, s_max, s_inc 211246001Sian bhs .Lnext_set_inv /* Next set */ 212152723Scognet mov pc, lr 213269390SianEEND(arm9_dcache_wbinv_all) 214248361SandrewEND(arm9_idcache_wbinv_all) 215129198Scognet 216152723Scognet.Larm9_cache_data: 217152723Scognet .word _C_LABEL(arm9_dcache_sets_max) 218152723Scognet 219129198Scognet/* 220129198Scognet * Context switch. 221129198Scognet * 222129198Scognet * These is the CPU-specific parts of the context switcher cpu_switch() 223129198Scognet * These functions actually perform the TTB reload. 224129198Scognet * 225129198Scognet * NOTE: Special calling convention 226129198Scognet * r1, r4-r13 must be preserved 227129198Scognet */ 228129198ScognetENTRY(arm9_context_switch) 229129198Scognet /* 230129198Scognet * We can assume that the caches will only contain kernel addresses 231129198Scognet * at this point. So no need to flush them again. 232129198Scognet */ 233129198Scognet mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 234129198Scognet mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ 235129198Scognet mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ 236129198Scognet 237129198Scognet /* Paranoia -- make sure the pipeline is empty. */ 238129198Scognet nop 239129198Scognet nop 240129198Scognet nop 241152723Scognet mov pc, lr 242248361SandrewEND(arm9_context_switch) 243152723Scognet 244152723Scognet .bss 245152723Scognet 246152723Scognet/* XXX The following macros should probably be moved to asm.h */ 247152723Scognet#define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x: 248152723Scognet#define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x)) 249152723Scognet 250152723Scognet/* 251152723Scognet * Parameters for the cache cleaning code. Note that the order of these 252236991Simp * four variables is assumed in the code above. Hence the reason for 253152723Scognet * declaring them in the assembler file. 254152723Scognet */ 255276596Sian .align 2 256152723ScognetC_OBJECT(arm9_dcache_sets_max) 257152723Scognet .space 4 258152723ScognetC_OBJECT(arm9_dcache_index_max) 259152723Scognet .space 4 260152723ScognetC_OBJECT(arm9_dcache_sets_inc) 261152723Scognet .space 4 262152723ScognetC_OBJECT(arm9_dcache_index_inc) 263152723Scognet .space 4 264