busdma_machdep-v6.c revision 286969
1/*- 2 * Copyright (c) 2012-2014 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 286969 2015-08-20 19:39:15Z ian $"); 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43#include <sys/bus.h> 44#include <sys/busdma_bufalloc.h> 45#include <sys/counter.h> 46#include <sys/interrupt.h> 47#include <sys/kernel.h> 48#include <sys/ktr.h> 49#include <sys/lock.h> 50#include <sys/memdesc.h> 51#include <sys/proc.h> 52#include <sys/mutex.h> 53#include <sys/sysctl.h> 54#include <sys/uio.h> 55 56#include <vm/vm.h> 57#include <vm/vm_page.h> 58#include <vm/vm_map.h> 59#include <vm/vm_extern.h> 60#include <vm/vm_kern.h> 61 62#include <machine/atomic.h> 63#include <machine/bus.h> 64#include <machine/cpufunc.h> 65#include <machine/md_var.h> 66 67#define MAX_BPAGES 64 68#define MAX_DMA_SEGMENTS 4096 69#define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2 70#define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3 71#define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE) 72#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 73 74struct bounce_zone; 75 76struct bus_dma_tag { 77 bus_dma_tag_t parent; 78 bus_size_t alignment; 79 bus_size_t boundary; 80 bus_addr_t lowaddr; 81 bus_addr_t highaddr; 82 bus_dma_filter_t *filter; 83 void *filterarg; 84 bus_size_t maxsize; 85 u_int nsegments; 86 bus_size_t maxsegsz; 87 int flags; 88 int ref_count; 89 int map_count; 90 bus_dma_lock_t *lockfunc; 91 void *lockfuncarg; 92 struct bounce_zone *bounce_zone; 93 /* 94 * DMA range for this tag. If the page doesn't fall within 95 * one of these ranges, an error is returned. The caller 96 * may then decide what to do with the transfer. If the 97 * range pointer is NULL, it is ignored. 98 */ 99 struct arm32_dma_range *ranges; 100 int _nranges; 101}; 102 103struct bounce_page { 104 vm_offset_t vaddr; /* kva of bounce buffer */ 105 bus_addr_t busaddr; /* Physical address */ 106 vm_offset_t datavaddr; /* kva of client data */ 107 bus_addr_t dataaddr; /* client physical address */ 108 bus_size_t datacount; /* client data count */ 109 STAILQ_ENTRY(bounce_page) links; 110}; 111 112struct sync_list { 113 vm_offset_t vaddr; /* kva of client data */ 114 bus_addr_t busaddr; /* client physical address */ 115 bus_size_t datacount; /* client data count */ 116}; 117 118int busdma_swi_pending; 119 120struct bounce_zone { 121 STAILQ_ENTRY(bounce_zone) links; 122 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 123 int total_bpages; 124 int free_bpages; 125 int reserved_bpages; 126 int active_bpages; 127 int total_bounced; 128 int total_deferred; 129 int map_count; 130 bus_size_t alignment; 131 bus_addr_t lowaddr; 132 char zoneid[8]; 133 char lowaddrid[20]; 134 struct sysctl_ctx_list sysctl_tree; 135 struct sysctl_oid *sysctl_tree_top; 136}; 137 138static struct mtx bounce_lock; 139static int total_bpages; 140static int busdma_zonecount; 141static uint32_t tags_total; 142static uint32_t maps_total; 143static uint32_t maps_dmamem; 144static uint32_t maps_coherent; 145static counter_u64_t maploads_total; 146static counter_u64_t maploads_bounced; 147static counter_u64_t maploads_coherent; 148static counter_u64_t maploads_dmamem; 149static counter_u64_t maploads_mbuf; 150static counter_u64_t maploads_physmem; 151 152static STAILQ_HEAD(, bounce_zone) bounce_zone_list; 153 154SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 155SYSCTL_UINT(_hw_busdma, OID_AUTO, tags_total, CTLFLAG_RD, &tags_total, 0, 156 "Number of active tags"); 157SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_total, CTLFLAG_RD, &maps_total, 0, 158 "Number of active maps"); 159SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_dmamem, CTLFLAG_RD, &maps_dmamem, 0, 160 "Number of active maps for bus_dmamem_alloc buffers"); 161SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0, 162 "Number of active maps with BUS_DMA_COHERENT flag set"); 163SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, 164 &maploads_total, "Number of load operations performed"); 165SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD, 166 &maploads_bounced, "Number of load operations that used bounce buffers"); 167SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_coherent, CTLFLAG_RD, 168 &maploads_dmamem, "Number of load operations on BUS_DMA_COHERENT memory"); 169SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_dmamem, CTLFLAG_RD, 170 &maploads_dmamem, "Number of load operations on bus_dmamem_alloc buffers"); 171SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_mbuf, CTLFLAG_RD, 172 &maploads_mbuf, "Number of load operations for mbufs"); 173SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_physmem, CTLFLAG_RD, 174 &maploads_physmem, "Number of load operations on physical buffers"); 175SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 176 "Total bounce pages"); 177 178struct bus_dmamap { 179 struct bp_list bpages; 180 int pagesneeded; 181 int pagesreserved; 182 bus_dma_tag_t dmat; 183 struct memdesc mem; 184 pmap_t pmap; 185 bus_dmamap_callback_t *callback; 186 void *callback_arg; 187 int flags; 188#define DMAMAP_COHERENT (1 << 0) 189#define DMAMAP_DMAMEM_ALLOC (1 << 1) 190#define DMAMAP_MBUF (1 << 2) 191 STAILQ_ENTRY(bus_dmamap) links; 192 bus_dma_segment_t *segments; 193 int sync_count; 194 struct sync_list slist[]; 195}; 196 197static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 198static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 199 200static void init_bounce_pages(void *dummy); 201static int alloc_bounce_zone(bus_dma_tag_t dmat); 202static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 203static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 204 int commit); 205static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 206 vm_offset_t vaddr, bus_addr_t addr, 207 bus_size_t size); 208static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 209static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 210 void *buf, bus_size_t buflen, int flags); 211static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 212 vm_paddr_t buf, bus_size_t buflen, int flags); 213static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 214 int flags); 215 216static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 217static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 218static void 219busdma_init(void *dummy) 220{ 221 int uma_flags; 222 223 maploads_total = counter_u64_alloc(M_WAITOK); 224 maploads_bounced = counter_u64_alloc(M_WAITOK); 225 maploads_coherent = counter_u64_alloc(M_WAITOK); 226 maploads_dmamem = counter_u64_alloc(M_WAITOK); 227 maploads_mbuf = counter_u64_alloc(M_WAITOK); 228 maploads_physmem = counter_u64_alloc(M_WAITOK); 229 230 uma_flags = 0; 231 232 /* Create a cache of buffers in standard (cacheable) memory. */ 233 standard_allocator = busdma_bufalloc_create("buffer", 234 arm_dcache_align, /* minimum_alignment */ 235 NULL, /* uma_alloc func */ 236 NULL, /* uma_free func */ 237 uma_flags); /* uma_zcreate_flags */ 238 239#ifdef INVARIANTS 240 /* 241 * Force UMA zone to allocate service structures like 242 * slabs using own allocator. uma_debug code performs 243 * atomic ops on uma_slab_t fields and safety of this 244 * operation is not guaranteed for write-back caches 245 */ 246 uma_flags = UMA_ZONE_OFFPAGE; 247#endif 248 /* 249 * Create a cache of buffers in uncacheable memory, to implement the 250 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 251 */ 252 coherent_allocator = busdma_bufalloc_create("coherent", 253 arm_dcache_align, /* minimum_alignment */ 254 busdma_bufalloc_alloc_uncacheable, 255 busdma_bufalloc_free_uncacheable, 256 uma_flags); /* uma_zcreate_flags */ 257} 258 259/* 260 * This init historically used SI_SUB_VM, but now the init code requires 261 * malloc(9) using M_DEVBUF memory and the pcpu zones for counter(9), which get 262 * set up by SI_SUB_KMEM and SI_ORDER_LAST, so we'll go right after that by 263 * using SI_SUB_KMEM+1. 264 */ 265SYSINIT(busdma, SI_SUB_KMEM+1, SI_ORDER_FIRST, busdma_init, NULL); 266 267/* 268 * This routine checks the exclusion zone constraints from a tag against the 269 * physical RAM available on the machine. If a tag specifies an exclusion zone 270 * but there's no RAM in that zone, then we avoid allocating resources to bounce 271 * a request, and we can use any memory allocator (as opposed to needing 272 * kmem_alloc_contig() just because it can allocate pages in an address range). 273 * 274 * Most tags have BUS_SPACE_MAXADDR or BUS_SPACE_MAXADDR_32BIT (they are the 275 * same value on 32-bit architectures) as their lowaddr constraint, and we can't 276 * possibly have RAM at an address higher than the highest address we can 277 * express, so we take a fast out. 278 */ 279static int 280exclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr) 281{ 282 int i; 283 284 if (lowaddr >= BUS_SPACE_MAXADDR) 285 return (0); 286 287 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 288 if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) || 289 (lowaddr < phys_avail[i] && highaddr >= phys_avail[i])) 290 return (1); 291 } 292 return (0); 293} 294 295/* 296 * Return true if the tag has an exclusion zone that could lead to bouncing. 297 */ 298static __inline int 299exclusion_bounce(bus_dma_tag_t dmat) 300{ 301 302 return (dmat->flags & BUS_DMA_EXCL_BOUNCE); 303} 304 305/* 306 * Return true if the given address does not fall on the alignment boundary. 307 */ 308static __inline int 309alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr) 310{ 311 312 return (addr & (dmat->alignment - 1)); 313} 314 315/* 316 * Return true if the DMA should bounce because the start or end does not fall 317 * on a cacheline boundary (which would require a partial cacheline flush). 318 * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by 319 * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a 320 * strict rule that such memory cannot be accessed by the CPU while DMA is in 321 * progress (or by multiple DMA engines at once), so that it's always safe to do 322 * full cacheline flushes even if that affects memory outside the range of a 323 * given DMA operation that doesn't involve the full allocated buffer. If we're 324 * mapping an mbuf, that follows the same rules as a buffer we allocated. 325 */ 326static __inline int 327cacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size) 328{ 329 330 if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF)) 331 return (0); 332 return ((addr | size) & arm_dcache_align_mask); 333} 334 335/* 336 * Return true if we might need to bounce the DMA described by addr and size. 337 * 338 * This is used to quick-check whether we need to do the more expensive work of 339 * checking the DMA page-by-page looking for alignment and exclusion bounces. 340 * 341 * Note that the addr argument might be either virtual or physical. It doesn't 342 * matter because we only look at the low-order bits, which are the same in both 343 * address spaces. 344 */ 345static __inline int 346might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr, 347 bus_size_t size) 348{ 349 350 return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) || 351 alignment_bounce(dmat, addr) || 352 cacheline_bounce(map, addr, size)); 353} 354 355/* 356 * Return true if we must bounce the DMA described by paddr and size. 357 * 358 * Bouncing can be triggered by DMA that doesn't begin and end on cacheline 359 * boundaries, or doesn't begin on an alignment boundary, or falls within the 360 * exclusion zone of any tag in the ancestry chain. 361 * 362 * For exclusions, walk the chain of tags comparing paddr to the exclusion zone 363 * within each tag. If the tag has a filter function, use it to decide whether 364 * the DMA needs to bounce, otherwise any DMA within the zone bounces. 365 */ 366static int 367must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, 368 bus_size_t size) 369{ 370 371 if (cacheline_bounce(map, paddr, size)) 372 return (1); 373 374 /* 375 * The tag already contains ancestors' alignment restrictions so this 376 * check doesn't need to be inside the loop. 377 */ 378 if (alignment_bounce(dmat, paddr)) 379 return (1); 380 381 /* 382 * Even though each tag has an exclusion zone that is a superset of its 383 * own and all its ancestors' exclusions, the exclusion zone of each tag 384 * up the chain must be checked within the loop, because the busdma 385 * rules say the filter function is called only when the address lies 386 * within the low-highaddr range of the tag that filterfunc belongs to. 387 */ 388 while (dmat != NULL && exclusion_bounce(dmat)) { 389 if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) && 390 (dmat->filter == NULL || 391 dmat->filter(dmat->filterarg, paddr) != 0)) 392 return (1); 393 dmat = dmat->parent; 394 } 395 396 return (0); 397} 398 399static __inline struct arm32_dma_range * 400_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 401 bus_addr_t curaddr) 402{ 403 struct arm32_dma_range *dr; 404 int i; 405 406 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 407 if (curaddr >= dr->dr_sysbase && 408 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 409 return (dr); 410 } 411 412 return (NULL); 413} 414 415/* 416 * Convenience function for manipulating driver locks from busdma (during 417 * busdma_swi, for example). Drivers that don't provide their own locks 418 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 419 * non-mutex locking scheme don't have to use this at all. 420 */ 421void 422busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 423{ 424 struct mtx *dmtx; 425 426 dmtx = (struct mtx *)arg; 427 switch (op) { 428 case BUS_DMA_LOCK: 429 mtx_lock(dmtx); 430 break; 431 case BUS_DMA_UNLOCK: 432 mtx_unlock(dmtx); 433 break; 434 default: 435 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 436 } 437} 438 439/* 440 * dflt_lock should never get called. It gets put into the dma tag when 441 * lockfunc == NULL, which is only valid if the maps that are associated 442 * with the tag are meant to never be defered. 443 * XXX Should have a way to identify which driver is responsible here. 444 */ 445static void 446dflt_lock(void *arg, bus_dma_lock_op_t op) 447{ 448 449 panic("driver error: busdma dflt_lock called"); 450} 451 452/* 453 * Allocate a device specific dma_tag. 454 */ 455int 456bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 457 bus_size_t boundary, bus_addr_t lowaddr, 458 bus_addr_t highaddr, bus_dma_filter_t *filter, 459 void *filterarg, bus_size_t maxsize, int nsegments, 460 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 461 void *lockfuncarg, bus_dma_tag_t *dmat) 462{ 463 bus_dma_tag_t newtag; 464 int error = 0; 465 466#if 0 467 if (!parent) 468 parent = arm_root_dma_tag; 469#endif 470 471 /* Basic sanity checking. */ 472 KASSERT(boundary == 0 || powerof2(boundary), 473 ("dma tag boundary %lu, must be a power of 2", boundary)); 474 KASSERT(boundary == 0 || boundary >= maxsegsz, 475 ("dma tag boundary %lu is < maxsegsz %lu\n", boundary, maxsegsz)); 476 KASSERT(alignment != 0 && powerof2(alignment), 477 ("dma tag alignment %lu, must be non-zero power of 2", alignment)); 478 KASSERT(maxsegsz != 0, ("dma tag maxsegsz must not be zero")); 479 480 /* Return a NULL tag on failure */ 481 *dmat = NULL; 482 483 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 484 M_ZERO | M_NOWAIT); 485 if (newtag == NULL) { 486 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 487 __func__, newtag, 0, error); 488 return (ENOMEM); 489 } 490 491 newtag->parent = parent; 492 newtag->alignment = alignment; 493 newtag->boundary = boundary; 494 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 495 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 496 (PAGE_SIZE - 1); 497 newtag->filter = filter; 498 newtag->filterarg = filterarg; 499 newtag->maxsize = maxsize; 500 newtag->nsegments = nsegments; 501 newtag->maxsegsz = maxsegsz; 502 newtag->flags = flags; 503 newtag->ref_count = 1; /* Count ourself */ 504 newtag->map_count = 0; 505 newtag->ranges = bus_dma_get_range(); 506 newtag->_nranges = bus_dma_get_range_nb(); 507 if (lockfunc != NULL) { 508 newtag->lockfunc = lockfunc; 509 newtag->lockfuncarg = lockfuncarg; 510 } else { 511 newtag->lockfunc = dflt_lock; 512 newtag->lockfuncarg = NULL; 513 } 514 515 /* Take into account any restrictions imposed by our parent tag */ 516 if (parent != NULL) { 517 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 518 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 519 newtag->alignment = MAX(parent->alignment, newtag->alignment); 520 newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE; 521 if (newtag->boundary == 0) 522 newtag->boundary = parent->boundary; 523 else if (parent->boundary != 0) 524 newtag->boundary = MIN(parent->boundary, 525 newtag->boundary); 526 if (newtag->filter == NULL) { 527 /* 528 * Short circuit to looking at our parent directly 529 * since we have encapsulated all of its information 530 */ 531 newtag->filter = parent->filter; 532 newtag->filterarg = parent->filterarg; 533 newtag->parent = parent->parent; 534 } 535 if (newtag->parent != NULL) 536 atomic_add_int(&parent->ref_count, 1); 537 } 538 539 if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr)) 540 newtag->flags |= BUS_DMA_EXCL_BOUNCE; 541 if (alignment_bounce(newtag, 1)) 542 newtag->flags |= BUS_DMA_ALIGN_BOUNCE; 543 544 /* 545 * Any request can auto-bounce due to cacheline alignment, in addition 546 * to any alignment or boundary specifications in the tag, so if the 547 * ALLOCNOW flag is set, there's always work to do. 548 */ 549 if ((flags & BUS_DMA_ALLOCNOW) != 0) { 550 struct bounce_zone *bz; 551 /* 552 * Round size up to a full page, and add one more page because 553 * there can always be one more boundary crossing than the 554 * number of pages in a transfer. 555 */ 556 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 557 558 if ((error = alloc_bounce_zone(newtag)) != 0) { 559 free(newtag, M_DEVBUF); 560 return (error); 561 } 562 bz = newtag->bounce_zone; 563 564 if (ptoa(bz->total_bpages) < maxsize) { 565 int pages; 566 567 pages = atop(maxsize) - bz->total_bpages; 568 569 /* Add pages to our bounce pool */ 570 if (alloc_bounce_pages(newtag, pages) < pages) 571 error = ENOMEM; 572 } 573 /* Performed initial allocation */ 574 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 575 } else 576 newtag->bounce_zone = NULL; 577 578 if (error != 0) { 579 free(newtag, M_DEVBUF); 580 } else { 581 atomic_add_32(&tags_total, 1); 582 *dmat = newtag; 583 } 584 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 585 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 586 return (error); 587} 588 589int 590bus_dma_tag_destroy(bus_dma_tag_t dmat) 591{ 592 bus_dma_tag_t dmat_copy; 593 int error; 594 595 error = 0; 596 dmat_copy = dmat; 597 598 if (dmat != NULL) { 599 600 if (dmat->map_count != 0) { 601 error = EBUSY; 602 goto out; 603 } 604 605 while (dmat != NULL) { 606 bus_dma_tag_t parent; 607 608 parent = dmat->parent; 609 atomic_subtract_int(&dmat->ref_count, 1); 610 if (dmat->ref_count == 0) { 611 atomic_subtract_32(&tags_total, 1); 612 free(dmat, M_DEVBUF); 613 /* 614 * Last reference count, so 615 * release our reference 616 * count on our parent. 617 */ 618 dmat = parent; 619 } else 620 dmat = NULL; 621 } 622 } 623out: 624 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 625 return (error); 626} 627 628static int 629allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 630{ 631 struct bounce_zone *bz; 632 int maxpages; 633 int error; 634 635 if (dmat->bounce_zone == NULL) 636 if ((error = alloc_bounce_zone(dmat)) != 0) 637 return (error); 638 bz = dmat->bounce_zone; 639 /* Initialize the new map */ 640 STAILQ_INIT(&(mapp->bpages)); 641 642 /* 643 * Attempt to add pages to our pool on a per-instance basis up to a sane 644 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 645 * alignment and boundary constraints, it could still auto-bounce due to 646 * cacheline alignment, which requires at most two bounce pages. 647 */ 648 if (dmat->flags & BUS_DMA_COULD_BOUNCE) 649 maxpages = MAX_BPAGES; 650 else 651 maxpages = 2 * bz->map_count; 652 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 || 653 (bz->map_count > 0 && bz->total_bpages < maxpages)) { 654 int pages; 655 656 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 657 pages = MIN(maxpages - bz->total_bpages, pages); 658 pages = MAX(pages, 2); 659 if (alloc_bounce_pages(dmat, pages) < pages) 660 return (ENOMEM); 661 662 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 663 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 664 } 665 bz->map_count++; 666 return (0); 667} 668 669static bus_dmamap_t 670allocate_map(bus_dma_tag_t dmat, int mflags) 671{ 672 int mapsize, segsize; 673 bus_dmamap_t map; 674 675 /* 676 * Allocate the map. The map structure ends with an embedded 677 * variable-sized array of sync_list structures. Following that 678 * we allocate enough extra space to hold the array of bus_dma_segments. 679 */ 680 KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS, 681 ("cannot allocate %u dma segments (max is %u)", 682 dmat->nsegments, MAX_DMA_SEGMENTS)); 683 segsize = sizeof(struct bus_dma_segment) * dmat->nsegments; 684 mapsize = sizeof(*map) + sizeof(struct sync_list) * dmat->nsegments; 685 map = malloc(mapsize + segsize, M_DEVBUF, mflags | M_ZERO); 686 if (map == NULL) { 687 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 688 return (NULL); 689 } 690 map->segments = (bus_dma_segment_t *)((uintptr_t)map + mapsize); 691 return (map); 692} 693 694/* 695 * Allocate a handle for mapping from kva/uva/physical 696 * address space into bus device space. 697 */ 698int 699bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 700{ 701 bus_dmamap_t map; 702 int error = 0; 703 704 *mapp = map = allocate_map(dmat, M_NOWAIT); 705 if (map == NULL) { 706 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 707 return (ENOMEM); 708 } 709 710 /* 711 * Bouncing might be required if the driver asks for an exclusion 712 * region, a data alignment that is stricter than 1, or DMA that begins 713 * or ends with a partial cacheline. Whether bouncing will actually 714 * happen can't be known until mapping time, but we need to pre-allocate 715 * resources now because we might not be allowed to at mapping time. 716 */ 717 error = allocate_bz_and_pages(dmat, map); 718 if (error != 0) { 719 free(map, M_DEVBUF); 720 *mapp = NULL; 721 return (error); 722 } 723 if (map->flags & DMAMAP_COHERENT) 724 atomic_add_32(&maps_coherent, 1); 725 atomic_add_32(&maps_total, 1); 726 dmat->map_count++; 727 728 return (0); 729} 730 731/* 732 * Destroy a handle for mapping from kva/uva/physical 733 * address space into bus device space. 734 */ 735int 736bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 737{ 738 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 739 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 740 __func__, dmat, EBUSY); 741 return (EBUSY); 742 } 743 if (dmat->bounce_zone) 744 dmat->bounce_zone->map_count--; 745 if (map->flags & DMAMAP_COHERENT) 746 atomic_subtract_32(&maps_coherent, 1); 747 atomic_subtract_32(&maps_total, 1); 748 free(map, M_DEVBUF); 749 dmat->map_count--; 750 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 751 return (0); 752} 753 754 755/* 756 * Allocate a piece of memory that can be efficiently mapped into 757 * bus device space based on the constraints lited in the dma tag. 758 * A dmamap to for use with dmamap_load is also allocated. 759 */ 760int 761bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 762 bus_dmamap_t *mapp) 763{ 764 busdma_bufalloc_t ba; 765 struct busdma_bufzone *bufzone; 766 bus_dmamap_t map; 767 vm_memattr_t memattr; 768 int mflags; 769 770 if (flags & BUS_DMA_NOWAIT) 771 mflags = M_NOWAIT; 772 else 773 mflags = M_WAITOK; 774 if (flags & BUS_DMA_ZERO) 775 mflags |= M_ZERO; 776 777 *mapp = map = allocate_map(dmat, mflags); 778 if (map == NULL) { 779 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 780 __func__, dmat, dmat->flags, ENOMEM); 781 return (ENOMEM); 782 } 783 map->flags = DMAMAP_DMAMEM_ALLOC; 784 785 /* Choose a busdma buffer allocator based on memory type flags. */ 786 if (flags & BUS_DMA_COHERENT) { 787 memattr = VM_MEMATTR_UNCACHEABLE; 788 ba = coherent_allocator; 789 map->flags |= DMAMAP_COHERENT; 790 } else { 791 memattr = VM_MEMATTR_DEFAULT; 792 ba = standard_allocator; 793 } 794 795 /* 796 * Try to find a bufzone in the allocator that holds a cache of buffers 797 * of the right size for this request. If the buffer is too big to be 798 * held in the allocator cache, this returns NULL. 799 */ 800 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 801 802 /* 803 * Allocate the buffer from the uma(9) allocator if... 804 * - It's small enough to be in the allocator (bufzone not NULL). 805 * - The alignment constraint isn't larger than the allocation size 806 * (the allocator aligns buffers to their size boundaries). 807 * - There's no need to handle lowaddr/highaddr exclusion zones. 808 * else allocate non-contiguous pages if... 809 * - The page count that could get allocated doesn't exceed nsegments. 810 * - The alignment constraint isn't larger than a page boundary. 811 * - There are no boundary-crossing constraints. 812 * else allocate a block of contiguous pages because one or more of the 813 * constraints is something that only the contig allocator can fulfill. 814 */ 815 if (bufzone != NULL && dmat->alignment <= bufzone->size && 816 !exclusion_bounce(dmat)) { 817 *vaddr = uma_zalloc(bufzone->umazone, mflags); 818 } else if (dmat->nsegments >= btoc(dmat->maxsize) && 819 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 820 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 821 mflags, 0, dmat->lowaddr, memattr); 822 } else { 823 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 824 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 825 memattr); 826 } 827 828 829 if (*vaddr == NULL) { 830 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 831 __func__, dmat, dmat->flags, ENOMEM); 832 free(map, M_DEVBUF); 833 *mapp = NULL; 834 return (ENOMEM); 835 } 836 if (map->flags & DMAMAP_COHERENT) 837 atomic_add_32(&maps_coherent, 1); 838 atomic_add_32(&maps_dmamem, 1); 839 atomic_add_32(&maps_total, 1); 840 dmat->map_count++; 841 842 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 843 __func__, dmat, dmat->flags, 0); 844 return (0); 845} 846 847/* 848 * Free a piece of memory and it's allociated dmamap, that was allocated 849 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 850 */ 851void 852bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 853{ 854 struct busdma_bufzone *bufzone; 855 busdma_bufalloc_t ba; 856 857 if (map->flags & DMAMAP_COHERENT) 858 ba = coherent_allocator; 859 else 860 ba = standard_allocator; 861 862 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 863 864 if (bufzone != NULL && dmat->alignment <= bufzone->size && 865 !exclusion_bounce(dmat)) 866 uma_zfree(bufzone->umazone, vaddr); 867 else 868 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 869 870 dmat->map_count--; 871 if (map->flags & DMAMAP_COHERENT) 872 atomic_subtract_32(&maps_coherent, 1); 873 atomic_subtract_32(&maps_total, 1); 874 atomic_subtract_32(&maps_dmamem, 1); 875 free(map, M_DEVBUF); 876 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 877} 878 879static void 880_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 881 bus_size_t buflen, int flags) 882{ 883 bus_addr_t curaddr; 884 bus_size_t sgsize; 885 886 if (map->pagesneeded == 0) { 887 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 888 " map= %p, pagesneeded= %d", 889 dmat->lowaddr, dmat->boundary, dmat->alignment, 890 map, map->pagesneeded); 891 /* 892 * Count the number of bounce pages 893 * needed in order to complete this transfer 894 */ 895 curaddr = buf; 896 while (buflen != 0) { 897 sgsize = MIN(buflen, dmat->maxsegsz); 898 if (must_bounce(dmat, map, curaddr, sgsize) != 0) { 899 sgsize = MIN(sgsize, PAGE_SIZE); 900 map->pagesneeded++; 901 } 902 curaddr += sgsize; 903 buflen -= sgsize; 904 } 905 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 906 } 907} 908 909static void 910_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 911 void *buf, bus_size_t buflen, int flags) 912{ 913 vm_offset_t vaddr; 914 vm_offset_t vendaddr; 915 bus_addr_t paddr; 916 917 if (map->pagesneeded == 0) { 918 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 919 " map= %p, pagesneeded= %d", 920 dmat->lowaddr, dmat->boundary, dmat->alignment, 921 map, map->pagesneeded); 922 /* 923 * Count the number of bounce pages 924 * needed in order to complete this transfer 925 */ 926 vaddr = (vm_offset_t)buf; 927 vendaddr = (vm_offset_t)buf + buflen; 928 929 while (vaddr < vendaddr) { 930 if (__predict_true(map->pmap == kernel_pmap)) 931 paddr = pmap_kextract(vaddr); 932 else 933 paddr = pmap_extract(map->pmap, vaddr); 934 if (must_bounce(dmat, map, paddr, 935 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr & 936 PAGE_MASK)))) != 0) { 937 map->pagesneeded++; 938 } 939 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 940 941 } 942 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 943 } 944} 945 946static int 947_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 948{ 949 950 /* Reserve Necessary Bounce Pages */ 951 mtx_lock(&bounce_lock); 952 if (flags & BUS_DMA_NOWAIT) { 953 if (reserve_bounce_pages(dmat, map, 0) != 0) { 954 map->pagesneeded = 0; 955 mtx_unlock(&bounce_lock); 956 return (ENOMEM); 957 } 958 } else { 959 if (reserve_bounce_pages(dmat, map, 1) != 0) { 960 /* Queue us for resources */ 961 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 962 mtx_unlock(&bounce_lock); 963 return (EINPROGRESS); 964 } 965 } 966 mtx_unlock(&bounce_lock); 967 968 return (0); 969} 970 971/* 972 * Add a single contiguous physical range to the segment list. 973 */ 974static int 975_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 976 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 977{ 978 bus_addr_t baddr, bmask; 979 int seg; 980 981 /* 982 * Make sure we don't cross any boundaries. 983 */ 984 bmask = ~(dmat->boundary - 1); 985 if (dmat->boundary > 0) { 986 baddr = (curaddr + dmat->boundary) & bmask; 987 if (sgsize > (baddr - curaddr)) 988 sgsize = (baddr - curaddr); 989 } 990 991 if (dmat->ranges) { 992 struct arm32_dma_range *dr; 993 994 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 995 curaddr); 996 if (dr == NULL) { 997 _bus_dmamap_unload(dmat, map); 998 return (0); 999 } 1000 /* 1001 * In a valid DMA range. Translate the physical 1002 * memory address to an address in the DMA window. 1003 */ 1004 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 1005 } 1006 1007 /* 1008 * Insert chunk into a segment, coalescing with 1009 * previous segment if possible. 1010 */ 1011 seg = *segp; 1012 if (seg == -1) { 1013 seg = 0; 1014 segs[seg].ds_addr = curaddr; 1015 segs[seg].ds_len = sgsize; 1016 } else { 1017 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 1018 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 1019 (dmat->boundary == 0 || 1020 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 1021 segs[seg].ds_len += sgsize; 1022 else { 1023 if (++seg >= dmat->nsegments) 1024 return (0); 1025 segs[seg].ds_addr = curaddr; 1026 segs[seg].ds_len = sgsize; 1027 } 1028 } 1029 *segp = seg; 1030 return (sgsize); 1031} 1032 1033/* 1034 * Utility function to load a physical buffer. segp contains 1035 * the starting segment on entrace, and the ending segment on exit. 1036 */ 1037int 1038_bus_dmamap_load_phys(bus_dma_tag_t dmat, 1039 bus_dmamap_t map, 1040 vm_paddr_t buf, bus_size_t buflen, 1041 int flags, 1042 bus_dma_segment_t *segs, 1043 int *segp) 1044{ 1045 bus_addr_t curaddr; 1046 bus_size_t sgsize; 1047 int error; 1048 1049 if (segs == NULL) 1050 segs = map->segments; 1051 1052 counter_u64_add(maploads_total, 1); 1053 counter_u64_add(maploads_physmem, 1); 1054 1055 if (might_bounce(dmat, map, buflen, buflen)) { 1056 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 1057 if (map->pagesneeded != 0) { 1058 counter_u64_add(maploads_bounced, 1); 1059 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1060 if (error) 1061 return (error); 1062 } 1063 } 1064 1065 while (buflen > 0) { 1066 curaddr = buf; 1067 sgsize = MIN(buflen, dmat->maxsegsz); 1068 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1069 sgsize)) { 1070 sgsize = MIN(sgsize, PAGE_SIZE); 1071 curaddr = add_bounce_page(dmat, map, 0, curaddr, 1072 sgsize); 1073 } 1074 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1075 segp); 1076 if (sgsize == 0) 1077 break; 1078 buf += sgsize; 1079 buflen -= sgsize; 1080 } 1081 1082 /* 1083 * Did we fit? 1084 */ 1085 if (buflen != 0) { 1086 _bus_dmamap_unload(dmat, map); 1087 return (EFBIG); /* XXX better return value here? */ 1088 } 1089 return (0); 1090} 1091 1092int 1093_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 1094 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 1095 bus_dma_segment_t *segs, int *segp) 1096{ 1097 1098 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 1099 segs, segp)); 1100} 1101 1102/* 1103 * Utility function to load a linear buffer. segp contains 1104 * the starting segment on entrace, and the ending segment on exit. 1105 */ 1106int 1107_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1108 bus_dmamap_t map, 1109 void *buf, bus_size_t buflen, 1110 pmap_t pmap, 1111 int flags, 1112 bus_dma_segment_t *segs, 1113 int *segp) 1114{ 1115 bus_size_t sgsize; 1116 bus_addr_t curaddr; 1117 vm_offset_t vaddr; 1118 struct sync_list *sl; 1119 int error; 1120 1121 counter_u64_add(maploads_total, 1); 1122 if (map->flags & DMAMAP_COHERENT) 1123 counter_u64_add(maploads_coherent, 1); 1124 if (map->flags & DMAMAP_DMAMEM_ALLOC) 1125 counter_u64_add(maploads_dmamem, 1); 1126 1127 if (segs == NULL) 1128 segs = map->segments; 1129 1130 if (flags & BUS_DMA_LOAD_MBUF) { 1131 counter_u64_add(maploads_mbuf, 1); 1132 map->flags |= DMAMAP_MBUF; 1133 } 1134 1135 map->pmap = pmap; 1136 1137 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) { 1138 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1139 if (map->pagesneeded != 0) { 1140 counter_u64_add(maploads_bounced, 1); 1141 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1142 if (error) 1143 return (error); 1144 } 1145 } 1146 1147 sl = NULL; 1148 vaddr = (vm_offset_t)buf; 1149 1150 while (buflen > 0) { 1151 /* 1152 * Get the physical address for this segment. 1153 */ 1154 if (__predict_true(map->pmap == kernel_pmap)) 1155 curaddr = pmap_kextract(vaddr); 1156 else 1157 curaddr = pmap_extract(map->pmap, vaddr); 1158 1159 /* 1160 * Compute the segment size, and adjust counts. 1161 */ 1162 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1163 if (sgsize > dmat->maxsegsz) 1164 sgsize = dmat->maxsegsz; 1165 if (buflen < sgsize) 1166 sgsize = buflen; 1167 1168 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1169 sgsize)) { 1170 curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1171 sgsize); 1172 } else { 1173 sl = &map->slist[map->sync_count - 1]; 1174 if (map->sync_count == 0 || 1175#ifdef ARM_L2_PIPT 1176 curaddr != sl->busaddr + sl->datacount || 1177#endif 1178 vaddr != sl->vaddr + sl->datacount) { 1179 if (++map->sync_count > dmat->nsegments) 1180 goto cleanup; 1181 sl++; 1182 sl->vaddr = vaddr; 1183 sl->datacount = sgsize; 1184 sl->busaddr = curaddr; 1185 } else 1186 sl->datacount += sgsize; 1187 } 1188 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1189 segp); 1190 if (sgsize == 0) 1191 break; 1192 vaddr += sgsize; 1193 buflen -= sgsize; 1194 } 1195 1196cleanup: 1197 /* 1198 * Did we fit? 1199 */ 1200 if (buflen != 0) { 1201 _bus_dmamap_unload(dmat, map); 1202 return (EFBIG); /* XXX better return value here? */ 1203 } 1204 return (0); 1205} 1206 1207 1208void 1209__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1210 struct memdesc *mem, bus_dmamap_callback_t *callback, 1211 void *callback_arg) 1212{ 1213 1214 map->mem = *mem; 1215 map->dmat = dmat; 1216 map->callback = callback; 1217 map->callback_arg = callback_arg; 1218} 1219 1220bus_dma_segment_t * 1221_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1222 bus_dma_segment_t *segs, int nsegs, int error) 1223{ 1224 1225 if (segs == NULL) 1226 segs = map->segments; 1227 return (segs); 1228} 1229 1230/* 1231 * Release the mapping held by map. 1232 */ 1233void 1234_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1235{ 1236 struct bounce_page *bpage; 1237 struct bounce_zone *bz; 1238 1239 if ((bz = dmat->bounce_zone) != NULL) { 1240 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1241 STAILQ_REMOVE_HEAD(&map->bpages, links); 1242 free_bounce_page(dmat, bpage); 1243 } 1244 1245 bz = dmat->bounce_zone; 1246 bz->free_bpages += map->pagesreserved; 1247 bz->reserved_bpages -= map->pagesreserved; 1248 map->pagesreserved = 0; 1249 map->pagesneeded = 0; 1250 } 1251 map->sync_count = 0; 1252 map->flags &= ~DMAMAP_MBUF; 1253} 1254 1255#ifdef notyetbounceuser 1256/* If busdma uses user pages, then the interrupt handler could 1257 * be use the kernel vm mapping. Both bounce pages and sync list 1258 * do not cross page boundaries. 1259 * Below is a rough sequence that a person would do to fix the 1260 * user page reference in the kernel vmspace. This would be 1261 * done in the dma post routine. 1262 */ 1263void 1264_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1265 pmap_t pmap, int op) 1266{ 1267 bus_size_t sgsize; 1268 bus_addr_t curaddr; 1269 vm_offset_t va; 1270 1271 /* 1272 * each synclist entry is contained within a single page. 1273 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1274 */ 1275 curaddr = pmap_extract(pmap, buf); 1276 va = pmap_dma_map(curaddr); 1277 switch (op) { 1278 case SYNC_USER_INV: 1279 cpu_dcache_wb_range(va, sgsize); 1280 break; 1281 1282 case SYNC_USER_COPYTO: 1283 bcopy((void *)va, (void *)bounce, sgsize); 1284 break; 1285 1286 case SYNC_USER_COPYFROM: 1287 bcopy((void *) bounce, (void *)va, sgsize); 1288 break; 1289 1290 default: 1291 break; 1292 } 1293 1294 pmap_dma_unmap(va); 1295} 1296#endif 1297 1298#ifdef ARM_L2_PIPT 1299#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1300#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1301#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1302#else 1303#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1304#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1305#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1306#endif 1307 1308void 1309_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1310{ 1311 struct bounce_page *bpage; 1312 struct sync_list *sl, *end; 1313 /* 1314 * If the buffer was from user space, it is possible that this is not 1315 * the same vm map, especially on a POST operation. It's not clear that 1316 * dma on userland buffers can work at all right now. To be safe, until 1317 * we're able to test direct userland dma, panic on a map mismatch. 1318 */ 1319 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1320 if (!pmap_dmap_iscurrent(map->pmap)) 1321 panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1322 1323 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1324 "performing bounce", __func__, dmat, dmat->flags, op); 1325 1326 /* 1327 * For PREWRITE do a writeback. Clean the caches from the 1328 * innermost to the outermost levels. 1329 */ 1330 if (op & BUS_DMASYNC_PREWRITE) { 1331 while (bpage != NULL) { 1332 if (bpage->datavaddr != 0) 1333 bcopy((void *)bpage->datavaddr, 1334 (void *)bpage->vaddr, 1335 bpage->datacount); 1336 else 1337 physcopyout(bpage->dataaddr, 1338 (void *)bpage->vaddr, 1339 bpage->datacount); 1340 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1341 bpage->datacount); 1342 l2cache_wb_range((vm_offset_t)bpage->vaddr, 1343 (vm_offset_t)bpage->busaddr, 1344 bpage->datacount); 1345 bpage = STAILQ_NEXT(bpage, links); 1346 } 1347 dmat->bounce_zone->total_bounced++; 1348 } 1349 1350 /* 1351 * Do an invalidate for PREREAD unless a writeback was already 1352 * done above due to PREWRITE also being set. The reason for a 1353 * PREREAD invalidate is to prevent dirty lines currently in the 1354 * cache from being evicted during the DMA. If a writeback was 1355 * done due to PREWRITE also being set there will be no dirty 1356 * lines and the POSTREAD invalidate handles the rest. The 1357 * invalidate is done from the innermost to outermost level. If 1358 * L2 were done first, a dirty cacheline could be automatically 1359 * evicted from L1 before we invalidated it, re-dirtying the L2. 1360 */ 1361 if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) { 1362 bpage = STAILQ_FIRST(&map->bpages); 1363 while (bpage != NULL) { 1364 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1365 bpage->datacount); 1366 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1367 (vm_offset_t)bpage->busaddr, 1368 bpage->datacount); 1369 bpage = STAILQ_NEXT(bpage, links); 1370 } 1371 } 1372 1373 /* 1374 * Re-invalidate the caches on a POSTREAD, even though they were 1375 * already invalidated at PREREAD time. Aggressive prefetching 1376 * due to accesses to other data near the dma buffer could have 1377 * brought buffer data into the caches which is now stale. The 1378 * caches are invalidated from the outermost to innermost; the 1379 * prefetches could be happening right now, and if L1 were 1380 * invalidated first, stale L2 data could be prefetched into L1. 1381 */ 1382 if (op & BUS_DMASYNC_POSTREAD) { 1383 while (bpage != NULL) { 1384 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1385 (vm_offset_t)bpage->busaddr, 1386 bpage->datacount); 1387 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1388 bpage->datacount); 1389 if (bpage->datavaddr != 0) 1390 bcopy((void *)bpage->vaddr, 1391 (void *)bpage->datavaddr, 1392 bpage->datacount); 1393 else 1394 physcopyin((void *)bpage->vaddr, 1395 bpage->dataaddr, 1396 bpage->datacount); 1397 bpage = STAILQ_NEXT(bpage, links); 1398 } 1399 dmat->bounce_zone->total_bounced++; 1400 } 1401 } 1402 1403 /* 1404 * For COHERENT memory no cache maintenance is necessary, but ensure all 1405 * writes have reached memory for the PREWRITE case. No action is 1406 * needed for a PREREAD without PREWRITE also set, because that would 1407 * imply that the cpu had written to the COHERENT buffer and expected 1408 * the dma device to see that change, and by definition a PREWRITE sync 1409 * is required to make that happen. 1410 */ 1411 if (map->flags & DMAMAP_COHERENT) { 1412 if (op & BUS_DMASYNC_PREWRITE) { 1413 dsb(); 1414 cpu_l2cache_drain_writebuf(); 1415 } 1416 return; 1417 } 1418 1419 /* 1420 * Cache maintenance for normal (non-COHERENT non-bounce) buffers. All 1421 * the comments about the sequences for flushing cache levels in the 1422 * bounce buffer code above apply here as well. In particular, the fact 1423 * that the sequence is inner-to-outer for PREREAD invalidation and 1424 * outer-to-inner for POSTREAD invalidation is not a mistake. 1425 */ 1426 if (map->sync_count != 0) { 1427 if (!pmap_dmap_iscurrent(map->pmap)) 1428 panic("_bus_dmamap_sync: wrong user map for sync."); 1429 1430 sl = &map->slist[0]; 1431 end = &map->slist[map->sync_count]; 1432 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1433 "performing sync", __func__, dmat, dmat->flags, op); 1434 1435 switch (op) { 1436 case BUS_DMASYNC_PREWRITE: 1437 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1438 while (sl != end) { 1439 cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1440 l2cache_wb_range(sl->vaddr, sl->busaddr, 1441 sl->datacount); 1442 sl++; 1443 } 1444 break; 1445 1446 case BUS_DMASYNC_PREREAD: 1447 /* 1448 * An mbuf may start in the middle of a cacheline. There 1449 * will be no cpu writes to the beginning of that line 1450 * (which contains the mbuf header) while dma is in 1451 * progress. Handle that case by doing a writeback of 1452 * just the first cacheline before invalidating the 1453 * overall buffer. Any mbuf in a chain may have this 1454 * misalignment. Buffers which are not mbufs bounce if 1455 * they are not aligned to a cacheline. 1456 */ 1457 while (sl != end) { 1458 if (sl->vaddr & arm_dcache_align_mask) { 1459 KASSERT(map->flags & DMAMAP_MBUF, 1460 ("unaligned buffer is not an mbuf")); 1461 cpu_dcache_wb_range(sl->vaddr, 1); 1462 l2cache_wb_range(sl->vaddr, 1463 sl->busaddr, 1); 1464 } 1465 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1466 l2cache_inv_range(sl->vaddr, sl->busaddr, 1467 sl->datacount); 1468 sl++; 1469 } 1470 break; 1471 1472 case BUS_DMASYNC_POSTWRITE: 1473 break; 1474 1475 case BUS_DMASYNC_POSTREAD: 1476 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1477 while (sl != end) { 1478 l2cache_inv_range(sl->vaddr, sl->busaddr, 1479 sl->datacount); 1480 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1481 sl++; 1482 } 1483 break; 1484 1485 default: 1486 panic("unsupported combination of sync operations: 0x%08x\n", op); 1487 break; 1488 } 1489 } 1490} 1491 1492static void 1493init_bounce_pages(void *dummy __unused) 1494{ 1495 1496 total_bpages = 0; 1497 STAILQ_INIT(&bounce_zone_list); 1498 STAILQ_INIT(&bounce_map_waitinglist); 1499 STAILQ_INIT(&bounce_map_callbacklist); 1500 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1501} 1502SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1503 1504static struct sysctl_ctx_list * 1505busdma_sysctl_tree(struct bounce_zone *bz) 1506{ 1507 1508 return (&bz->sysctl_tree); 1509} 1510 1511static struct sysctl_oid * 1512busdma_sysctl_tree_top(struct bounce_zone *bz) 1513{ 1514 1515 return (bz->sysctl_tree_top); 1516} 1517 1518static int 1519alloc_bounce_zone(bus_dma_tag_t dmat) 1520{ 1521 struct bounce_zone *bz; 1522 1523 /* Check to see if we already have a suitable zone */ 1524 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1525 if ((dmat->alignment <= bz->alignment) && 1526 (dmat->lowaddr >= bz->lowaddr)) { 1527 dmat->bounce_zone = bz; 1528 return (0); 1529 } 1530 } 1531 1532 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1533 M_NOWAIT | M_ZERO)) == NULL) 1534 return (ENOMEM); 1535 1536 STAILQ_INIT(&bz->bounce_page_list); 1537 bz->free_bpages = 0; 1538 bz->reserved_bpages = 0; 1539 bz->active_bpages = 0; 1540 bz->lowaddr = dmat->lowaddr; 1541 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1542 bz->map_count = 0; 1543 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1544 busdma_zonecount++; 1545 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1546 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1547 dmat->bounce_zone = bz; 1548 1549 sysctl_ctx_init(&bz->sysctl_tree); 1550 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1551 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1552 CTLFLAG_RD, 0, ""); 1553 if (bz->sysctl_tree_top == NULL) { 1554 sysctl_ctx_free(&bz->sysctl_tree); 1555 return (0); /* XXX error code? */ 1556 } 1557 1558 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1559 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1560 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1561 "Total bounce pages"); 1562 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1563 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1564 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1565 "Free bounce pages"); 1566 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1567 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1568 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1569 "Reserved bounce pages"); 1570 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1571 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1572 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1573 "Active bounce pages"); 1574 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1575 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1576 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1577 "Total bounce requests (pages bounced)"); 1578 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1579 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1580 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1581 "Total bounce requests that were deferred"); 1582 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1583 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1584 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1585 SYSCTL_ADD_ULONG(busdma_sysctl_tree(bz), 1586 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1587 "alignment", CTLFLAG_RD, &bz->alignment, ""); 1588 1589 return (0); 1590} 1591 1592static int 1593alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1594{ 1595 struct bounce_zone *bz; 1596 int count; 1597 1598 bz = dmat->bounce_zone; 1599 count = 0; 1600 while (numpages > 0) { 1601 struct bounce_page *bpage; 1602 1603 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1604 M_NOWAIT | M_ZERO); 1605 1606 if (bpage == NULL) 1607 break; 1608 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1609 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0); 1610 if (bpage->vaddr == 0) { 1611 free(bpage, M_DEVBUF); 1612 break; 1613 } 1614 bpage->busaddr = pmap_kextract(bpage->vaddr); 1615 mtx_lock(&bounce_lock); 1616 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1617 total_bpages++; 1618 bz->total_bpages++; 1619 bz->free_bpages++; 1620 mtx_unlock(&bounce_lock); 1621 count++; 1622 numpages--; 1623 } 1624 return (count); 1625} 1626 1627static int 1628reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1629{ 1630 struct bounce_zone *bz; 1631 int pages; 1632 1633 mtx_assert(&bounce_lock, MA_OWNED); 1634 bz = dmat->bounce_zone; 1635 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1636 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1637 return (map->pagesneeded - (map->pagesreserved + pages)); 1638 bz->free_bpages -= pages; 1639 bz->reserved_bpages += pages; 1640 map->pagesreserved += pages; 1641 pages = map->pagesneeded - map->pagesreserved; 1642 1643 return (pages); 1644} 1645 1646static bus_addr_t 1647add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1648 bus_addr_t addr, bus_size_t size) 1649{ 1650 struct bounce_zone *bz; 1651 struct bounce_page *bpage; 1652 1653 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1654 KASSERT(map != NULL, 1655 ("add_bounce_page: bad map %p", map)); 1656 1657 bz = dmat->bounce_zone; 1658 if (map->pagesneeded == 0) 1659 panic("add_bounce_page: map doesn't need any pages"); 1660 map->pagesneeded--; 1661 1662 if (map->pagesreserved == 0) 1663 panic("add_bounce_page: map doesn't need any pages"); 1664 map->pagesreserved--; 1665 1666 mtx_lock(&bounce_lock); 1667 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1668 if (bpage == NULL) 1669 panic("add_bounce_page: free page list is empty"); 1670 1671 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1672 bz->reserved_bpages--; 1673 bz->active_bpages++; 1674 mtx_unlock(&bounce_lock); 1675 1676 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1677 /* Page offset needs to be preserved. */ 1678 bpage->vaddr |= addr & PAGE_MASK; 1679 bpage->busaddr |= addr & PAGE_MASK; 1680 } 1681 bpage->datavaddr = vaddr; 1682 bpage->dataaddr = addr; 1683 bpage->datacount = size; 1684 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1685 return (bpage->busaddr); 1686} 1687 1688static void 1689free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1690{ 1691 struct bus_dmamap *map; 1692 struct bounce_zone *bz; 1693 1694 bz = dmat->bounce_zone; 1695 bpage->datavaddr = 0; 1696 bpage->datacount = 0; 1697 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1698 /* 1699 * Reset the bounce page to start at offset 0. Other uses 1700 * of this bounce page may need to store a full page of 1701 * data and/or assume it starts on a page boundary. 1702 */ 1703 bpage->vaddr &= ~PAGE_MASK; 1704 bpage->busaddr &= ~PAGE_MASK; 1705 } 1706 1707 mtx_lock(&bounce_lock); 1708 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1709 bz->free_bpages++; 1710 bz->active_bpages--; 1711 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1712 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1713 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1714 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1715 map, links); 1716 busdma_swi_pending = 1; 1717 bz->total_deferred++; 1718 swi_sched(vm_ih, 0); 1719 } 1720 } 1721 mtx_unlock(&bounce_lock); 1722} 1723 1724void 1725busdma_swi(void) 1726{ 1727 bus_dma_tag_t dmat; 1728 struct bus_dmamap *map; 1729 1730 mtx_lock(&bounce_lock); 1731 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1732 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1733 mtx_unlock(&bounce_lock); 1734 dmat = map->dmat; 1735 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK); 1736 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1737 map->callback_arg, BUS_DMA_WAITOK); 1738 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1739 mtx_lock(&bounce_lock); 1740 } 1741 mtx_unlock(&bounce_lock); 1742} 1743