busdma_machdep-v6.c revision 274602
1/*- 2 * Copyright (c) 2012-2014 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 274602 2014-11-16 20:55:51Z ian $"); 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43#include <sys/bus.h> 44#include <sys/busdma_bufalloc.h> 45#include <sys/counter.h> 46#include <sys/interrupt.h> 47#include <sys/kernel.h> 48#include <sys/ktr.h> 49#include <sys/lock.h> 50#include <sys/memdesc.h> 51#include <sys/proc.h> 52#include <sys/mutex.h> 53#include <sys/sysctl.h> 54#include <sys/uio.h> 55 56#include <vm/vm.h> 57#include <vm/vm_page.h> 58#include <vm/vm_map.h> 59#include <vm/vm_extern.h> 60#include <vm/vm_kern.h> 61 62#include <machine/atomic.h> 63#include <machine/bus.h> 64#include <machine/cpufunc.h> 65#include <machine/md_var.h> 66 67#define MAX_BPAGES 64 68#define MAX_DMA_SEGMENTS 4096 69#define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2 70#define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3 71#define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE) 72#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 73 74struct bounce_zone; 75 76struct bus_dma_tag { 77 bus_dma_tag_t parent; 78 bus_size_t alignment; 79 bus_size_t boundary; 80 bus_addr_t lowaddr; 81 bus_addr_t highaddr; 82 bus_dma_filter_t *filter; 83 void *filterarg; 84 bus_size_t maxsize; 85 u_int nsegments; 86 bus_size_t maxsegsz; 87 int flags; 88 int ref_count; 89 int map_count; 90 bus_dma_lock_t *lockfunc; 91 void *lockfuncarg; 92 struct bounce_zone *bounce_zone; 93 /* 94 * DMA range for this tag. If the page doesn't fall within 95 * one of these ranges, an error is returned. The caller 96 * may then decide what to do with the transfer. If the 97 * range pointer is NULL, it is ignored. 98 */ 99 struct arm32_dma_range *ranges; 100 int _nranges; 101}; 102 103struct bounce_page { 104 vm_offset_t vaddr; /* kva of bounce buffer */ 105 bus_addr_t busaddr; /* Physical address */ 106 vm_offset_t datavaddr; /* kva of client data */ 107 bus_addr_t dataaddr; /* client physical address */ 108 bus_size_t datacount; /* client data count */ 109 STAILQ_ENTRY(bounce_page) links; 110}; 111 112struct sync_list { 113 vm_offset_t vaddr; /* kva of bounce buffer */ 114 bus_addr_t busaddr; /* Physical address */ 115 bus_size_t datacount; /* client data count */ 116}; 117 118int busdma_swi_pending; 119 120struct bounce_zone { 121 STAILQ_ENTRY(bounce_zone) links; 122 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 123 int total_bpages; 124 int free_bpages; 125 int reserved_bpages; 126 int active_bpages; 127 int total_bounced; 128 int total_deferred; 129 int map_count; 130 bus_size_t alignment; 131 bus_addr_t lowaddr; 132 char zoneid[8]; 133 char lowaddrid[20]; 134 struct sysctl_ctx_list sysctl_tree; 135 struct sysctl_oid *sysctl_tree_top; 136}; 137 138static struct mtx bounce_lock; 139static int total_bpages; 140static int busdma_zonecount; 141static uint32_t tags_total; 142static uint32_t maps_total; 143static uint32_t maps_dmamem; 144static uint32_t maps_coherent; 145static counter_u64_t maploads_total; 146static counter_u64_t maploads_bounced; 147static counter_u64_t maploads_coherent; 148static counter_u64_t maploads_dmamem; 149static counter_u64_t maploads_mbuf; 150static counter_u64_t maploads_physmem; 151 152static STAILQ_HEAD(, bounce_zone) bounce_zone_list; 153 154SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 155SYSCTL_UINT(_hw_busdma, OID_AUTO, tags_total, CTLFLAG_RD, &tags_total, 0, 156 "Number of active tags"); 157SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_total, CTLFLAG_RD, &maps_total, 0, 158 "Number of active maps"); 159SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_dmamem, CTLFLAG_RD, &maps_dmamem, 0, 160 "Number of active maps for bus_dmamem_alloc buffers"); 161SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0, 162 "Number of active maps with BUS_DMA_COHERENT flag set"); 163SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, 164 &maploads_total, "Number of load operations performed"); 165SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD, 166 &maploads_bounced, "Number of load operations that used bounce buffers"); 167SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_coherent, CTLFLAG_RD, 168 &maploads_dmamem, "Number of load operations on BUS_DMA_COHERENT memory"); 169SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_dmamem, CTLFLAG_RD, 170 &maploads_dmamem, "Number of load operations on bus_dmamem_alloc buffers"); 171SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_mbuf, CTLFLAG_RD, 172 &maploads_mbuf, "Number of load operations for mbufs"); 173SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_physmem, CTLFLAG_RD, 174 &maploads_physmem, "Number of load operations on physical buffers"); 175SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 176 "Total bounce pages"); 177 178struct bus_dmamap { 179 struct bp_list bpages; 180 int pagesneeded; 181 int pagesreserved; 182 bus_dma_tag_t dmat; 183 struct memdesc mem; 184 pmap_t pmap; 185 bus_dmamap_callback_t *callback; 186 void *callback_arg; 187 int flags; 188#define DMAMAP_COHERENT (1 << 0) 189#define DMAMAP_DMAMEM_ALLOC (1 << 1) 190#define DMAMAP_MBUF (1 << 2) 191 STAILQ_ENTRY(bus_dmamap) links; 192 bus_dma_segment_t *segments; 193 int sync_count; 194 struct sync_list slist[]; 195}; 196 197static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 198static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 199 200static void init_bounce_pages(void *dummy); 201static int alloc_bounce_zone(bus_dma_tag_t dmat); 202static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 203static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 204 int commit); 205static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 206 vm_offset_t vaddr, bus_addr_t addr, 207 bus_size_t size); 208static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 209static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 210 void *buf, bus_size_t buflen, int flags); 211static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 212 vm_paddr_t buf, bus_size_t buflen, int flags); 213static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 214 int flags); 215 216static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 217static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 218static void 219busdma_init(void *dummy) 220{ 221 int uma_flags; 222 223 maploads_total = counter_u64_alloc(M_WAITOK); 224 maploads_bounced = counter_u64_alloc(M_WAITOK); 225 maploads_coherent = counter_u64_alloc(M_WAITOK); 226 maploads_dmamem = counter_u64_alloc(M_WAITOK); 227 maploads_mbuf = counter_u64_alloc(M_WAITOK); 228 maploads_physmem = counter_u64_alloc(M_WAITOK); 229 230 uma_flags = 0; 231 232 /* Create a cache of buffers in standard (cacheable) memory. */ 233 standard_allocator = busdma_bufalloc_create("buffer", 234 arm_dcache_align, /* minimum_alignment */ 235 NULL, /* uma_alloc func */ 236 NULL, /* uma_free func */ 237 uma_flags); /* uma_zcreate_flags */ 238 239#ifdef INVARIANTS 240 /* 241 * Force UMA zone to allocate service structures like 242 * slabs using own allocator. uma_debug code performs 243 * atomic ops on uma_slab_t fields and safety of this 244 * operation is not guaranteed for write-back caches 245 */ 246 uma_flags = UMA_ZONE_OFFPAGE; 247#endif 248 /* 249 * Create a cache of buffers in uncacheable memory, to implement the 250 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 251 */ 252 coherent_allocator = busdma_bufalloc_create("coherent", 253 arm_dcache_align, /* minimum_alignment */ 254 busdma_bufalloc_alloc_uncacheable, 255 busdma_bufalloc_free_uncacheable, 256 uma_flags); /* uma_zcreate_flags */ 257} 258 259/* 260 * This init historically used SI_SUB_VM, but now the init code requires 261 * malloc(9) using M_DEVBUF memory and the pcpu zones for counter(9), which get 262 * set up by SI_SUB_KMEM and SI_ORDER_LAST, so we'll go right after that by 263 * using SI_SUB_KMEM+1. 264 */ 265SYSINIT(busdma, SI_SUB_KMEM+1, SI_ORDER_FIRST, busdma_init, NULL); 266 267/* 268 * This routine checks the exclusion zone constraints from a tag against the 269 * physical RAM available on the machine. If a tag specifies an exclusion zone 270 * but there's no RAM in that zone, then we avoid allocating resources to bounce 271 * a request, and we can use any memory allocator (as opposed to needing 272 * kmem_alloc_contig() just because it can allocate pages in an address range). 273 * 274 * Most tags have BUS_SPACE_MAXADDR or BUS_SPACE_MAXADDR_32BIT (they are the 275 * same value on 32-bit architectures) as their lowaddr constraint, and we can't 276 * possibly have RAM at an address higher than the highest address we can 277 * express, so we take a fast out. 278 */ 279static int 280exclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr) 281{ 282 int i; 283 284 if (lowaddr >= BUS_SPACE_MAXADDR) 285 return (0); 286 287 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 288 if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) || 289 (lowaddr < phys_avail[i] && highaddr >= phys_avail[i])) 290 return (1); 291 } 292 return (0); 293} 294 295/* 296 * Return true if the tag has an exclusion zone that could lead to bouncing. 297 */ 298static __inline int 299exclusion_bounce(bus_dma_tag_t dmat) 300{ 301 302 return (dmat->flags & BUS_DMA_EXCL_BOUNCE); 303} 304 305/* 306 * Return true if the given address does not fall on the alignment boundary. 307 */ 308static __inline int 309alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr) 310{ 311 312 return (addr & (dmat->alignment - 1)); 313} 314 315/* 316 * Return true if the DMA should bounce because the start or end does not fall 317 * on a cacheline boundary (which would require a partial cacheline flush). 318 * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by 319 * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a 320 * strict rule that such memory cannot be accessed by the CPU while DMA is in 321 * progress (or by multiple DMA engines at once), so that it's always safe to do 322 * full cacheline flushes even if that affects memory outside the range of a 323 * given DMA operation that doesn't involve the full allocated buffer. If we're 324 * mapping an mbuf, that follows the same rules as a buffer we allocated. 325 */ 326static __inline int 327cacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size) 328{ 329 330 if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF)) 331 return (0); 332 return ((addr | size) & arm_dcache_align_mask); 333} 334 335/* 336 * Return true if we might need to bounce the DMA described by addr and size. 337 * 338 * This is used to quick-check whether we need to do the more expensive work of 339 * checking the DMA page-by-page looking for alignment and exclusion bounces. 340 * 341 * Note that the addr argument might be either virtual or physical. It doesn't 342 * matter because we only look at the low-order bits, which are the same in both 343 * address spaces. 344 */ 345static __inline int 346might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr, 347 bus_size_t size) 348{ 349 350 return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) || 351 alignment_bounce(dmat, addr) || 352 cacheline_bounce(map, addr, size)); 353} 354 355/* 356 * Return true if we must bounce the DMA described by paddr and size. 357 * 358 * Bouncing can be triggered by DMA that doesn't begin and end on cacheline 359 * boundaries, or doesn't begin on an alignment boundary, or falls within the 360 * exclusion zone of any tag in the ancestry chain. 361 * 362 * For exclusions, walk the chain of tags comparing paddr to the exclusion zone 363 * within each tag. If the tag has a filter function, use it to decide whether 364 * the DMA needs to bounce, otherwise any DMA within the zone bounces. 365 */ 366static int 367must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, 368 bus_size_t size) 369{ 370 371 if (cacheline_bounce(map, paddr, size)) 372 return (1); 373 374 /* 375 * The tag already contains ancestors' alignment restrictions so this 376 * check doesn't need to be inside the loop. 377 */ 378 if (alignment_bounce(dmat, paddr)) 379 return (1); 380 381 /* 382 * Even though each tag has an exclusion zone that is a superset of its 383 * own and all its ancestors' exclusions, the exclusion zone of each tag 384 * up the chain must be checked within the loop, because the busdma 385 * rules say the filter function is called only when the address lies 386 * within the low-highaddr range of the tag that filterfunc belongs to. 387 */ 388 while (dmat != NULL && exclusion_bounce(dmat)) { 389 if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) && 390 (dmat->filter == NULL || 391 dmat->filter(dmat->filterarg, paddr) != 0)) 392 return (1); 393 dmat = dmat->parent; 394 } 395 396 return (0); 397} 398 399static __inline struct arm32_dma_range * 400_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 401 bus_addr_t curaddr) 402{ 403 struct arm32_dma_range *dr; 404 int i; 405 406 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 407 if (curaddr >= dr->dr_sysbase && 408 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 409 return (dr); 410 } 411 412 return (NULL); 413} 414 415/* 416 * Convenience function for manipulating driver locks from busdma (during 417 * busdma_swi, for example). Drivers that don't provide their own locks 418 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 419 * non-mutex locking scheme don't have to use this at all. 420 */ 421void 422busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 423{ 424 struct mtx *dmtx; 425 426 dmtx = (struct mtx *)arg; 427 switch (op) { 428 case BUS_DMA_LOCK: 429 mtx_lock(dmtx); 430 break; 431 case BUS_DMA_UNLOCK: 432 mtx_unlock(dmtx); 433 break; 434 default: 435 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 436 } 437} 438 439/* 440 * dflt_lock should never get called. It gets put into the dma tag when 441 * lockfunc == NULL, which is only valid if the maps that are associated 442 * with the tag are meant to never be defered. 443 * XXX Should have a way to identify which driver is responsible here. 444 */ 445static void 446dflt_lock(void *arg, bus_dma_lock_op_t op) 447{ 448 449 panic("driver error: busdma dflt_lock called"); 450} 451 452/* 453 * Allocate a device specific dma_tag. 454 */ 455int 456bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 457 bus_size_t boundary, bus_addr_t lowaddr, 458 bus_addr_t highaddr, bus_dma_filter_t *filter, 459 void *filterarg, bus_size_t maxsize, int nsegments, 460 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 461 void *lockfuncarg, bus_dma_tag_t *dmat) 462{ 463 bus_dma_tag_t newtag; 464 int error = 0; 465 466#if 0 467 if (!parent) 468 parent = arm_root_dma_tag; 469#endif 470 471 /* Basic sanity checking. */ 472 KASSERT(boundary == 0 || powerof2(boundary), 473 ("dma tag boundary %lu, must be a power of 2", boundary)); 474 KASSERT(boundary == 0 || boundary >= maxsegsz, 475 ("dma tag boundary %lu is < maxsegsz %lu\n", boundary, maxsegsz)); 476 KASSERT(alignment != 0 && powerof2(alignment), 477 ("dma tag alignment %lu, must be non-zero power of 2", alignment)); 478 KASSERT(maxsegsz != 0, ("dma tag maxsegsz must not be zero")); 479 480 /* Return a NULL tag on failure */ 481 *dmat = NULL; 482 483 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 484 M_ZERO | M_NOWAIT); 485 if (newtag == NULL) { 486 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 487 __func__, newtag, 0, error); 488 return (ENOMEM); 489 } 490 491 newtag->parent = parent; 492 newtag->alignment = alignment; 493 newtag->boundary = boundary; 494 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 495 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 496 (PAGE_SIZE - 1); 497 newtag->filter = filter; 498 newtag->filterarg = filterarg; 499 newtag->maxsize = maxsize; 500 newtag->nsegments = nsegments; 501 newtag->maxsegsz = maxsegsz; 502 newtag->flags = flags; 503 newtag->ref_count = 1; /* Count ourself */ 504 newtag->map_count = 0; 505 newtag->ranges = bus_dma_get_range(); 506 newtag->_nranges = bus_dma_get_range_nb(); 507 if (lockfunc != NULL) { 508 newtag->lockfunc = lockfunc; 509 newtag->lockfuncarg = lockfuncarg; 510 } else { 511 newtag->lockfunc = dflt_lock; 512 newtag->lockfuncarg = NULL; 513 } 514 515 /* Take into account any restrictions imposed by our parent tag */ 516 if (parent != NULL) { 517 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 518 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 519 newtag->alignment = MAX(parent->alignment, newtag->alignment); 520 newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE; 521 if (newtag->boundary == 0) 522 newtag->boundary = parent->boundary; 523 else if (parent->boundary != 0) 524 newtag->boundary = MIN(parent->boundary, 525 newtag->boundary); 526 if (newtag->filter == NULL) { 527 /* 528 * Short circuit to looking at our parent directly 529 * since we have encapsulated all of its information 530 */ 531 newtag->filter = parent->filter; 532 newtag->filterarg = parent->filterarg; 533 newtag->parent = parent->parent; 534 } 535 if (newtag->parent != NULL) 536 atomic_add_int(&parent->ref_count, 1); 537 } 538 539 if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr)) 540 newtag->flags |= BUS_DMA_EXCL_BOUNCE; 541 if (alignment_bounce(newtag, 1)) 542 newtag->flags |= BUS_DMA_ALIGN_BOUNCE; 543 544 /* 545 * Any request can auto-bounce due to cacheline alignment, in addition 546 * to any alignment or boundary specifications in the tag, so if the 547 * ALLOCNOW flag is set, there's always work to do. 548 */ 549 if ((flags & BUS_DMA_ALLOCNOW) != 0) { 550 struct bounce_zone *bz; 551 /* 552 * Round size up to a full page, and add one more page because 553 * there can always be one more boundary crossing than the 554 * number of pages in a transfer. 555 */ 556 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 557 558 if ((error = alloc_bounce_zone(newtag)) != 0) { 559 free(newtag, M_DEVBUF); 560 return (error); 561 } 562 bz = newtag->bounce_zone; 563 564 if (ptoa(bz->total_bpages) < maxsize) { 565 int pages; 566 567 pages = atop(maxsize) - bz->total_bpages; 568 569 /* Add pages to our bounce pool */ 570 if (alloc_bounce_pages(newtag, pages) < pages) 571 error = ENOMEM; 572 } 573 /* Performed initial allocation */ 574 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 575 } else 576 newtag->bounce_zone = NULL; 577 578 if (error != 0) { 579 free(newtag, M_DEVBUF); 580 } else { 581 atomic_add_32(&tags_total, 1); 582 *dmat = newtag; 583 } 584 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 585 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 586 return (error); 587} 588 589int 590bus_dma_tag_destroy(bus_dma_tag_t dmat) 591{ 592 bus_dma_tag_t dmat_copy; 593 int error; 594 595 error = 0; 596 dmat_copy = dmat; 597 598 if (dmat != NULL) { 599 600 if (dmat->map_count != 0) { 601 error = EBUSY; 602 goto out; 603 } 604 605 while (dmat != NULL) { 606 bus_dma_tag_t parent; 607 608 parent = dmat->parent; 609 atomic_subtract_int(&dmat->ref_count, 1); 610 if (dmat->ref_count == 0) { 611 atomic_subtract_32(&tags_total, 1); 612 free(dmat, M_DEVBUF); 613 /* 614 * Last reference count, so 615 * release our reference 616 * count on our parent. 617 */ 618 dmat = parent; 619 } else 620 dmat = NULL; 621 } 622 } 623out: 624 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 625 return (error); 626} 627 628static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 629{ 630 struct bounce_zone *bz; 631 int maxpages; 632 int error; 633 634 if (dmat->bounce_zone == NULL) 635 if ((error = alloc_bounce_zone(dmat)) != 0) 636 return (error); 637 bz = dmat->bounce_zone; 638 /* Initialize the new map */ 639 STAILQ_INIT(&(mapp->bpages)); 640 641 /* 642 * Attempt to add pages to our pool on a per-instance basis up to a sane 643 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 644 * alignment and boundary constraints, it could still auto-bounce due to 645 * cacheline alignment, which requires at most two bounce pages. 646 */ 647 if (dmat->flags & BUS_DMA_COULD_BOUNCE) 648 maxpages = MAX_BPAGES; 649 else 650 maxpages = 2 * bz->map_count; 651 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 || 652 (bz->map_count > 0 && bz->total_bpages < maxpages)) { 653 int pages; 654 655 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 656 pages = MIN(maxpages - bz->total_bpages, pages); 657 pages = MAX(pages, 2); 658 if (alloc_bounce_pages(dmat, pages) < pages) 659 return (ENOMEM); 660 661 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 662 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 663 } 664 bz->map_count++; 665 return (0); 666} 667 668static bus_dmamap_t 669allocate_map(bus_dma_tag_t dmat, int mflags) 670{ 671 int mapsize, segsize; 672 bus_dmamap_t map; 673 674 /* 675 * Allocate the map. The map structure ends with an embedded 676 * variable-sized array of sync_list structures. Following that 677 * we allocate enough extra space to hold the array of bus_dma_segments. 678 */ 679 KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS, 680 ("cannot allocate %u dma segments (max is %u)", 681 dmat->nsegments, MAX_DMA_SEGMENTS)); 682 segsize = sizeof(struct bus_dma_segment) * dmat->nsegments; 683 mapsize = sizeof(*map) + sizeof(struct sync_list) * dmat->nsegments; 684 map = malloc(mapsize + segsize, M_DEVBUF, mflags | M_ZERO); 685 if (map == NULL) { 686 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 687 return (NULL); 688 } 689 map->segments = (bus_dma_segment_t *)((uintptr_t)map + mapsize); 690 return (map); 691} 692 693/* 694 * Allocate a handle for mapping from kva/uva/physical 695 * address space into bus device space. 696 */ 697int 698bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 699{ 700 bus_dmamap_t map; 701 int error = 0; 702 703 *mapp = map = allocate_map(dmat, M_NOWAIT); 704 if (map == NULL) { 705 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 706 return (ENOMEM); 707 } 708 709 /* 710 * Bouncing might be required if the driver asks for an exclusion 711 * region, a data alignment that is stricter than 1, or DMA that begins 712 * or ends with a partial cacheline. Whether bouncing will actually 713 * happen can't be known until mapping time, but we need to pre-allocate 714 * resources now because we might not be allowed to at mapping time. 715 */ 716 error = allocate_bz_and_pages(dmat, map); 717 if (error != 0) { 718 free(map, M_DEVBUF); 719 *mapp = NULL; 720 return (error); 721 } 722 if (map->flags & DMAMAP_COHERENT) 723 atomic_add_32(&maps_coherent, 1); 724 atomic_add_32(&maps_total, 1); 725 dmat->map_count++; 726 727 return (0); 728} 729 730/* 731 * Destroy a handle for mapping from kva/uva/physical 732 * address space into bus device space. 733 */ 734int 735bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 736{ 737 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 738 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 739 __func__, dmat, EBUSY); 740 return (EBUSY); 741 } 742 if (dmat->bounce_zone) 743 dmat->bounce_zone->map_count--; 744 if (map->flags & DMAMAP_COHERENT) 745 atomic_subtract_32(&maps_coherent, 1); 746 atomic_subtract_32(&maps_total, 1); 747 free(map, M_DEVBUF); 748 dmat->map_count--; 749 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 750 return (0); 751} 752 753 754/* 755 * Allocate a piece of memory that can be efficiently mapped into 756 * bus device space based on the constraints lited in the dma tag. 757 * A dmamap to for use with dmamap_load is also allocated. 758 */ 759int 760bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 761 bus_dmamap_t *mapp) 762{ 763 busdma_bufalloc_t ba; 764 struct busdma_bufzone *bufzone; 765 bus_dmamap_t map; 766 vm_memattr_t memattr; 767 int mflags; 768 769 if (flags & BUS_DMA_NOWAIT) 770 mflags = M_NOWAIT; 771 else 772 mflags = M_WAITOK; 773 if (flags & BUS_DMA_ZERO) 774 mflags |= M_ZERO; 775 776 *mapp = map = allocate_map(dmat, mflags); 777 if (map == NULL) { 778 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 779 __func__, dmat, dmat->flags, ENOMEM); 780 return (ENOMEM); 781 } 782 map->flags = DMAMAP_DMAMEM_ALLOC; 783 784 /* Choose a busdma buffer allocator based on memory type flags. */ 785 if (flags & BUS_DMA_COHERENT) { 786 memattr = VM_MEMATTR_UNCACHEABLE; 787 ba = coherent_allocator; 788 map->flags |= DMAMAP_COHERENT; 789 } else { 790 memattr = VM_MEMATTR_DEFAULT; 791 ba = standard_allocator; 792 } 793 794 /* 795 * Try to find a bufzone in the allocator that holds a cache of buffers 796 * of the right size for this request. If the buffer is too big to be 797 * held in the allocator cache, this returns NULL. 798 */ 799 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 800 801 /* 802 * Allocate the buffer from the uma(9) allocator if... 803 * - It's small enough to be in the allocator (bufzone not NULL). 804 * - The alignment constraint isn't larger than the allocation size 805 * (the allocator aligns buffers to their size boundaries). 806 * - There's no need to handle lowaddr/highaddr exclusion zones. 807 * else allocate non-contiguous pages if... 808 * - The page count that could get allocated doesn't exceed nsegments. 809 * - The alignment constraint isn't larger than a page boundary. 810 * - There are no boundary-crossing constraints. 811 * else allocate a block of contiguous pages because one or more of the 812 * constraints is something that only the contig allocator can fulfill. 813 */ 814 if (bufzone != NULL && dmat->alignment <= bufzone->size && 815 !exclusion_bounce(dmat)) { 816 *vaddr = uma_zalloc(bufzone->umazone, mflags); 817 } else if (dmat->nsegments >= btoc(dmat->maxsize) && 818 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 819 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 820 mflags, 0, dmat->lowaddr, memattr); 821 } else { 822 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 823 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 824 memattr); 825 } 826 827 828 if (*vaddr == NULL) { 829 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 830 __func__, dmat, dmat->flags, ENOMEM); 831 free(map, M_DEVBUF); 832 *mapp = NULL; 833 return (ENOMEM); 834 } 835 if (map->flags & DMAMAP_COHERENT) 836 atomic_add_32(&maps_coherent, 1); 837 atomic_add_32(&maps_dmamem, 1); 838 atomic_add_32(&maps_total, 1); 839 dmat->map_count++; 840 841 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 842 __func__, dmat, dmat->flags, 0); 843 return (0); 844} 845 846/* 847 * Free a piece of memory and it's allociated dmamap, that was allocated 848 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 849 */ 850void 851bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 852{ 853 struct busdma_bufzone *bufzone; 854 busdma_bufalloc_t ba; 855 856 if (map->flags & DMAMAP_COHERENT) 857 ba = coherent_allocator; 858 else 859 ba = standard_allocator; 860 861 /* Be careful not to access map from here on. */ 862 863 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 864 865 if (bufzone != NULL && dmat->alignment <= bufzone->size && 866 !exclusion_bounce(dmat)) 867 uma_zfree(bufzone->umazone, vaddr); 868 else 869 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 870 871 dmat->map_count--; 872 if (map->flags & DMAMAP_COHERENT) 873 atomic_subtract_32(&maps_coherent, 1); 874 atomic_subtract_32(&maps_total, 1); 875 atomic_subtract_32(&maps_dmamem, 1); 876 free(map, M_DEVBUF); 877 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 878} 879 880static void 881_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 882 bus_size_t buflen, int flags) 883{ 884 bus_addr_t curaddr; 885 bus_size_t sgsize; 886 887 if (map->pagesneeded == 0) { 888 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 889 " map= %p, pagesneeded= %d", 890 dmat->lowaddr, dmat->boundary, dmat->alignment, 891 map, map->pagesneeded); 892 /* 893 * Count the number of bounce pages 894 * needed in order to complete this transfer 895 */ 896 curaddr = buf; 897 while (buflen != 0) { 898 sgsize = MIN(buflen, dmat->maxsegsz); 899 if (must_bounce(dmat, map, curaddr, sgsize) != 0) { 900 sgsize = MIN(sgsize, PAGE_SIZE); 901 map->pagesneeded++; 902 } 903 curaddr += sgsize; 904 buflen -= sgsize; 905 } 906 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 907 } 908} 909 910static void 911_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 912 void *buf, bus_size_t buflen, int flags) 913{ 914 vm_offset_t vaddr; 915 vm_offset_t vendaddr; 916 bus_addr_t paddr; 917 918 if (map->pagesneeded == 0) { 919 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 920 " map= %p, pagesneeded= %d", 921 dmat->lowaddr, dmat->boundary, dmat->alignment, 922 map, map->pagesneeded); 923 /* 924 * Count the number of bounce pages 925 * needed in order to complete this transfer 926 */ 927 vaddr = (vm_offset_t)buf; 928 vendaddr = (vm_offset_t)buf + buflen; 929 930 while (vaddr < vendaddr) { 931 if (__predict_true(map->pmap == kernel_pmap)) 932 paddr = pmap_kextract(vaddr); 933 else 934 paddr = pmap_extract(map->pmap, vaddr); 935 if (must_bounce(dmat, map, paddr, 936 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr & 937 PAGE_MASK)))) != 0) { 938 map->pagesneeded++; 939 } 940 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 941 942 } 943 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 944 } 945} 946 947static int 948_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 949{ 950 951 /* Reserve Necessary Bounce Pages */ 952 mtx_lock(&bounce_lock); 953 if (flags & BUS_DMA_NOWAIT) { 954 if (reserve_bounce_pages(dmat, map, 0) != 0) { 955 map->pagesneeded = 0; 956 mtx_unlock(&bounce_lock); 957 return (ENOMEM); 958 } 959 } else { 960 if (reserve_bounce_pages(dmat, map, 1) != 0) { 961 /* Queue us for resources */ 962 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 963 mtx_unlock(&bounce_lock); 964 return (EINPROGRESS); 965 } 966 } 967 mtx_unlock(&bounce_lock); 968 969 return (0); 970} 971 972/* 973 * Add a single contiguous physical range to the segment list. 974 */ 975static int 976_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 977 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 978{ 979 bus_addr_t baddr, bmask; 980 int seg; 981 982 /* 983 * Make sure we don't cross any boundaries. 984 */ 985 bmask = ~(dmat->boundary - 1); 986 if (dmat->boundary > 0) { 987 baddr = (curaddr + dmat->boundary) & bmask; 988 if (sgsize > (baddr - curaddr)) 989 sgsize = (baddr - curaddr); 990 } 991 992 if (dmat->ranges) { 993 struct arm32_dma_range *dr; 994 995 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 996 curaddr); 997 if (dr == NULL) { 998 _bus_dmamap_unload(dmat, map); 999 return (0); 1000 } 1001 /* 1002 * In a valid DMA range. Translate the physical 1003 * memory address to an address in the DMA window. 1004 */ 1005 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 1006 } 1007 1008 /* 1009 * Insert chunk into a segment, coalescing with 1010 * previous segment if possible. 1011 */ 1012 seg = *segp; 1013 if (seg == -1) { 1014 seg = 0; 1015 segs[seg].ds_addr = curaddr; 1016 segs[seg].ds_len = sgsize; 1017 } else { 1018 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 1019 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 1020 (dmat->boundary == 0 || 1021 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 1022 segs[seg].ds_len += sgsize; 1023 else { 1024 if (++seg >= dmat->nsegments) 1025 return (0); 1026 segs[seg].ds_addr = curaddr; 1027 segs[seg].ds_len = sgsize; 1028 } 1029 } 1030 *segp = seg; 1031 return (sgsize); 1032} 1033 1034/* 1035 * Utility function to load a physical buffer. segp contains 1036 * the starting segment on entrace, and the ending segment on exit. 1037 */ 1038int 1039_bus_dmamap_load_phys(bus_dma_tag_t dmat, 1040 bus_dmamap_t map, 1041 vm_paddr_t buf, bus_size_t buflen, 1042 int flags, 1043 bus_dma_segment_t *segs, 1044 int *segp) 1045{ 1046 bus_addr_t curaddr; 1047 bus_size_t sgsize; 1048 int error; 1049 1050 if (segs == NULL) 1051 segs = map->segments; 1052 1053 counter_u64_add(maploads_total, 1); 1054 counter_u64_add(maploads_physmem, 1); 1055 1056 if (might_bounce(dmat, map, buflen, buflen)) { 1057 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 1058 if (map->pagesneeded != 0) { 1059 counter_u64_add(maploads_bounced, 1); 1060 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1061 if (error) 1062 return (error); 1063 } 1064 } 1065 1066 while (buflen > 0) { 1067 curaddr = buf; 1068 sgsize = MIN(buflen, dmat->maxsegsz); 1069 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1070 sgsize)) { 1071 sgsize = MIN(sgsize, PAGE_SIZE); 1072 curaddr = add_bounce_page(dmat, map, 0, curaddr, 1073 sgsize); 1074 } 1075 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1076 segp); 1077 if (sgsize == 0) 1078 break; 1079 buf += sgsize; 1080 buflen -= sgsize; 1081 } 1082 1083 /* 1084 * Did we fit? 1085 */ 1086 if (buflen != 0) { 1087 _bus_dmamap_unload(dmat, map); 1088 return (EFBIG); /* XXX better return value here? */ 1089 } 1090 return (0); 1091} 1092 1093int 1094_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 1095 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 1096 bus_dma_segment_t *segs, int *segp) 1097{ 1098 1099 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 1100 segs, segp)); 1101} 1102 1103/* 1104 * Utility function to load a linear buffer. segp contains 1105 * the starting segment on entrace, and the ending segment on exit. 1106 */ 1107int 1108_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1109 bus_dmamap_t map, 1110 void *buf, bus_size_t buflen, 1111 pmap_t pmap, 1112 int flags, 1113 bus_dma_segment_t *segs, 1114 int *segp) 1115{ 1116 bus_size_t sgsize; 1117 bus_addr_t curaddr; 1118 vm_offset_t vaddr; 1119 struct sync_list *sl; 1120 int error; 1121 1122 counter_u64_add(maploads_total, 1); 1123 if (map->flags & DMAMAP_COHERENT) 1124 counter_u64_add(maploads_coherent, 1); 1125 if (map->flags & DMAMAP_DMAMEM_ALLOC) 1126 counter_u64_add(maploads_dmamem, 1); 1127 1128 if (segs == NULL) 1129 segs = map->segments; 1130 1131 if (flags & BUS_DMA_LOAD_MBUF) { 1132 counter_u64_add(maploads_mbuf, 1); 1133 map->flags |= DMAMAP_MBUF; 1134 } 1135 1136 map->pmap = pmap; 1137 1138 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) { 1139 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1140 if (map->pagesneeded != 0) { 1141 counter_u64_add(maploads_bounced, 1); 1142 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1143 if (error) 1144 return (error); 1145 } 1146 } 1147 1148 sl = NULL; 1149 vaddr = (vm_offset_t)buf; 1150 1151 while (buflen > 0) { 1152 /* 1153 * Get the physical address for this segment. 1154 */ 1155 if (__predict_true(map->pmap == kernel_pmap)) 1156 curaddr = pmap_kextract(vaddr); 1157 else 1158 curaddr = pmap_extract(map->pmap, vaddr); 1159 1160 /* 1161 * Compute the segment size, and adjust counts. 1162 */ 1163 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1164 if (sgsize > dmat->maxsegsz) 1165 sgsize = dmat->maxsegsz; 1166 if (buflen < sgsize) 1167 sgsize = buflen; 1168 1169 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1170 sgsize)) { 1171 curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1172 sgsize); 1173 } else { 1174 sl = &map->slist[map->sync_count - 1]; 1175 if (map->sync_count == 0 || 1176#ifdef ARM_L2_PIPT 1177 curaddr != sl->busaddr + sl->datacount || 1178#endif 1179 vaddr != sl->vaddr + sl->datacount) { 1180 if (++map->sync_count > dmat->nsegments) 1181 goto cleanup; 1182 sl++; 1183 sl->vaddr = vaddr; 1184 sl->datacount = sgsize; 1185 sl->busaddr = curaddr; 1186 } else 1187 sl->datacount += sgsize; 1188 } 1189 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1190 segp); 1191 if (sgsize == 0) 1192 break; 1193 vaddr += sgsize; 1194 buflen -= sgsize; 1195 } 1196 1197cleanup: 1198 /* 1199 * Did we fit? 1200 */ 1201 if (buflen != 0) { 1202 _bus_dmamap_unload(dmat, map); 1203 return (EFBIG); /* XXX better return value here? */ 1204 } 1205 return (0); 1206} 1207 1208 1209void 1210__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1211 struct memdesc *mem, bus_dmamap_callback_t *callback, 1212 void *callback_arg) 1213{ 1214 1215 map->mem = *mem; 1216 map->dmat = dmat; 1217 map->callback = callback; 1218 map->callback_arg = callback_arg; 1219} 1220 1221bus_dma_segment_t * 1222_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1223 bus_dma_segment_t *segs, int nsegs, int error) 1224{ 1225 1226 if (segs == NULL) 1227 segs = map->segments; 1228 return (segs); 1229} 1230 1231/* 1232 * Release the mapping held by map. 1233 */ 1234void 1235_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1236{ 1237 struct bounce_page *bpage; 1238 struct bounce_zone *bz; 1239 1240 if ((bz = dmat->bounce_zone) != NULL) { 1241 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1242 STAILQ_REMOVE_HEAD(&map->bpages, links); 1243 free_bounce_page(dmat, bpage); 1244 } 1245 1246 bz = dmat->bounce_zone; 1247 bz->free_bpages += map->pagesreserved; 1248 bz->reserved_bpages -= map->pagesreserved; 1249 map->pagesreserved = 0; 1250 map->pagesneeded = 0; 1251 } 1252 map->sync_count = 0; 1253 map->flags &= ~DMAMAP_MBUF; 1254} 1255 1256#ifdef notyetbounceuser 1257/* If busdma uses user pages, then the interrupt handler could 1258 * be use the kernel vm mapping. Both bounce pages and sync list 1259 * do not cross page boundaries. 1260 * Below is a rough sequence that a person would do to fix the 1261 * user page reference in the kernel vmspace. This would be 1262 * done in the dma post routine. 1263 */ 1264void 1265_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1266 pmap_t pmap, int op) 1267{ 1268 bus_size_t sgsize; 1269 bus_addr_t curaddr; 1270 vm_offset_t va; 1271 1272 /* 1273 * each synclist entry is contained within a single page. 1274 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1275 */ 1276 curaddr = pmap_extract(pmap, buf); 1277 va = pmap_dma_map(curaddr); 1278 switch (op) { 1279 case SYNC_USER_INV: 1280 cpu_dcache_wb_range(va, sgsize); 1281 break; 1282 1283 case SYNC_USER_COPYTO: 1284 bcopy((void *)va, (void *)bounce, sgsize); 1285 break; 1286 1287 case SYNC_USER_COPYFROM: 1288 bcopy((void *) bounce, (void *)va, sgsize); 1289 break; 1290 1291 default: 1292 break; 1293 } 1294 1295 pmap_dma_unmap(va); 1296} 1297#endif 1298 1299#ifdef ARM_L2_PIPT 1300#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1301#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1302#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1303#else 1304#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1305#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1306#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1307#endif 1308 1309void 1310_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1311{ 1312 struct bounce_page *bpage; 1313 struct sync_list *sl, *end; 1314 /* 1315 * If the buffer was from user space, it is possible that this is not 1316 * the same vm map, especially on a POST operation. It's not clear that 1317 * dma on userland buffers can work at all right now, certainly not if a 1318 * partial cacheline flush has to be handled. To be safe, until we're 1319 * able to test direct userland dma, panic on a map mismatch. 1320 */ 1321 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1322 if (!pmap_dmap_iscurrent(map->pmap)) 1323 panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1324 /* Handle data bouncing. */ 1325 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1326 "performing bounce", __func__, dmat, dmat->flags, op); 1327 1328 if (op & BUS_DMASYNC_PREWRITE) { 1329 while (bpage != NULL) { 1330 if (bpage->datavaddr != 0) 1331 bcopy((void *)bpage->datavaddr, 1332 (void *)bpage->vaddr, 1333 bpage->datacount); 1334 else 1335 physcopyout(bpage->dataaddr, 1336 (void *)bpage->vaddr, 1337 bpage->datacount); 1338 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1339 bpage->datacount); 1340 l2cache_wb_range((vm_offset_t)bpage->vaddr, 1341 (vm_offset_t)bpage->busaddr, 1342 bpage->datacount); 1343 bpage = STAILQ_NEXT(bpage, links); 1344 } 1345 dmat->bounce_zone->total_bounced++; 1346 } 1347 1348 if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) { 1349 bpage = STAILQ_FIRST(&map->bpages); 1350 while (bpage != NULL) { 1351 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1352 bpage->datacount); 1353 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1354 (vm_offset_t)bpage->busaddr, 1355 bpage->datacount); 1356 bpage = STAILQ_NEXT(bpage, links); 1357 } 1358 } 1359 if (op & BUS_DMASYNC_POSTREAD) { 1360 while (bpage != NULL) { 1361 vm_offset_t startv; 1362 vm_paddr_t startp; 1363 int len; 1364 1365 startv = bpage->vaddr &~ arm_dcache_align_mask; 1366 startp = bpage->busaddr &~ arm_dcache_align_mask; 1367 len = bpage->datacount; 1368 1369 if (startv != bpage->vaddr) 1370 len += bpage->vaddr & arm_dcache_align_mask; 1371 if (len & arm_dcache_align_mask) 1372 len = (len - 1373 (len & arm_dcache_align_mask)) + 1374 arm_dcache_align; 1375 cpu_dcache_inv_range(startv, len); 1376 l2cache_inv_range(startv, startp, len); 1377 if (bpage->datavaddr != 0) 1378 bcopy((void *)bpage->vaddr, 1379 (void *)bpage->datavaddr, 1380 bpage->datacount); 1381 else 1382 physcopyin((void *)bpage->vaddr, 1383 bpage->dataaddr, 1384 bpage->datacount); 1385 bpage = STAILQ_NEXT(bpage, links); 1386 } 1387 dmat->bounce_zone->total_bounced++; 1388 } 1389 } 1390 1391 /* 1392 * For COHERENT memory no cache maintenance is necessary, but ensure all 1393 * writes have reached memory for the PREWRITE case. No action is 1394 * needed for a PREREAD without PREWRITE also set, because that would 1395 * imply that the cpu had written to the COHERENT buffer and expected 1396 * the dma device to see that change, and by definition a PREWRITE sync 1397 * is required to make that happen. 1398 */ 1399 if (map->flags & DMAMAP_COHERENT) { 1400 if (op & BUS_DMASYNC_PREWRITE) { 1401 dsb(); 1402 cpu_l2cache_drain_writebuf(); 1403 } 1404 return; 1405 } 1406 1407 if (map->sync_count != 0) { 1408 if (!pmap_dmap_iscurrent(map->pmap)) 1409 panic("_bus_dmamap_sync: wrong user map for sync."); 1410 /* ARM caches are not self-snooping for dma */ 1411 1412 sl = &map->slist[0]; 1413 end = &map->slist[map->sync_count]; 1414 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1415 "performing sync", __func__, dmat, dmat->flags, op); 1416 1417 switch (op) { 1418 case BUS_DMASYNC_PREWRITE: 1419 while (sl != end) { 1420 cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1421 l2cache_wb_range(sl->vaddr, sl->busaddr, 1422 sl->datacount); 1423 sl++; 1424 } 1425 break; 1426 1427 case BUS_DMASYNC_PREREAD: 1428 while (sl != end) { 1429 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1430 l2cache_inv_range(sl->vaddr, sl->busaddr, 1431 sl->datacount); 1432 sl++; 1433 } 1434 break; 1435 1436 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1437 while (sl != end) { 1438 cpu_dcache_wbinv_range(sl->vaddr, sl->datacount); 1439 l2cache_wbinv_range(sl->vaddr, 1440 sl->busaddr, sl->datacount); 1441 sl++; 1442 } 1443 break; 1444 1445 case BUS_DMASYNC_POSTREAD: 1446 case BUS_DMASYNC_POSTWRITE: 1447 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1448 break; 1449 default: 1450 panic("unsupported combination of sync operations: 0x%08x\n", op); 1451 break; 1452 } 1453 } 1454} 1455 1456static void 1457init_bounce_pages(void *dummy __unused) 1458{ 1459 1460 total_bpages = 0; 1461 STAILQ_INIT(&bounce_zone_list); 1462 STAILQ_INIT(&bounce_map_waitinglist); 1463 STAILQ_INIT(&bounce_map_callbacklist); 1464 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1465} 1466SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1467 1468static struct sysctl_ctx_list * 1469busdma_sysctl_tree(struct bounce_zone *bz) 1470{ 1471 1472 return (&bz->sysctl_tree); 1473} 1474 1475static struct sysctl_oid * 1476busdma_sysctl_tree_top(struct bounce_zone *bz) 1477{ 1478 1479 return (bz->sysctl_tree_top); 1480} 1481 1482static int 1483alloc_bounce_zone(bus_dma_tag_t dmat) 1484{ 1485 struct bounce_zone *bz; 1486 1487 /* Check to see if we already have a suitable zone */ 1488 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1489 if ((dmat->alignment <= bz->alignment) && 1490 (dmat->lowaddr >= bz->lowaddr)) { 1491 dmat->bounce_zone = bz; 1492 return (0); 1493 } 1494 } 1495 1496 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1497 M_NOWAIT | M_ZERO)) == NULL) 1498 return (ENOMEM); 1499 1500 STAILQ_INIT(&bz->bounce_page_list); 1501 bz->free_bpages = 0; 1502 bz->reserved_bpages = 0; 1503 bz->active_bpages = 0; 1504 bz->lowaddr = dmat->lowaddr; 1505 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1506 bz->map_count = 0; 1507 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1508 busdma_zonecount++; 1509 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1510 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1511 dmat->bounce_zone = bz; 1512 1513 sysctl_ctx_init(&bz->sysctl_tree); 1514 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1515 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1516 CTLFLAG_RD, 0, ""); 1517 if (bz->sysctl_tree_top == NULL) { 1518 sysctl_ctx_free(&bz->sysctl_tree); 1519 return (0); /* XXX error code? */ 1520 } 1521 1522 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1523 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1524 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1525 "Total bounce pages"); 1526 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1527 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1528 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1529 "Free bounce pages"); 1530 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1531 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1532 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1533 "Reserved bounce pages"); 1534 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1535 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1536 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1537 "Active bounce pages"); 1538 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1539 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1540 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1541 "Total bounce requests (pages bounced)"); 1542 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1543 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1544 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1545 "Total bounce requests that were deferred"); 1546 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1547 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1548 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1549 SYSCTL_ADD_ULONG(busdma_sysctl_tree(bz), 1550 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1551 "alignment", CTLFLAG_RD, &bz->alignment, ""); 1552 1553 return (0); 1554} 1555 1556static int 1557alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1558{ 1559 struct bounce_zone *bz; 1560 int count; 1561 1562 bz = dmat->bounce_zone; 1563 count = 0; 1564 while (numpages > 0) { 1565 struct bounce_page *bpage; 1566 1567 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1568 M_NOWAIT | M_ZERO); 1569 1570 if (bpage == NULL) 1571 break; 1572 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1573 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0); 1574 if (bpage->vaddr == 0) { 1575 free(bpage, M_DEVBUF); 1576 break; 1577 } 1578 bpage->busaddr = pmap_kextract(bpage->vaddr); 1579 mtx_lock(&bounce_lock); 1580 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1581 total_bpages++; 1582 bz->total_bpages++; 1583 bz->free_bpages++; 1584 mtx_unlock(&bounce_lock); 1585 count++; 1586 numpages--; 1587 } 1588 return (count); 1589} 1590 1591static int 1592reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1593{ 1594 struct bounce_zone *bz; 1595 int pages; 1596 1597 mtx_assert(&bounce_lock, MA_OWNED); 1598 bz = dmat->bounce_zone; 1599 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1600 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1601 return (map->pagesneeded - (map->pagesreserved + pages)); 1602 bz->free_bpages -= pages; 1603 bz->reserved_bpages += pages; 1604 map->pagesreserved += pages; 1605 pages = map->pagesneeded - map->pagesreserved; 1606 1607 return (pages); 1608} 1609 1610static bus_addr_t 1611add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1612 bus_addr_t addr, bus_size_t size) 1613{ 1614 struct bounce_zone *bz; 1615 struct bounce_page *bpage; 1616 1617 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1618 KASSERT(map != NULL, 1619 ("add_bounce_page: bad map %p", map)); 1620 1621 bz = dmat->bounce_zone; 1622 if (map->pagesneeded == 0) 1623 panic("add_bounce_page: map doesn't need any pages"); 1624 map->pagesneeded--; 1625 1626 if (map->pagesreserved == 0) 1627 panic("add_bounce_page: map doesn't need any pages"); 1628 map->pagesreserved--; 1629 1630 mtx_lock(&bounce_lock); 1631 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1632 if (bpage == NULL) 1633 panic("add_bounce_page: free page list is empty"); 1634 1635 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1636 bz->reserved_bpages--; 1637 bz->active_bpages++; 1638 mtx_unlock(&bounce_lock); 1639 1640 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1641 /* Page offset needs to be preserved. */ 1642 bpage->vaddr |= vaddr & PAGE_MASK; 1643 bpage->busaddr |= vaddr & PAGE_MASK; 1644 } 1645 bpage->datavaddr = vaddr; 1646 bpage->dataaddr = addr; 1647 bpage->datacount = size; 1648 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1649 return (bpage->busaddr); 1650} 1651 1652static void 1653free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1654{ 1655 struct bus_dmamap *map; 1656 struct bounce_zone *bz; 1657 1658 bz = dmat->bounce_zone; 1659 bpage->datavaddr = 0; 1660 bpage->datacount = 0; 1661 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1662 /* 1663 * Reset the bounce page to start at offset 0. Other uses 1664 * of this bounce page may need to store a full page of 1665 * data and/or assume it starts on a page boundary. 1666 */ 1667 bpage->vaddr &= ~PAGE_MASK; 1668 bpage->busaddr &= ~PAGE_MASK; 1669 } 1670 1671 mtx_lock(&bounce_lock); 1672 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1673 bz->free_bpages++; 1674 bz->active_bpages--; 1675 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1676 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1677 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1678 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1679 map, links); 1680 busdma_swi_pending = 1; 1681 bz->total_deferred++; 1682 swi_sched(vm_ih, 0); 1683 } 1684 } 1685 mtx_unlock(&bounce_lock); 1686} 1687 1688void 1689busdma_swi(void) 1690{ 1691 bus_dma_tag_t dmat; 1692 struct bus_dmamap *map; 1693 1694 mtx_lock(&bounce_lock); 1695 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1696 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1697 mtx_unlock(&bounce_lock); 1698 dmat = map->dmat; 1699 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK); 1700 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1701 map->callback_arg, BUS_DMA_WAITOK); 1702 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1703 mtx_lock(&bounce_lock); 1704 } 1705 mtx_unlock(&bounce_lock); 1706} 1707