busdma_machdep-v6.c revision 273599
1179895Sdelphij/*- 2210661Sdelphij * Copyright (c) 2012 Ian Lepore 3199553Syongari * Copyright (c) 2010 Mark Tinguely 4179895Sdelphij * Copyright (c) 2004 Olivier Houchard 5179895Sdelphij * Copyright (c) 2002 Peter Grehan 6199553Syongari * Copyright (c) 1997, 1998 Justin T. Gibbs. 7179895Sdelphij * All rights reserved. 8179895Sdelphij * 9179895Sdelphij * Redistribution and use in source and binary forms, with or without 10199553Syongari * modification, are permitted provided that the following conditions 11179895Sdelphij * are met: 12179895Sdelphij * 1. Redistributions of source code must retain the above copyright 13179895Sdelphij * notice, this list of conditions, and the following disclaimer, 14179895Sdelphij * without modification, immediately at the beginning of the file. 15179895Sdelphij * 2. The name of the author may not be used to endorse or promote products 16179895Sdelphij * derived from this software without specific prior written permission. 17179895Sdelphij * 18179895Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19179895Sdelphij * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20199553Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21179895Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22179895Sdelphij * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23179895Sdelphij * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24179895Sdelphij * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25179895Sdelphij * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26179895Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27179895Sdelphij * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28179895Sdelphij * SUCH DAMAGE. 29179895Sdelphij * 30179895Sdelphij * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31179895Sdelphij */ 32179895Sdelphij 33199553Syongari#include <sys/cdefs.h> 34179895Sdelphij__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 273599 2014-10-24 19:18:39Z loos $"); 35179895Sdelphij 36179895Sdelphij#define _ARM32_BUS_DMA_PRIVATE 37179895Sdelphij#include <sys/param.h> 38179895Sdelphij#include <sys/kdb.h> 39179895Sdelphij#include <ddb/ddb.h> 40179895Sdelphij#include <ddb/db_output.h> 41228325Syongari#include <sys/systm.h> 42228325Syongari#include <sys/malloc.h> 43179895Sdelphij#include <sys/bus.h> 44228326Syongari#include <sys/busdma_bufalloc.h> 45179895Sdelphij#include <sys/counter.h> 46179895Sdelphij#include <sys/interrupt.h> 47179895Sdelphij#include <sys/kernel.h> 48179895Sdelphij#include <sys/ktr.h> 49179895Sdelphij#include <sys/lock.h> 50179895Sdelphij#include <sys/memdesc.h> 51179895Sdelphij#include <sys/proc.h> 52179895Sdelphij#include <sys/mutex.h> 53179895Sdelphij#include <sys/sysctl.h> 54179895Sdelphij#include <sys/uio.h> 55179895Sdelphij 56179895Sdelphij#include <vm/vm.h> 57179895Sdelphij#include <vm/vm_page.h> 58179895Sdelphij#include <vm/vm_map.h> 59179895Sdelphij#include <vm/vm_extern.h> 60228325Syongari#include <vm/vm_kern.h> 61228325Syongari 62179895Sdelphij#include <machine/atomic.h> 63179895Sdelphij#include <machine/bus.h> 64179895Sdelphij#include <machine/cpufunc.h> 65179895Sdelphij#include <machine/md_var.h> 66179895Sdelphij 67179895Sdelphij#define MAX_BPAGES 64 68199558Syongari#define MAX_DMA_SEGMENTS 4096 69179895Sdelphij#define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2 70199558Syongari#define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3 71179895Sdelphij#define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE) 72179895Sdelphij#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 73179895Sdelphij 74179895Sdelphijstruct bounce_zone; 75179895Sdelphij 76179895Sdelphijstruct bus_dma_tag { 77179895Sdelphij bus_dma_tag_t parent; 78179895Sdelphij bus_size_t alignment; 79179895Sdelphij bus_size_t boundary; 80199608Syongari bus_addr_t lowaddr; 81179895Sdelphij bus_addr_t highaddr; 82199548Syongari bus_dma_filter_t *filter; 83179895Sdelphij void *filterarg; 84199548Syongari bus_size_t maxsize; 85199548Syongari u_int nsegments; 86199548Syongari bus_size_t maxsegsz; 87199611Syongari int flags; 88199611Syongari int ref_count; 89199611Syongari int map_count; 90199611Syongari bus_dma_lock_t *lockfunc; 91199611Syongari void *lockfuncarg; 92199611Syongari struct bounce_zone *bounce_zone; 93199611Syongari /* 94199611Syongari * DMA range for this tag. If the page doesn't fall within 95199611Syongari * one of these ranges, an error is returned. The caller 96199611Syongari * may then decide what to do with the transfer. If the 97199611Syongari * range pointer is NULL, it is ignored. 98199611Syongari */ 99179895Sdelphij struct arm32_dma_range *ranges; 100179895Sdelphij int _nranges; 101179895Sdelphij}; 102179895Sdelphij 103179895Sdelphijstruct bounce_page { 104199608Syongari vm_offset_t vaddr; /* kva of bounce buffer */ 105179895Sdelphij bus_addr_t busaddr; /* Physical address */ 106199548Syongari vm_offset_t datavaddr; /* kva of client data */ 107179895Sdelphij bus_addr_t dataaddr; /* client physical address */ 108179895Sdelphij bus_size_t datacount; /* client data count */ 109179895Sdelphij STAILQ_ENTRY(bounce_page) links; 110179895Sdelphij}; 111199608Syongari 112179895Sdelphijstruct sync_list { 113228325Syongari vm_offset_t vaddr; /* kva of bounce buffer */ 114228325Syongari bus_addr_t busaddr; /* Physical address */ 115228325Syongari bus_size_t datacount; /* client data count */ 116228325Syongari}; 117228325Syongari 118228325Syongariint busdma_swi_pending; 119228325Syongari 120228325Syongaristruct bounce_zone { 121228325Syongari STAILQ_ENTRY(bounce_zone) links; 122228325Syongari STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 123228325Syongari int total_bpages; 124228325Syongari int free_bpages; 125228325Syongari int reserved_bpages; 126228325Syongari int active_bpages; 127228325Syongari int total_bounced; 128228325Syongari int total_deferred; 129228325Syongari int map_count; 130228325Syongari bus_size_t alignment; 131228325Syongari bus_addr_t lowaddr; 132228325Syongari char zoneid[8]; 133228325Syongari char lowaddrid[20]; 134228325Syongari struct sysctl_ctx_list sysctl_tree; 135228325Syongari struct sysctl_oid *sysctl_tree_top; 136228325Syongari}; 137228325Syongari 138228325Syongaristatic struct mtx bounce_lock; 139228325Syongaristatic int total_bpages; 140228325Syongaristatic int busdma_zonecount; 141228325Syongaristatic uint32_t tags_total; 142228325Syongaristatic uint32_t maps_total; 143199548Syongaristatic uint32_t maps_dmamem; 144199548Syongaristatic uint32_t maps_coherent; 145199548Syongaristatic counter_u64_t maploads_total; 146199548Syongaristatic counter_u64_t maploads_bounced; 147179895Sdelphijstatic counter_u64_t maploads_coherent; 148179895Sdelphijstatic counter_u64_t maploads_dmamem; 149179895Sdelphijstatic counter_u64_t maploads_mbuf; 150179895Sdelphijstatic counter_u64_t maploads_physmem; 151199608Syongari 152179895Sdelphijstatic STAILQ_HEAD(, bounce_zone) bounce_zone_list; 153199548Syongari 154199548SyongariSYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 155199548SyongariSYSCTL_UINT(_hw_busdma, OID_AUTO, tags_total, CTLFLAG_RD, &tags_total, 0, 156179895Sdelphij "Number of active tags"); 157179895SdelphijSYSCTL_UINT(_hw_busdma, OID_AUTO, maps_total, CTLFLAG_RD, &maps_total, 0, 158179895Sdelphij "Number of active maps"); 159179895SdelphijSYSCTL_UINT(_hw_busdma, OID_AUTO, maps_dmamem, CTLFLAG_RD, &maps_dmamem, 0, 160179895Sdelphij "Number of active maps for bus_dmamem_alloc buffers"); 161179895SdelphijSYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0, 162179895Sdelphij "Number of active maps with BUS_DMA_COHERENT flag set"); 163179895SdelphijSYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, 164179895Sdelphij &maploads_total, "Number of load operations performed"); 165179895SdelphijSYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD, 166179895Sdelphij &maploads_bounced, "Number of load operations that used bounce buffers"); 167179895SdelphijSYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_coherent, CTLFLAG_RD, 168179895Sdelphij &maploads_dmamem, "Number of load operations on BUS_DMA_COHERENT memory"); 169179895SdelphijSYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_dmamem, CTLFLAG_RD, 170179895Sdelphij &maploads_dmamem, "Number of load operations on bus_dmamem_alloc buffers"); 171179895SdelphijSYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_mbuf, CTLFLAG_RD, 172179895Sdelphij &maploads_mbuf, "Number of load operations for mbufs"); 173179895SdelphijSYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_physmem, CTLFLAG_RD, 174179895Sdelphij &maploads_physmem, "Number of load operations on physical buffers"); 175179895SdelphijSYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 176179895Sdelphij "Total bounce pages"); 177179895Sdelphij 178179895Sdelphijstruct bus_dmamap { 179179895Sdelphij struct bp_list bpages; 180179895Sdelphij int pagesneeded; 181179895Sdelphij int pagesreserved; 182179895Sdelphij bus_dma_tag_t dmat; 183179895Sdelphij struct memdesc mem; 184179895Sdelphij pmap_t pmap; 185179895Sdelphij bus_dmamap_callback_t *callback; 186179895Sdelphij void *callback_arg; 187179895Sdelphij int flags; 188179895Sdelphij#define DMAMAP_COHERENT (1 << 0) 189179895Sdelphij#define DMAMAP_DMAMEM_ALLOC (1 << 1) 190179895Sdelphij#define DMAMAP_MBUF (1 << 2) 191179895Sdelphij STAILQ_ENTRY(bus_dmamap) links; 192179895Sdelphij bus_dma_segment_t *segments; 193179895Sdelphij int sync_count; 194179895Sdelphij struct sync_list slist[]; 195179895Sdelphij}; 196179895Sdelphij 197179895Sdelphijstatic STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 198179895Sdelphijstatic STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 199179895Sdelphij 200179895Sdelphijstatic void init_bounce_pages(void *dummy); 201179895Sdelphijstatic int alloc_bounce_zone(bus_dma_tag_t dmat); 202179895Sdelphijstatic int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 203179895Sdelphijstatic int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 204179895Sdelphij int commit); 205179895Sdelphijstatic bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 206179895Sdelphij vm_offset_t vaddr, bus_addr_t addr, 207179895Sdelphij bus_size_t size); 208179895Sdelphijstatic void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 209179895Sdelphijstatic void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 210179895Sdelphij void *buf, bus_size_t buflen, int flags); 211179895Sdelphijstatic void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 212179895Sdelphij vm_paddr_t buf, bus_size_t buflen, int flags); 213179895Sdelphijstatic int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 214179895Sdelphij int flags); 215179895Sdelphij 216179895Sdelphijstatic busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 217179895Sdelphijstatic busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 218179895Sdelphijstatic void 219179895Sdelphijbusdma_init(void *dummy) 220179895Sdelphij{ 221179895Sdelphij int uma_flags; 222179895Sdelphij 223179895Sdelphij maploads_total = counter_u64_alloc(M_WAITOK); 224179895Sdelphij maploads_bounced = counter_u64_alloc(M_WAITOK); 225179895Sdelphij maploads_coherent = counter_u64_alloc(M_WAITOK); 226179895Sdelphij maploads_dmamem = counter_u64_alloc(M_WAITOK); 227179895Sdelphij maploads_mbuf = counter_u64_alloc(M_WAITOK); 228179895Sdelphij maploads_physmem = counter_u64_alloc(M_WAITOK); 229179895Sdelphij 230228325Syongari uma_flags = 0; 231228325Syongari 232179895Sdelphij /* Create a cache of buffers in standard (cacheable) memory. */ 233179895Sdelphij standard_allocator = busdma_bufalloc_create("buffer", 234228332Syongari arm_dcache_align, /* minimum_alignment */ 235228332Syongari NULL, /* uma_alloc func */ 236228332Syongari NULL, /* uma_free func */ 237228332Syongari uma_flags); /* uma_zcreate_flags */ 238228332Syongari 239228332Syongari#ifdef INVARIANTS 240228332Syongari /* 241228332Syongari * Force UMA zone to allocate service structures like 242228332Syongari * slabs using own allocator. uma_debug code performs 243228332Syongari * atomic ops on uma_slab_t fields and safety of this 244228332Syongari * operation is not guaranteed for write-back caches 245228332Syongari */ 246228332Syongari uma_flags = UMA_ZONE_OFFPAGE; 247228332Syongari#endif 248228332Syongari /* 249228332Syongari * Create a cache of buffers in uncacheable memory, to implement the 250228332Syongari * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 251228332Syongari */ 252228332Syongari coherent_allocator = busdma_bufalloc_create("coherent", 253228332Syongari arm_dcache_align, /* minimum_alignment */ 254228332Syongari busdma_bufalloc_alloc_uncacheable, 255228332Syongari busdma_bufalloc_free_uncacheable, 256228332Syongari uma_flags); /* uma_zcreate_flags */ 257228332Syongari} 258228332Syongari 259228332Syongari/* 260228332Syongari * This init historically used SI_SUB_VM, but now the init code requires 261228332Syongari * malloc(9) using M_DEVBUF memory and the pcpu zones for counter(9), which get 262228332Syongari * set up by SI_SUB_KMEM and SI_ORDER_LAST, so we'll go right after that by 263228332Syongari * using SI_SUB_KMEM+1. 264228332Syongari */ 265228332SyongariSYSINIT(busdma, SI_SUB_KMEM+1, SI_ORDER_FIRST, busdma_init, NULL); 266228332Syongari 267228332Syongari/* 268228332Syongari * This routine checks the exclusion zone constraints from a tag against the 269228332Syongari * physical RAM available on the machine. If a tag specifies an exclusion zone 270228332Syongari * but there's no RAM in that zone, then we avoid allocating resources to bounce 271228332Syongari * a request, and we can use any memory allocator (as opposed to needing 272228332Syongari * kmem_alloc_contig() just because it can allocate pages in an address range). 273228332Syongari * 274228332Syongari * Most tags have BUS_SPACE_MAXADDR or BUS_SPACE_MAXADDR_32BIT (they are the 275228332Syongari * same value on 32-bit architectures) as their lowaddr constraint, and we can't 276228332Syongari * possibly have RAM at an address higher than the highest address we can 277228332Syongari * express, so we take a fast out. 278228332Syongari */ 279228332Syongaristatic int 280228332Syongariexclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr) 281228332Syongari{ 282228332Syongari int i; 283228332Syongari 284179895Sdelphij if (lowaddr >= BUS_SPACE_MAXADDR) 285179895Sdelphij return (0); 286179895Sdelphij 287179895Sdelphij for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 288179895Sdelphij if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) || 289179895Sdelphij (lowaddr < phys_avail[i] && highaddr >= phys_avail[i])) 290179895Sdelphij return (1); 291179895Sdelphij } 292179895Sdelphij return (0); 293179895Sdelphij} 294179895Sdelphij 295179895Sdelphij/* 296199552Syongari * Return true if the tag has an exclusion zone that could lead to bouncing. 297179895Sdelphij */ 298179895Sdelphijstatic __inline int 299179895Sdelphijexclusion_bounce(bus_dma_tag_t dmat) 300179895Sdelphij{ 301179895Sdelphij 302179895Sdelphij return (dmat->flags & BUS_DMA_EXCL_BOUNCE); 303179895Sdelphij} 304179895Sdelphij 305179895Sdelphij/* 306179895Sdelphij * Return true if the given address does not fall on the alignment boundary. 307179895Sdelphij */ 308179895Sdelphijstatic __inline int 309179895Sdelphijalignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr) 310179895Sdelphij{ 311179895Sdelphij 312179895Sdelphij return (addr & (dmat->alignment - 1)); 313179895Sdelphij} 314179895Sdelphij 315179895Sdelphij/* 316228325Syongari * Return true if the DMA should bounce because the start or end does not fall 317228325Syongari * on a cacheline boundary (which would require a partial cacheline flush). 318228325Syongari * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by 319228325Syongari * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a 320228325Syongari * strict rule that such memory cannot be accessed by the CPU while DMA is in 321179895Sdelphij * progress (or by multiple DMA engines at once), so that it's always safe to do 322179895Sdelphij * full cacheline flushes even if that affects memory outside the range of a 323179895Sdelphij * given DMA operation that doesn't involve the full allocated buffer. If we're 324228332Syongari * mapping an mbuf, that follows the same rules as a buffer we allocated. 325179895Sdelphij */ 326179895Sdelphijstatic __inline int 327179895Sdelphijcacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size) 328179895Sdelphij{ 329179895Sdelphij 330179895Sdelphij if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF)) 331179895Sdelphij return (0); 332179895Sdelphij return ((addr | size) & arm_dcache_align_mask); 333179895Sdelphij} 334179895Sdelphij 335179895Sdelphij/* 336179895Sdelphij * Return true if we might need to bounce the DMA described by addr and size. 337179895Sdelphij * 338179895Sdelphij * This is used to quick-check whether we need to do the more expensive work of 339179895Sdelphij * checking the DMA page-by-page looking for alignment and exclusion bounces. 340179895Sdelphij * 341199552Syongari * Note that the addr argument might be either virtual or physical. It doesn't 342199552Syongari * matter because we only look at the low-order bits, which are the same in both 343228331Syongari * address spaces. 344199552Syongari */ 345199552Syongaristatic __inline int 346228331Syongarimight_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr, 347179895Sdelphij bus_size_t size) 348179895Sdelphij{ 349 return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) || 350 alignment_bounce(dmat, addr) || 351 cacheline_bounce(map, addr, size)); 352} 353 354/* 355 * Return true if we must bounce the DMA described by paddr and size. 356 * 357 * Bouncing can be triggered by DMA that doesn't begin and end on cacheline 358 * boundaries, or doesn't begin on an alignment boundary, or falls within the 359 * exclusion zone of any tag in the ancestry chain. 360 * 361 * For exclusions, walk the chain of tags comparing paddr to the exclusion zone 362 * within each tag. If the tag has a filter function, use it to decide whether 363 * the DMA needs to bounce, otherwise any DMA within the zone bounces. 364 */ 365static int 366must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, 367 bus_size_t size) 368{ 369 370 if (cacheline_bounce(map, paddr, size)) 371 return (1); 372 373 /* 374 * The tag already contains ancestors' alignment restrictions so this 375 * check doesn't need to be inside the loop. 376 */ 377 if (alignment_bounce(dmat, paddr)) 378 return (1); 379 380 /* 381 * Even though each tag has an exclusion zone that is a superset of its 382 * own and all its ancestors' exclusions, the exclusion zone of each tag 383 * up the chain must be checked within the loop, because the busdma 384 * rules say the filter function is called only when the address lies 385 * within the low-highaddr range of the tag that filterfunc belongs to. 386 */ 387 while (dmat != NULL && exclusion_bounce(dmat)) { 388 if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) && 389 (dmat->filter == NULL || 390 dmat->filter(dmat->filterarg, paddr) != 0)) 391 return (1); 392 dmat = dmat->parent; 393 } 394 395 return (0); 396} 397 398static __inline struct arm32_dma_range * 399_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 400 bus_addr_t curaddr) 401{ 402 struct arm32_dma_range *dr; 403 int i; 404 405 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 406 if (curaddr >= dr->dr_sysbase && 407 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 408 return (dr); 409 } 410 411 return (NULL); 412} 413 414/* 415 * Convenience function for manipulating driver locks from busdma (during 416 * busdma_swi, for example). Drivers that don't provide their own locks 417 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 418 * non-mutex locking scheme don't have to use this at all. 419 */ 420void 421busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 422{ 423 struct mtx *dmtx; 424 425 dmtx = (struct mtx *)arg; 426 switch (op) { 427 case BUS_DMA_LOCK: 428 mtx_lock(dmtx); 429 break; 430 case BUS_DMA_UNLOCK: 431 mtx_unlock(dmtx); 432 break; 433 default: 434 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 435 } 436} 437 438/* 439 * dflt_lock should never get called. It gets put into the dma tag when 440 * lockfunc == NULL, which is only valid if the maps that are associated 441 * with the tag are meant to never be defered. 442 * XXX Should have a way to identify which driver is responsible here. 443 */ 444static void 445dflt_lock(void *arg, bus_dma_lock_op_t op) 446{ 447 panic("driver error: busdma dflt_lock called"); 448} 449 450/* 451 * Allocate a device specific dma_tag. 452 */ 453int 454bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 455 bus_size_t boundary, bus_addr_t lowaddr, 456 bus_addr_t highaddr, bus_dma_filter_t *filter, 457 void *filterarg, bus_size_t maxsize, int nsegments, 458 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 459 void *lockfuncarg, bus_dma_tag_t *dmat) 460{ 461 bus_dma_tag_t newtag; 462 int error = 0; 463 464#if 0 465 if (!parent) 466 parent = arm_root_dma_tag; 467#endif 468 469 /* Basic sanity checking */ 470 if (boundary != 0 && boundary < maxsegsz) 471 maxsegsz = boundary; 472 473 /* Return a NULL tag on failure */ 474 *dmat = NULL; 475 476 if (maxsegsz == 0) { 477 return (EINVAL); 478 } 479 480 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 481 M_ZERO | M_NOWAIT); 482 if (newtag == NULL) { 483 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 484 __func__, newtag, 0, error); 485 return (ENOMEM); 486 } 487 488 newtag->parent = parent; 489 newtag->alignment = alignment; 490 newtag->boundary = boundary; 491 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 492 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 493 (PAGE_SIZE - 1); 494 newtag->filter = filter; 495 newtag->filterarg = filterarg; 496 newtag->maxsize = maxsize; 497 newtag->nsegments = nsegments; 498 newtag->maxsegsz = maxsegsz; 499 newtag->flags = flags; 500 newtag->ref_count = 1; /* Count ourself */ 501 newtag->map_count = 0; 502 newtag->ranges = bus_dma_get_range(); 503 newtag->_nranges = bus_dma_get_range_nb(); 504 if (lockfunc != NULL) { 505 newtag->lockfunc = lockfunc; 506 newtag->lockfuncarg = lockfuncarg; 507 } else { 508 newtag->lockfunc = dflt_lock; 509 newtag->lockfuncarg = NULL; 510 } 511 512 /* Take into account any restrictions imposed by our parent tag */ 513 if (parent != NULL) { 514 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 515 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 516 newtag->alignment = MAX(parent->alignment, newtag->alignment); 517 newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE; 518 if (newtag->boundary == 0) 519 newtag->boundary = parent->boundary; 520 else if (parent->boundary != 0) 521 newtag->boundary = MIN(parent->boundary, 522 newtag->boundary); 523 if (newtag->filter == NULL) { 524 /* 525 * Short circuit to looking at our parent directly 526 * since we have encapsulated all of its information 527 */ 528 newtag->filter = parent->filter; 529 newtag->filterarg = parent->filterarg; 530 newtag->parent = parent->parent; 531 } 532 if (newtag->parent != NULL) 533 atomic_add_int(&parent->ref_count, 1); 534 } 535 536 if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr)) 537 newtag->flags |= BUS_DMA_EXCL_BOUNCE; 538 if (alignment_bounce(newtag, 1)) 539 newtag->flags |= BUS_DMA_ALIGN_BOUNCE; 540 541 /* 542 * Any request can auto-bounce due to cacheline alignment, in addition 543 * to any alignment or boundary specifications in the tag, so if the 544 * ALLOCNOW flag is set, there's always work to do. 545 */ 546 if ((flags & BUS_DMA_ALLOCNOW) != 0) { 547 struct bounce_zone *bz; 548 /* 549 * Round size up to a full page, and add one more page because 550 * there can always be one more boundary crossing than the 551 * number of pages in a transfer. 552 */ 553 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 554 555 if ((error = alloc_bounce_zone(newtag)) != 0) { 556 free(newtag, M_DEVBUF); 557 return (error); 558 } 559 bz = newtag->bounce_zone; 560 561 if (ptoa(bz->total_bpages) < maxsize) { 562 int pages; 563 564 pages = atop(maxsize) - bz->total_bpages; 565 566 /* Add pages to our bounce pool */ 567 if (alloc_bounce_pages(newtag, pages) < pages) 568 error = ENOMEM; 569 } 570 /* Performed initial allocation */ 571 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 572 } else 573 newtag->bounce_zone = NULL; 574 575 if (error != 0) { 576 free(newtag, M_DEVBUF); 577 } else { 578 atomic_add_32(&tags_total, 1); 579 *dmat = newtag; 580 } 581 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 582 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 583 return (error); 584} 585 586int 587bus_dma_tag_destroy(bus_dma_tag_t dmat) 588{ 589 bus_dma_tag_t dmat_copy; 590 int error; 591 592 error = 0; 593 dmat_copy = dmat; 594 595 if (dmat != NULL) { 596 597 if (dmat->map_count != 0) { 598 error = EBUSY; 599 goto out; 600 } 601 602 while (dmat != NULL) { 603 bus_dma_tag_t parent; 604 605 parent = dmat->parent; 606 atomic_subtract_int(&dmat->ref_count, 1); 607 if (dmat->ref_count == 0) { 608 atomic_subtract_32(&tags_total, 1); 609 free(dmat, M_DEVBUF); 610 /* 611 * Last reference count, so 612 * release our reference 613 * count on our parent. 614 */ 615 dmat = parent; 616 } else 617 dmat = NULL; 618 } 619 } 620out: 621 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 622 return (error); 623} 624 625static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 626{ 627 struct bounce_zone *bz; 628 int maxpages; 629 int error; 630 631 if (dmat->bounce_zone == NULL) 632 if ((error = alloc_bounce_zone(dmat)) != 0) 633 return (error); 634 bz = dmat->bounce_zone; 635 /* Initialize the new map */ 636 STAILQ_INIT(&(mapp->bpages)); 637 638 /* 639 * Attempt to add pages to our pool on a per-instance basis up to a sane 640 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 641 * alignment and boundary constraints, it could still auto-bounce due to 642 * cacheline alignment, which requires at most two bounce pages. 643 */ 644 if (dmat->flags & BUS_DMA_COULD_BOUNCE) 645 maxpages = MAX_BPAGES; 646 else 647 maxpages = 2 * bz->map_count; 648 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 || 649 (bz->map_count > 0 && bz->total_bpages < maxpages)) { 650 int pages; 651 652 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 653 pages = MIN(maxpages - bz->total_bpages, pages); 654 pages = MAX(pages, 2); 655 if (alloc_bounce_pages(dmat, pages) < pages) 656 return (ENOMEM); 657 658 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 659 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 660 } 661 bz->map_count++; 662 return (0); 663} 664 665static bus_dmamap_t 666allocate_map(bus_dma_tag_t dmat, int mflags) 667{ 668 int mapsize, segsize; 669 bus_dmamap_t map; 670 671 /* 672 * Allocate the map. The map structure ends with an embedded 673 * variable-sized array of sync_list structures. Following that 674 * we allocate enough extra space to hold the array of bus_dma_segments. 675 */ 676 KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS, 677 ("cannot allocate %u dma segments (max is %u)", 678 dmat->nsegments, MAX_DMA_SEGMENTS)); 679 segsize = sizeof(struct bus_dma_segment) * dmat->nsegments; 680 mapsize = sizeof(*map) + sizeof(struct sync_list) * dmat->nsegments; 681 map = malloc(mapsize + segsize, M_DEVBUF, mflags | M_ZERO); 682 if (map == NULL) { 683 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 684 return (NULL); 685 } 686 map->segments = (bus_dma_segment_t *)((uintptr_t)map + mapsize); 687 return (map); 688} 689 690/* 691 * Allocate a handle for mapping from kva/uva/physical 692 * address space into bus device space. 693 */ 694int 695bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 696{ 697 bus_dmamap_t map; 698 int error = 0; 699 700 *mapp = map = allocate_map(dmat, M_NOWAIT); 701 if (map == NULL) { 702 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 703 return (ENOMEM); 704 } 705 706 /* 707 * Bouncing might be required if the driver asks for an exclusion 708 * region, a data alignment that is stricter than 1, or DMA that begins 709 * or ends with a partial cacheline. Whether bouncing will actually 710 * happen can't be known until mapping time, but we need to pre-allocate 711 * resources now because we might not be allowed to at mapping time. 712 */ 713 error = allocate_bz_and_pages(dmat, map); 714 if (error != 0) { 715 free(map, M_DEVBUF); 716 *mapp = NULL; 717 return (error); 718 } 719 if (map->flags & DMAMAP_COHERENT) 720 atomic_add_32(&maps_coherent, 1); 721 atomic_add_32(&maps_total, 1); 722 dmat->map_count++; 723 724 return (0); 725} 726 727/* 728 * Destroy a handle for mapping from kva/uva/physical 729 * address space into bus device space. 730 */ 731int 732bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 733{ 734 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 735 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 736 __func__, dmat, EBUSY); 737 return (EBUSY); 738 } 739 if (dmat->bounce_zone) 740 dmat->bounce_zone->map_count--; 741 if (map->flags & DMAMAP_COHERENT) 742 atomic_subtract_32(&maps_coherent, 1); 743 atomic_subtract_32(&maps_total, 1); 744 free(map, M_DEVBUF); 745 dmat->map_count--; 746 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 747 return (0); 748} 749 750 751/* 752 * Allocate a piece of memory that can be efficiently mapped into 753 * bus device space based on the constraints lited in the dma tag. 754 * A dmamap to for use with dmamap_load is also allocated. 755 */ 756int 757bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 758 bus_dmamap_t *mapp) 759{ 760 busdma_bufalloc_t ba; 761 struct busdma_bufzone *bufzone; 762 bus_dmamap_t map; 763 vm_memattr_t memattr; 764 int mflags; 765 766 if (flags & BUS_DMA_NOWAIT) 767 mflags = M_NOWAIT; 768 else 769 mflags = M_WAITOK; 770 if (flags & BUS_DMA_ZERO) 771 mflags |= M_ZERO; 772 773 *mapp = map = allocate_map(dmat, mflags); 774 if (map == NULL) { 775 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 776 __func__, dmat, dmat->flags, ENOMEM); 777 return (ENOMEM); 778 } 779 map->flags = DMAMAP_DMAMEM_ALLOC; 780 781 /* Choose a busdma buffer allocator based on memory type flags. */ 782 if (flags & BUS_DMA_COHERENT) { 783 memattr = VM_MEMATTR_UNCACHEABLE; 784 ba = coherent_allocator; 785 map->flags |= DMAMAP_COHERENT; 786 } else { 787 memattr = VM_MEMATTR_DEFAULT; 788 ba = standard_allocator; 789 } 790 791 /* 792 * Try to find a bufzone in the allocator that holds a cache of buffers 793 * of the right size for this request. If the buffer is too big to be 794 * held in the allocator cache, this returns NULL. 795 */ 796 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 797 798 /* 799 * Allocate the buffer from the uma(9) allocator if... 800 * - It's small enough to be in the allocator (bufzone not NULL). 801 * - The alignment constraint isn't larger than the allocation size 802 * (the allocator aligns buffers to their size boundaries). 803 * - There's no need to handle lowaddr/highaddr exclusion zones. 804 * else allocate non-contiguous pages if... 805 * - The page count that could get allocated doesn't exceed nsegments. 806 * - The alignment constraint isn't larger than a page boundary. 807 * - There are no boundary-crossing constraints. 808 * else allocate a block of contiguous pages because one or more of the 809 * constraints is something that only the contig allocator can fulfill. 810 */ 811 if (bufzone != NULL && dmat->alignment <= bufzone->size && 812 !exclusion_bounce(dmat)) { 813 *vaddr = uma_zalloc(bufzone->umazone, mflags); 814 } else if (dmat->nsegments >= btoc(dmat->maxsize) && 815 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 816 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 817 mflags, 0, dmat->lowaddr, memattr); 818 } else { 819 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 820 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 821 memattr); 822 } 823 824 825 if (*vaddr == NULL) { 826 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 827 __func__, dmat, dmat->flags, ENOMEM); 828 free(map, M_DEVBUF); 829 *mapp = NULL; 830 return (ENOMEM); 831 } 832 if (map->flags & DMAMAP_COHERENT) 833 atomic_add_32(&maps_coherent, 1); 834 atomic_add_32(&maps_dmamem, 1); 835 atomic_add_32(&maps_total, 1); 836 dmat->map_count++; 837 838 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 839 __func__, dmat, dmat->flags, 0); 840 return (0); 841} 842 843/* 844 * Free a piece of memory and it's allociated dmamap, that was allocated 845 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 846 */ 847void 848bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 849{ 850 struct busdma_bufzone *bufzone; 851 busdma_bufalloc_t ba; 852 853 if (map->flags & DMAMAP_COHERENT) 854 ba = coherent_allocator; 855 else 856 ba = standard_allocator; 857 858 /* Be careful not to access map from here on. */ 859 860 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 861 862 if (bufzone != NULL && dmat->alignment <= bufzone->size && 863 !exclusion_bounce(dmat)) 864 uma_zfree(bufzone->umazone, vaddr); 865 else 866 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 867 868 dmat->map_count--; 869 if (map->flags & DMAMAP_COHERENT) 870 atomic_subtract_32(&maps_coherent, 1); 871 atomic_subtract_32(&maps_total, 1); 872 atomic_subtract_32(&maps_dmamem, 1); 873 free(map, M_DEVBUF); 874 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 875} 876 877static void 878_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 879 bus_size_t buflen, int flags) 880{ 881 bus_addr_t curaddr; 882 bus_size_t sgsize; 883 884 if (map->pagesneeded == 0) { 885 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 886 " map= %p, pagesneeded= %d", 887 dmat->lowaddr, dmat->boundary, dmat->alignment, 888 map, map->pagesneeded); 889 /* 890 * Count the number of bounce pages 891 * needed in order to complete this transfer 892 */ 893 curaddr = buf; 894 while (buflen != 0) { 895 sgsize = MIN(buflen, dmat->maxsegsz); 896 if (must_bounce(dmat, map, curaddr, sgsize) != 0) { 897 sgsize = MIN(sgsize, PAGE_SIZE); 898 map->pagesneeded++; 899 } 900 curaddr += sgsize; 901 buflen -= sgsize; 902 } 903 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 904 } 905} 906 907static void 908_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 909 void *buf, bus_size_t buflen, int flags) 910{ 911 vm_offset_t vaddr; 912 vm_offset_t vendaddr; 913 bus_addr_t paddr; 914 915 if (map->pagesneeded == 0) { 916 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 917 " map= %p, pagesneeded= %d", 918 dmat->lowaddr, dmat->boundary, dmat->alignment, 919 map, map->pagesneeded); 920 /* 921 * Count the number of bounce pages 922 * needed in order to complete this transfer 923 */ 924 vaddr = (vm_offset_t)buf; 925 vendaddr = (vm_offset_t)buf + buflen; 926 927 while (vaddr < vendaddr) { 928 if (__predict_true(map->pmap == kernel_pmap)) 929 paddr = pmap_kextract(vaddr); 930 else 931 paddr = pmap_extract(map->pmap, vaddr); 932 if (must_bounce(dmat, map, paddr, 933 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr & 934 PAGE_MASK)))) != 0) { 935 map->pagesneeded++; 936 } 937 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 938 939 } 940 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 941 } 942} 943 944static int 945_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 946{ 947 948 /* Reserve Necessary Bounce Pages */ 949 mtx_lock(&bounce_lock); 950 if (flags & BUS_DMA_NOWAIT) { 951 if (reserve_bounce_pages(dmat, map, 0) != 0) { 952 map->pagesneeded = 0; 953 mtx_unlock(&bounce_lock); 954 return (ENOMEM); 955 } 956 } else { 957 if (reserve_bounce_pages(dmat, map, 1) != 0) { 958 /* Queue us for resources */ 959 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 960 mtx_unlock(&bounce_lock); 961 return (EINPROGRESS); 962 } 963 } 964 mtx_unlock(&bounce_lock); 965 966 return (0); 967} 968 969/* 970 * Add a single contiguous physical range to the segment list. 971 */ 972static int 973_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 974 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 975{ 976 bus_addr_t baddr, bmask; 977 int seg; 978 979 /* 980 * Make sure we don't cross any boundaries. 981 */ 982 bmask = ~(dmat->boundary - 1); 983 if (dmat->boundary > 0) { 984 baddr = (curaddr + dmat->boundary) & bmask; 985 if (sgsize > (baddr - curaddr)) 986 sgsize = (baddr - curaddr); 987 } 988 989 if (dmat->ranges) { 990 struct arm32_dma_range *dr; 991 992 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 993 curaddr); 994 if (dr == NULL) { 995 _bus_dmamap_unload(dmat, map); 996 return (0); 997 } 998 /* 999 * In a valid DMA range. Translate the physical 1000 * memory address to an address in the DMA window. 1001 */ 1002 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 1003 } 1004 1005 /* 1006 * Insert chunk into a segment, coalescing with 1007 * previous segment if possible. 1008 */ 1009 seg = *segp; 1010 if (seg == -1) { 1011 seg = 0; 1012 segs[seg].ds_addr = curaddr; 1013 segs[seg].ds_len = sgsize; 1014 } else { 1015 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 1016 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 1017 (dmat->boundary == 0 || 1018 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 1019 segs[seg].ds_len += sgsize; 1020 else { 1021 if (++seg >= dmat->nsegments) 1022 return (0); 1023 segs[seg].ds_addr = curaddr; 1024 segs[seg].ds_len = sgsize; 1025 } 1026 } 1027 *segp = seg; 1028 return (sgsize); 1029} 1030 1031/* 1032 * Utility function to load a physical buffer. segp contains 1033 * the starting segment on entrace, and the ending segment on exit. 1034 */ 1035int 1036_bus_dmamap_load_phys(bus_dma_tag_t dmat, 1037 bus_dmamap_t map, 1038 vm_paddr_t buf, bus_size_t buflen, 1039 int flags, 1040 bus_dma_segment_t *segs, 1041 int *segp) 1042{ 1043 bus_addr_t curaddr; 1044 bus_size_t sgsize; 1045 int error; 1046 1047 if (segs == NULL) 1048 segs = map->segments; 1049 1050 counter_u64_add(maploads_total, 1); 1051 counter_u64_add(maploads_physmem, 1); 1052 1053 if (might_bounce(dmat, map, buflen, buflen)) { 1054 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 1055 if (map->pagesneeded != 0) { 1056 counter_u64_add(maploads_bounced, 1); 1057 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1058 if (error) 1059 return (error); 1060 } 1061 } 1062 1063 while (buflen > 0) { 1064 curaddr = buf; 1065 sgsize = MIN(buflen, dmat->maxsegsz); 1066 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1067 sgsize)) { 1068 sgsize = MIN(sgsize, PAGE_SIZE); 1069 curaddr = add_bounce_page(dmat, map, 0, curaddr, 1070 sgsize); 1071 } 1072 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1073 segp); 1074 if (sgsize == 0) 1075 break; 1076 buf += sgsize; 1077 buflen -= sgsize; 1078 } 1079 1080 /* 1081 * Did we fit? 1082 */ 1083 if (buflen != 0) { 1084 _bus_dmamap_unload(dmat, map); 1085 return (EFBIG); /* XXX better return value here? */ 1086 } 1087 return (0); 1088} 1089 1090int 1091_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 1092 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 1093 bus_dma_segment_t *segs, int *segp) 1094{ 1095 1096 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 1097 segs, segp)); 1098} 1099 1100/* 1101 * Utility function to load a linear buffer. segp contains 1102 * the starting segment on entrace, and the ending segment on exit. 1103 */ 1104int 1105_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1106 bus_dmamap_t map, 1107 void *buf, bus_size_t buflen, 1108 pmap_t pmap, 1109 int flags, 1110 bus_dma_segment_t *segs, 1111 int *segp) 1112{ 1113 bus_size_t sgsize; 1114 bus_addr_t curaddr; 1115 vm_offset_t vaddr; 1116 struct sync_list *sl; 1117 int error; 1118 1119 counter_u64_add(maploads_total, 1); 1120 if (map->flags & DMAMAP_COHERENT) 1121 counter_u64_add(maploads_coherent, 1); 1122 if (map->flags & DMAMAP_DMAMEM_ALLOC) 1123 counter_u64_add(maploads_dmamem, 1); 1124 1125 if (segs == NULL) 1126 segs = map->segments; 1127 1128 if (flags & BUS_DMA_LOAD_MBUF) { 1129 counter_u64_add(maploads_mbuf, 1); 1130 map->flags |= DMAMAP_MBUF; 1131 } 1132 1133 map->pmap = pmap; 1134 1135 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) { 1136 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1137 if (map->pagesneeded != 0) { 1138 counter_u64_add(maploads_bounced, 1); 1139 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1140 if (error) 1141 return (error); 1142 } 1143 } 1144 1145 sl = NULL; 1146 vaddr = (vm_offset_t)buf; 1147 1148 while (buflen > 0) { 1149 /* 1150 * Get the physical address for this segment. 1151 */ 1152 if (__predict_true(map->pmap == kernel_pmap)) 1153 curaddr = pmap_kextract(vaddr); 1154 else 1155 curaddr = pmap_extract(map->pmap, vaddr); 1156 1157 /* 1158 * Compute the segment size, and adjust counts. 1159 */ 1160 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1161 if (sgsize > dmat->maxsegsz) 1162 sgsize = dmat->maxsegsz; 1163 if (buflen < sgsize) 1164 sgsize = buflen; 1165 1166 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1167 sgsize)) { 1168 curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1169 sgsize); 1170 } else { 1171 sl = &map->slist[map->sync_count - 1]; 1172 if (map->sync_count == 0 || 1173#ifdef ARM_L2_PIPT 1174 curaddr != sl->busaddr + sl->datacount || 1175#endif 1176 vaddr != sl->vaddr + sl->datacount) { 1177 if (++map->sync_count > dmat->nsegments) 1178 goto cleanup; 1179 sl++; 1180 sl->vaddr = vaddr; 1181 sl->datacount = sgsize; 1182 sl->busaddr = curaddr; 1183 } else 1184 sl->datacount += sgsize; 1185 } 1186 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1187 segp); 1188 if (sgsize == 0) 1189 break; 1190 vaddr += sgsize; 1191 buflen -= sgsize; 1192 } 1193 1194cleanup: 1195 /* 1196 * Did we fit? 1197 */ 1198 if (buflen != 0) { 1199 _bus_dmamap_unload(dmat, map); 1200 return (EFBIG); /* XXX better return value here? */ 1201 } 1202 return (0); 1203} 1204 1205 1206void 1207__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1208 struct memdesc *mem, bus_dmamap_callback_t *callback, 1209 void *callback_arg) 1210{ 1211 1212 map->mem = *mem; 1213 map->dmat = dmat; 1214 map->callback = callback; 1215 map->callback_arg = callback_arg; 1216} 1217 1218bus_dma_segment_t * 1219_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1220 bus_dma_segment_t *segs, int nsegs, int error) 1221{ 1222 1223 if (segs == NULL) 1224 segs = map->segments; 1225 return (segs); 1226} 1227 1228/* 1229 * Release the mapping held by map. 1230 */ 1231void 1232_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1233{ 1234 struct bounce_page *bpage; 1235 struct bounce_zone *bz; 1236 1237 if ((bz = dmat->bounce_zone) != NULL) { 1238 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1239 STAILQ_REMOVE_HEAD(&map->bpages, links); 1240 free_bounce_page(dmat, bpage); 1241 } 1242 1243 bz = dmat->bounce_zone; 1244 bz->free_bpages += map->pagesreserved; 1245 bz->reserved_bpages -= map->pagesreserved; 1246 map->pagesreserved = 0; 1247 map->pagesneeded = 0; 1248 } 1249 map->sync_count = 0; 1250 map->flags &= ~DMAMAP_MBUF; 1251} 1252 1253#ifdef notyetbounceuser 1254 /* If busdma uses user pages, then the interrupt handler could 1255 * be use the kernel vm mapping. Both bounce pages and sync list 1256 * do not cross page boundaries. 1257 * Below is a rough sequence that a person would do to fix the 1258 * user page reference in the kernel vmspace. This would be 1259 * done in the dma post routine. 1260 */ 1261void 1262_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1263 pmap_t pmap, int op) 1264{ 1265 bus_size_t sgsize; 1266 bus_addr_t curaddr; 1267 vm_offset_t va; 1268 1269 /* each synclist entry is contained within a single page. 1270 * 1271 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1272 */ 1273 curaddr = pmap_extract(pmap, buf); 1274 va = pmap_dma_map(curaddr); 1275 switch (op) { 1276 case SYNC_USER_INV: 1277 cpu_dcache_wb_range(va, sgsize); 1278 break; 1279 1280 case SYNC_USER_COPYTO: 1281 bcopy((void *)va, (void *)bounce, sgsize); 1282 break; 1283 1284 case SYNC_USER_COPYFROM: 1285 bcopy((void *) bounce, (void *)va, sgsize); 1286 break; 1287 1288 default: 1289 break; 1290 } 1291 1292 pmap_dma_unmap(va); 1293} 1294#endif 1295 1296#ifdef ARM_L2_PIPT 1297#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1298#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1299#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1300#else 1301#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1302#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1303#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1304#endif 1305 1306void 1307_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1308{ 1309 struct bounce_page *bpage; 1310 struct sync_list *sl, *end; 1311 /* 1312 * If the buffer was from user space, it is possible that this is not 1313 * the same vm map, especially on a POST operation. It's not clear that 1314 * dma on userland buffers can work at all right now, certainly not if a 1315 * partial cacheline flush has to be handled. To be safe, until we're 1316 * able to test direct userland dma, panic on a map mismatch. 1317 */ 1318 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1319 if (!pmap_dmap_iscurrent(map->pmap)) 1320 panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1321 /* Handle data bouncing. */ 1322 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1323 "performing bounce", __func__, dmat, dmat->flags, op); 1324 1325 if (op & BUS_DMASYNC_PREWRITE) { 1326 while (bpage != NULL) { 1327 if (bpage->datavaddr != 0) 1328 bcopy((void *)bpage->datavaddr, 1329 (void *)bpage->vaddr, 1330 bpage->datacount); 1331 else 1332 physcopyout(bpage->dataaddr, 1333 (void *)bpage->vaddr, 1334 bpage->datacount); 1335 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1336 bpage->datacount); 1337 l2cache_wb_range((vm_offset_t)bpage->vaddr, 1338 (vm_offset_t)bpage->busaddr, 1339 bpage->datacount); 1340 bpage = STAILQ_NEXT(bpage, links); 1341 } 1342 dmat->bounce_zone->total_bounced++; 1343 } 1344 1345 if (op & BUS_DMASYNC_PREREAD) { 1346 bpage = STAILQ_FIRST(&map->bpages); 1347 while (bpage != NULL) { 1348 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1349 bpage->datacount); 1350 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1351 (vm_offset_t)bpage->busaddr, 1352 bpage->datacount); 1353 bpage = STAILQ_NEXT(bpage, links); 1354 } 1355 } 1356 if (op & BUS_DMASYNC_POSTREAD) { 1357 while (bpage != NULL) { 1358 vm_offset_t startv; 1359 vm_paddr_t startp; 1360 int len; 1361 1362 startv = bpage->vaddr &~ arm_dcache_align_mask; 1363 startp = bpage->busaddr &~ arm_dcache_align_mask; 1364 len = bpage->datacount; 1365 1366 if (startv != bpage->vaddr) 1367 len += bpage->vaddr & arm_dcache_align_mask; 1368 if (len & arm_dcache_align_mask) 1369 len = (len - 1370 (len & arm_dcache_align_mask)) + 1371 arm_dcache_align; 1372 cpu_dcache_inv_range(startv, len); 1373 l2cache_inv_range(startv, startp, len); 1374 if (bpage->datavaddr != 0) 1375 bcopy((void *)bpage->vaddr, 1376 (void *)bpage->datavaddr, 1377 bpage->datacount); 1378 else 1379 physcopyin((void *)bpage->vaddr, 1380 bpage->dataaddr, 1381 bpage->datacount); 1382 bpage = STAILQ_NEXT(bpage, links); 1383 } 1384 dmat->bounce_zone->total_bounced++; 1385 } 1386 } 1387 if (map->flags & DMAMAP_COHERENT) 1388 return; 1389 1390 if (map->sync_count != 0) { 1391 if (!pmap_dmap_iscurrent(map->pmap)) 1392 panic("_bus_dmamap_sync: wrong user map for sync."); 1393 /* ARM caches are not self-snooping for dma */ 1394 1395 sl = &map->slist[0]; 1396 end = &map->slist[map->sync_count]; 1397 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1398 "performing sync", __func__, dmat, dmat->flags, op); 1399 1400 switch (op) { 1401 case BUS_DMASYNC_PREWRITE: 1402 while (sl != end) { 1403 cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1404 l2cache_wb_range(sl->vaddr, sl->busaddr, 1405 sl->datacount); 1406 sl++; 1407 } 1408 break; 1409 1410 case BUS_DMASYNC_PREREAD: 1411 while (sl != end) { 1412 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1413 l2cache_inv_range(sl->vaddr, sl->busaddr, 1414 sl->datacount); 1415 sl++; 1416 } 1417 break; 1418 1419 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1420 while (sl != end) { 1421 cpu_dcache_wbinv_range(sl->vaddr, sl->datacount); 1422 l2cache_wbinv_range(sl->vaddr, 1423 sl->busaddr, sl->datacount); 1424 sl++; 1425 } 1426 break; 1427 1428 case BUS_DMASYNC_POSTREAD: 1429 case BUS_DMASYNC_POSTWRITE: 1430 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1431 break; 1432 default: 1433 panic("unsupported combination of sync operations: 0x%08x\n", op); 1434 break; 1435 } 1436 } 1437} 1438 1439static void 1440init_bounce_pages(void *dummy __unused) 1441{ 1442 1443 total_bpages = 0; 1444 STAILQ_INIT(&bounce_zone_list); 1445 STAILQ_INIT(&bounce_map_waitinglist); 1446 STAILQ_INIT(&bounce_map_callbacklist); 1447 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1448} 1449SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1450 1451static struct sysctl_ctx_list * 1452busdma_sysctl_tree(struct bounce_zone *bz) 1453{ 1454 return (&bz->sysctl_tree); 1455} 1456 1457static struct sysctl_oid * 1458busdma_sysctl_tree_top(struct bounce_zone *bz) 1459{ 1460 return (bz->sysctl_tree_top); 1461} 1462 1463static int 1464alloc_bounce_zone(bus_dma_tag_t dmat) 1465{ 1466 struct bounce_zone *bz; 1467 1468 /* Check to see if we already have a suitable zone */ 1469 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1470 if ((dmat->alignment <= bz->alignment) && 1471 (dmat->lowaddr >= bz->lowaddr)) { 1472 dmat->bounce_zone = bz; 1473 return (0); 1474 } 1475 } 1476 1477 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1478 M_NOWAIT | M_ZERO)) == NULL) 1479 return (ENOMEM); 1480 1481 STAILQ_INIT(&bz->bounce_page_list); 1482 bz->free_bpages = 0; 1483 bz->reserved_bpages = 0; 1484 bz->active_bpages = 0; 1485 bz->lowaddr = dmat->lowaddr; 1486 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1487 bz->map_count = 0; 1488 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1489 busdma_zonecount++; 1490 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1491 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1492 dmat->bounce_zone = bz; 1493 1494 sysctl_ctx_init(&bz->sysctl_tree); 1495 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1496 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1497 CTLFLAG_RD, 0, ""); 1498 if (bz->sysctl_tree_top == NULL) { 1499 sysctl_ctx_free(&bz->sysctl_tree); 1500 return (0); /* XXX error code? */ 1501 } 1502 1503 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1504 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1505 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1506 "Total bounce pages"); 1507 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1508 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1509 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1510 "Free bounce pages"); 1511 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1512 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1513 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1514 "Reserved bounce pages"); 1515 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1516 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1517 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1518 "Active bounce pages"); 1519 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1520 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1521 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1522 "Total bounce requests (pages bounced)"); 1523 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1524 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1525 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1526 "Total bounce requests that were deferred"); 1527 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1528 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1529 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1530 SYSCTL_ADD_ULONG(busdma_sysctl_tree(bz), 1531 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1532 "alignment", CTLFLAG_RD, &bz->alignment, ""); 1533 1534 return (0); 1535} 1536 1537static int 1538alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1539{ 1540 struct bounce_zone *bz; 1541 int count; 1542 1543 bz = dmat->bounce_zone; 1544 count = 0; 1545 while (numpages > 0) { 1546 struct bounce_page *bpage; 1547 1548 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1549 M_NOWAIT | M_ZERO); 1550 1551 if (bpage == NULL) 1552 break; 1553 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1554 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0); 1555 if (bpage->vaddr == 0) { 1556 free(bpage, M_DEVBUF); 1557 break; 1558 } 1559 bpage->busaddr = pmap_kextract(bpage->vaddr); 1560 mtx_lock(&bounce_lock); 1561 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1562 total_bpages++; 1563 bz->total_bpages++; 1564 bz->free_bpages++; 1565 mtx_unlock(&bounce_lock); 1566 count++; 1567 numpages--; 1568 } 1569 return (count); 1570} 1571 1572static int 1573reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1574{ 1575 struct bounce_zone *bz; 1576 int pages; 1577 1578 mtx_assert(&bounce_lock, MA_OWNED); 1579 bz = dmat->bounce_zone; 1580 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1581 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1582 return (map->pagesneeded - (map->pagesreserved + pages)); 1583 bz->free_bpages -= pages; 1584 bz->reserved_bpages += pages; 1585 map->pagesreserved += pages; 1586 pages = map->pagesneeded - map->pagesreserved; 1587 1588 return (pages); 1589} 1590 1591static bus_addr_t 1592add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1593 bus_addr_t addr, bus_size_t size) 1594{ 1595 struct bounce_zone *bz; 1596 struct bounce_page *bpage; 1597 1598 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1599 KASSERT(map != NULL, 1600 ("add_bounce_page: bad map %p", map)); 1601 1602 bz = dmat->bounce_zone; 1603 if (map->pagesneeded == 0) 1604 panic("add_bounce_page: map doesn't need any pages"); 1605 map->pagesneeded--; 1606 1607 if (map->pagesreserved == 0) 1608 panic("add_bounce_page: map doesn't need any pages"); 1609 map->pagesreserved--; 1610 1611 mtx_lock(&bounce_lock); 1612 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1613 if (bpage == NULL) 1614 panic("add_bounce_page: free page list is empty"); 1615 1616 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1617 bz->reserved_bpages--; 1618 bz->active_bpages++; 1619 mtx_unlock(&bounce_lock); 1620 1621 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1622 /* Page offset needs to be preserved. */ 1623 bpage->vaddr |= vaddr & PAGE_MASK; 1624 bpage->busaddr |= vaddr & PAGE_MASK; 1625 } 1626 bpage->datavaddr = vaddr; 1627 bpage->dataaddr = addr; 1628 bpage->datacount = size; 1629 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1630 return (bpage->busaddr); 1631} 1632 1633static void 1634free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1635{ 1636 struct bus_dmamap *map; 1637 struct bounce_zone *bz; 1638 1639 bz = dmat->bounce_zone; 1640 bpage->datavaddr = 0; 1641 bpage->datacount = 0; 1642 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1643 /* 1644 * Reset the bounce page to start at offset 0. Other uses 1645 * of this bounce page may need to store a full page of 1646 * data and/or assume it starts on a page boundary. 1647 */ 1648 bpage->vaddr &= ~PAGE_MASK; 1649 bpage->busaddr &= ~PAGE_MASK; 1650 } 1651 1652 mtx_lock(&bounce_lock); 1653 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1654 bz->free_bpages++; 1655 bz->active_bpages--; 1656 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1657 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1658 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1659 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1660 map, links); 1661 busdma_swi_pending = 1; 1662 bz->total_deferred++; 1663 swi_sched(vm_ih, 0); 1664 } 1665 } 1666 mtx_unlock(&bounce_lock); 1667} 1668 1669void 1670busdma_swi(void) 1671{ 1672 bus_dma_tag_t dmat; 1673 struct bus_dmamap *map; 1674 1675 mtx_lock(&bounce_lock); 1676 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1677 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1678 mtx_unlock(&bounce_lock); 1679 dmat = map->dmat; 1680 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK); 1681 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1682 map->callback_arg, BUS_DMA_WAITOK); 1683 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1684 mtx_lock(&bounce_lock); 1685 } 1686 mtx_unlock(&bounce_lock); 1687} 1688