busdma_machdep-v6.c revision 269213
1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 269213 2014-07-29 02:36:50Z ian $"); 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43#include <sys/bus.h> 44#include <sys/busdma_bufalloc.h> 45#include <sys/interrupt.h> 46#include <sys/kernel.h> 47#include <sys/ktr.h> 48#include <sys/lock.h> 49#include <sys/memdesc.h> 50#include <sys/proc.h> 51#include <sys/mutex.h> 52#include <sys/sysctl.h> 53#include <sys/uio.h> 54 55#include <vm/vm.h> 56#include <vm/vm_page.h> 57#include <vm/vm_map.h> 58#include <vm/vm_extern.h> 59#include <vm/vm_kern.h> 60 61#include <machine/atomic.h> 62#include <machine/bus.h> 63#include <machine/cpufunc.h> 64#include <machine/md_var.h> 65 66#define MAX_BPAGES 64 67#define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2 68#define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3 69#define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE) 70#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 71 72struct bounce_zone; 73 74struct bus_dma_tag { 75 bus_dma_tag_t parent; 76 bus_size_t alignment; 77 bus_size_t boundary; 78 bus_addr_t lowaddr; 79 bus_addr_t highaddr; 80 bus_dma_filter_t *filter; 81 void *filterarg; 82 bus_size_t maxsize; 83 u_int nsegments; 84 bus_size_t maxsegsz; 85 int flags; 86 int ref_count; 87 int map_count; 88 bus_dma_lock_t *lockfunc; 89 void *lockfuncarg; 90 struct bounce_zone *bounce_zone; 91 /* 92 * DMA range for this tag. If the page doesn't fall within 93 * one of these ranges, an error is returned. The caller 94 * may then decide what to do with the transfer. If the 95 * range pointer is NULL, it is ignored. 96 */ 97 struct arm32_dma_range *ranges; 98 int _nranges; 99 /* 100 * Most tags need one or two segments, and can use the local tagsegs 101 * array. For tags with a larger limit, we'll allocate a bigger array 102 * on first use. 103 */ 104 bus_dma_segment_t *segments; 105 bus_dma_segment_t tagsegs[2]; 106 107 108}; 109 110struct bounce_page { 111 vm_offset_t vaddr; /* kva of bounce buffer */ 112 bus_addr_t busaddr; /* Physical address */ 113 vm_offset_t datavaddr; /* kva of client data */ 114 bus_addr_t dataaddr; /* client physical address */ 115 bus_size_t datacount; /* client data count */ 116 STAILQ_ENTRY(bounce_page) links; 117}; 118 119struct sync_list { 120 vm_offset_t vaddr; /* kva of bounce buffer */ 121 bus_addr_t busaddr; /* Physical address */ 122 bus_size_t datacount; /* client data count */ 123}; 124 125int busdma_swi_pending; 126 127struct bounce_zone { 128 STAILQ_ENTRY(bounce_zone) links; 129 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 130 int total_bpages; 131 int free_bpages; 132 int reserved_bpages; 133 int active_bpages; 134 int total_bounced; 135 int total_deferred; 136 int map_count; 137 bus_size_t alignment; 138 bus_addr_t lowaddr; 139 char zoneid[8]; 140 char lowaddrid[20]; 141 struct sysctl_ctx_list sysctl_tree; 142 struct sysctl_oid *sysctl_tree_top; 143}; 144 145static struct mtx bounce_lock; 146static int total_bpages; 147static int busdma_zonecount; 148static STAILQ_HEAD(, bounce_zone) bounce_zone_list; 149 150SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 151SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 152 "Total bounce pages"); 153 154struct bus_dmamap { 155 struct bp_list bpages; 156 int pagesneeded; 157 int pagesreserved; 158 bus_dma_tag_t dmat; 159 struct memdesc mem; 160 pmap_t pmap; 161 bus_dmamap_callback_t *callback; 162 void *callback_arg; 163 int flags; 164#define DMAMAP_COHERENT (1 << 0) 165#define DMAMAP_DMAMEM_ALLOC (1 << 1) 166#define DMAMAP_MBUF (1 << 2) 167 STAILQ_ENTRY(bus_dmamap) links; 168 int sync_count; 169 struct sync_list slist[]; 170}; 171 172static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 173static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 174 175static void init_bounce_pages(void *dummy); 176static int alloc_bounce_zone(bus_dma_tag_t dmat); 177static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 178static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 179 int commit); 180static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 181 vm_offset_t vaddr, bus_addr_t addr, 182 bus_size_t size); 183static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 184static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 185 void *buf, bus_size_t buflen, int flags); 186static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 187 vm_paddr_t buf, bus_size_t buflen, int flags); 188static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 189 int flags); 190 191static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 192static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 193static void 194busdma_init(void *dummy) 195{ 196 int uma_flags; 197 198 uma_flags = 0; 199 200 /* Create a cache of buffers in standard (cacheable) memory. */ 201 standard_allocator = busdma_bufalloc_create("buffer", 202 arm_dcache_align, /* minimum_alignment */ 203 NULL, /* uma_alloc func */ 204 NULL, /* uma_free func */ 205 uma_flags); /* uma_zcreate_flags */ 206 207#ifdef INVARIANTS 208 /* 209 * Force UMA zone to allocate service structures like 210 * slabs using own allocator. uma_debug code performs 211 * atomic ops on uma_slab_t fields and safety of this 212 * operation is not guaranteed for write-back caches 213 */ 214 uma_flags = UMA_ZONE_OFFPAGE; 215#endif 216 /* 217 * Create a cache of buffers in uncacheable memory, to implement the 218 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 219 */ 220 coherent_allocator = busdma_bufalloc_create("coherent", 221 arm_dcache_align, /* minimum_alignment */ 222 busdma_bufalloc_alloc_uncacheable, 223 busdma_bufalloc_free_uncacheable, 224 uma_flags); /* uma_zcreate_flags */ 225} 226 227/* 228 * This init historically used SI_SUB_VM, but now the init code requires 229 * malloc(9) using M_DEVBUF memory, which is set up later than SI_SUB_VM, by 230 * SI_SUB_KMEM and SI_ORDER_THIRD, so we'll go right after that by using 231 * SI_SUB_KMEM and SI_ORDER_FOURTH. 232 */ 233SYSINIT(busdma, SI_SUB_KMEM, SI_ORDER_FOURTH, busdma_init, NULL); 234 235/* 236 * This routine checks the exclusion zone constraints from a tag against the 237 * physical RAM available on the machine. If a tag specifies an exclusion zone 238 * but there's no RAM in that zone, then we avoid allocating resources to bounce 239 * a request, and we can use any memory allocator (as opposed to needing 240 * kmem_alloc_contig() just because it can allocate pages in an address range). 241 * 242 * Most tags have BUS_SPACE_MAXADDR or BUS_SPACE_MAXADDR_32BIT (they are the 243 * same value on 32-bit architectures) as their lowaddr constraint, and we can't 244 * possibly have RAM at an address higher than the highest address we can 245 * express, so we take a fast out. 246 */ 247static int 248exclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr) 249{ 250 int i; 251 252 if (lowaddr >= BUS_SPACE_MAXADDR) 253 return (0); 254 255 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 256 if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) || 257 (lowaddr < phys_avail[i] && highaddr >= phys_avail[i])) 258 return (1); 259 } 260 return (0); 261} 262 263/* 264 * Return true if the tag has an exclusion zone that could lead to bouncing. 265 */ 266static __inline int 267exclusion_bounce(bus_dma_tag_t dmat) 268{ 269 270 return (dmat->flags & BUS_DMA_EXCL_BOUNCE); 271} 272 273/* 274 * Return true if the given address does not fall on the alignment boundary. 275 */ 276static __inline int 277alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr) 278{ 279 280 return (addr & (dmat->alignment - 1)); 281} 282 283/* 284 * Return true if the DMA should bounce because the start or end does not fall 285 * on a cacheline boundary (which would require a partial cacheline flush). 286 * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by 287 * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a 288 * strict rule that such memory cannot be accessed by the CPU while DMA is in 289 * progress (or by multiple DMA engines at once), so that it's always safe to do 290 * full cacheline flushes even if that affects memory outside the range of a 291 * given DMA operation that doesn't involve the full allocated buffer. If we're 292 * mapping an mbuf, that follows the same rules as a buffer we allocated. 293 */ 294static __inline int 295cacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size) 296{ 297 298 if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF)) 299 return (0); 300 return ((addr | size) & arm_dcache_align_mask); 301} 302 303/* 304 * Return true if we might need to bounce the DMA described by addr and size. 305 * 306 * This is used to quick-check whether we need to do the more expensive work of 307 * checking the DMA page-by-page looking for alignment and exclusion bounces. 308 * 309 * Note that the addr argument might be either virtual or physical. It doesn't 310 * matter because we only look at the low-order bits, which are the same in both 311 * address spaces. 312 */ 313static __inline int 314might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr, 315 bus_size_t size) 316{ 317 return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) || 318 alignment_bounce(dmat, addr) || 319 cacheline_bounce(map, addr, size)); 320} 321 322/* 323 * Return true if we must bounce the DMA described by paddr and size. 324 * 325 * Bouncing can be triggered by DMA that doesn't begin and end on cacheline 326 * boundaries, or doesn't begin on an alignment boundary, or falls within the 327 * exclusion zone of any tag in the ancestry chain. 328 * 329 * For exclusions, walk the chain of tags comparing paddr to the exclusion zone 330 * within each tag. If the tag has a filter function, use it to decide whether 331 * the DMA needs to bounce, otherwise any DMA within the zone bounces. 332 */ 333static int 334must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, 335 bus_size_t size) 336{ 337 338 if (cacheline_bounce(map, paddr, size)) 339 return (1); 340 341 /* 342 * The tag already contains ancestors' alignment restrictions so this 343 * check doesn't need to be inside the loop. 344 */ 345 if (alignment_bounce(dmat, paddr)) 346 return (1); 347 348 /* 349 * Even though each tag has an exclusion zone that is a superset of its 350 * own and all its ancestors' exclusions, the exclusion zone of each tag 351 * up the chain must be checked within the loop, because the busdma 352 * rules say the filter function is called only when the address lies 353 * within the low-highaddr range of the tag that filterfunc belongs to. 354 */ 355 while (dmat != NULL && exclusion_bounce(dmat)) { 356 if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) && 357 (dmat->filter == NULL || 358 dmat->filter(dmat->filterarg, paddr) != 0)) 359 return (1); 360 dmat = dmat->parent; 361 } 362 363 return (0); 364} 365 366static __inline struct arm32_dma_range * 367_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 368 bus_addr_t curaddr) 369{ 370 struct arm32_dma_range *dr; 371 int i; 372 373 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 374 if (curaddr >= dr->dr_sysbase && 375 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 376 return (dr); 377 } 378 379 return (NULL); 380} 381 382/* 383 * Convenience function for manipulating driver locks from busdma (during 384 * busdma_swi, for example). Drivers that don't provide their own locks 385 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 386 * non-mutex locking scheme don't have to use this at all. 387 */ 388void 389busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 390{ 391 struct mtx *dmtx; 392 393 dmtx = (struct mtx *)arg; 394 switch (op) { 395 case BUS_DMA_LOCK: 396 mtx_lock(dmtx); 397 break; 398 case BUS_DMA_UNLOCK: 399 mtx_unlock(dmtx); 400 break; 401 default: 402 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 403 } 404} 405 406/* 407 * dflt_lock should never get called. It gets put into the dma tag when 408 * lockfunc == NULL, which is only valid if the maps that are associated 409 * with the tag are meant to never be defered. 410 * XXX Should have a way to identify which driver is responsible here. 411 */ 412static void 413dflt_lock(void *arg, bus_dma_lock_op_t op) 414{ 415 panic("driver error: busdma dflt_lock called"); 416} 417 418/* 419 * Allocate a device specific dma_tag. 420 */ 421int 422bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 423 bus_size_t boundary, bus_addr_t lowaddr, 424 bus_addr_t highaddr, bus_dma_filter_t *filter, 425 void *filterarg, bus_size_t maxsize, int nsegments, 426 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 427 void *lockfuncarg, bus_dma_tag_t *dmat) 428{ 429 bus_dma_tag_t newtag; 430 int error = 0; 431 432#if 0 433 if (!parent) 434 parent = arm_root_dma_tag; 435#endif 436 437 /* Basic sanity checking */ 438 if (boundary != 0 && boundary < maxsegsz) 439 maxsegsz = boundary; 440 441 /* Return a NULL tag on failure */ 442 *dmat = NULL; 443 444 if (maxsegsz == 0) { 445 return (EINVAL); 446 } 447 448 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 449 M_ZERO | M_NOWAIT); 450 if (newtag == NULL) { 451 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 452 __func__, newtag, 0, error); 453 return (ENOMEM); 454 } 455 456 newtag->parent = parent; 457 newtag->alignment = alignment; 458 newtag->boundary = boundary; 459 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 460 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 461 (PAGE_SIZE - 1); 462 newtag->filter = filter; 463 newtag->filterarg = filterarg; 464 newtag->maxsize = maxsize; 465 newtag->nsegments = nsegments; 466 newtag->maxsegsz = maxsegsz; 467 newtag->flags = flags; 468 newtag->ref_count = 1; /* Count ourself */ 469 newtag->map_count = 0; 470 newtag->ranges = bus_dma_get_range(); 471 newtag->_nranges = bus_dma_get_range_nb(); 472 if (lockfunc != NULL) { 473 newtag->lockfunc = lockfunc; 474 newtag->lockfuncarg = lockfuncarg; 475 } else { 476 newtag->lockfunc = dflt_lock; 477 newtag->lockfuncarg = NULL; 478 } 479 /* 480 * If all the segments we need fit into the local tagsegs array, set the 481 * pointer now. Otherwise NULL the pointer and an array of segments 482 * will be allocated later, on first use. We don't pre-allocate now 483 * because some tags exist just to pass contraints to children in the 484 * device hierarchy, and they tend to use BUS_SPACE_UNRESTRICTED and we 485 * sure don't want to try to allocate an array for that. 486 */ 487 if (newtag->nsegments <= nitems(newtag->tagsegs)) 488 newtag->segments = newtag->tagsegs; 489 else 490 newtag->segments = NULL; 491 492 /* Take into account any restrictions imposed by our parent tag */ 493 if (parent != NULL) { 494 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 495 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 496 newtag->alignment = MAX(parent->alignment, newtag->alignment); 497 newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE; 498 if (newtag->boundary == 0) 499 newtag->boundary = parent->boundary; 500 else if (parent->boundary != 0) 501 newtag->boundary = MIN(parent->boundary, 502 newtag->boundary); 503 if (newtag->filter == NULL) { 504 /* 505 * Short circuit to looking at our parent directly 506 * since we have encapsulated all of its information 507 */ 508 newtag->filter = parent->filter; 509 newtag->filterarg = parent->filterarg; 510 newtag->parent = parent->parent; 511 } 512 if (newtag->parent != NULL) 513 atomic_add_int(&parent->ref_count, 1); 514 } 515 516 if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr)) 517 newtag->flags |= BUS_DMA_EXCL_BOUNCE; 518 if (alignment_bounce(newtag, 1)) 519 newtag->flags |= BUS_DMA_ALIGN_BOUNCE; 520 521 /* 522 * Any request can auto-bounce due to cacheline alignment, in addition 523 * to any alignment or boundary specifications in the tag, so if the 524 * ALLOCNOW flag is set, there's always work to do. 525 */ 526 if ((flags & BUS_DMA_ALLOCNOW) != 0) { 527 struct bounce_zone *bz; 528 /* 529 * Round size up to a full page, and add one more page because 530 * there can always be one more boundary crossing than the 531 * number of pages in a transfer. 532 */ 533 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 534 535 if ((error = alloc_bounce_zone(newtag)) != 0) { 536 free(newtag, M_DEVBUF); 537 return (error); 538 } 539 bz = newtag->bounce_zone; 540 541 if (ptoa(bz->total_bpages) < maxsize) { 542 int pages; 543 544 pages = atop(maxsize) - bz->total_bpages; 545 546 /* Add pages to our bounce pool */ 547 if (alloc_bounce_pages(newtag, pages) < pages) 548 error = ENOMEM; 549 } 550 /* Performed initial allocation */ 551 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 552 } else 553 newtag->bounce_zone = NULL; 554 555 if (error != 0) { 556 free(newtag, M_DEVBUF); 557 } else { 558 *dmat = newtag; 559 } 560 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 561 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 562 return (error); 563} 564 565int 566bus_dma_tag_destroy(bus_dma_tag_t dmat) 567{ 568 bus_dma_tag_t dmat_copy; 569 int error; 570 571 error = 0; 572 dmat_copy = dmat; 573 574 if (dmat != NULL) { 575 576 if (dmat->map_count != 0) { 577 error = EBUSY; 578 goto out; 579 } 580 581 while (dmat != NULL) { 582 bus_dma_tag_t parent; 583 584 parent = dmat->parent; 585 atomic_subtract_int(&dmat->ref_count, 1); 586 if (dmat->ref_count == 0) { 587 if (dmat->segments != NULL && 588 dmat->segments != dmat->tagsegs) 589 free(dmat->segments, M_DEVBUF); 590 free(dmat, M_DEVBUF); 591 /* 592 * Last reference count, so 593 * release our reference 594 * count on our parent. 595 */ 596 dmat = parent; 597 } else 598 dmat = NULL; 599 } 600 } 601out: 602 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 603 return (error); 604} 605 606static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 607{ 608 struct bounce_zone *bz; 609 int maxpages; 610 int error; 611 612 if (dmat->bounce_zone == NULL) 613 if ((error = alloc_bounce_zone(dmat)) != 0) 614 return (error); 615 bz = dmat->bounce_zone; 616 /* Initialize the new map */ 617 STAILQ_INIT(&(mapp->bpages)); 618 619 /* 620 * Attempt to add pages to our pool on a per-instance basis up to a sane 621 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 622 * alignment and boundary constraints, it could still auto-bounce due to 623 * cacheline alignment, which requires at most two bounce pages. 624 */ 625 if (dmat->flags & BUS_DMA_COULD_BOUNCE) 626 maxpages = MAX_BPAGES; 627 else 628 maxpages = 2 * bz->map_count; 629 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 || 630 (bz->map_count > 0 && bz->total_bpages < maxpages)) { 631 int pages; 632 633 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 634 pages = MIN(maxpages - bz->total_bpages, pages); 635 pages = MAX(pages, 2); 636 if (alloc_bounce_pages(dmat, pages) < pages) 637 return (ENOMEM); 638 639 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 640 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 641 } 642 bz->map_count++; 643 return (0); 644} 645 646/* 647 * Allocate a handle for mapping from kva/uva/physical 648 * address space into bus device space. 649 */ 650int 651bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 652{ 653 int mapsize; 654 int error = 0; 655 656 mapsize = sizeof(**mapp) + (sizeof(struct sync_list) * dmat->nsegments); 657 *mapp = (bus_dmamap_t)malloc(mapsize, M_DEVBUF, M_NOWAIT | M_ZERO); 658 if (*mapp == NULL) { 659 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 660 return (ENOMEM); 661 } 662 (*mapp)->sync_count = 0; 663 664 if (dmat->segments == NULL) { 665 dmat->segments = (bus_dma_segment_t *)malloc( 666 sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF, 667 M_NOWAIT); 668 if (dmat->segments == NULL) { 669 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 670 __func__, dmat, ENOMEM); 671 free(*mapp, M_DEVBUF); 672 *mapp = NULL; 673 return (ENOMEM); 674 } 675 } 676 /* 677 * Bouncing might be required if the driver asks for an active 678 * exclusion region, a data alignment that is stricter than 1, and/or 679 * an active address boundary. 680 */ 681 error = allocate_bz_and_pages(dmat, *mapp); 682 if (error != 0) { 683 free(*mapp, M_DEVBUF); 684 *mapp = NULL; 685 return (error); 686 } 687 return (error); 688} 689 690/* 691 * Destroy a handle for mapping from kva/uva/physical 692 * address space into bus device space. 693 */ 694int 695bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 696{ 697 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 698 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 699 __func__, dmat, EBUSY); 700 return (EBUSY); 701 } 702 if (dmat->bounce_zone) 703 dmat->bounce_zone->map_count--; 704 free(map, M_DEVBUF); 705 dmat->map_count--; 706 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 707 return (0); 708} 709 710 711/* 712 * Allocate a piece of memory that can be efficiently mapped into 713 * bus device space based on the constraints lited in the dma tag. 714 * A dmamap to for use with dmamap_load is also allocated. 715 */ 716int 717bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 718 bus_dmamap_t *mapp) 719{ 720 busdma_bufalloc_t ba; 721 struct busdma_bufzone *bufzone; 722 vm_memattr_t memattr; 723 int mflags; 724 int mapsize; 725 int error; 726 727 if (flags & BUS_DMA_NOWAIT) 728 mflags = M_NOWAIT; 729 else 730 mflags = M_WAITOK; 731 732 /* ARM non-snooping caches need a map for the VA cache sync structure */ 733 734 mapsize = sizeof(**mapp) + (sizeof(struct sync_list) * dmat->nsegments); 735 *mapp = (bus_dmamap_t)malloc(mapsize, M_DEVBUF, M_NOWAIT | M_ZERO); 736 if (*mapp == NULL) { 737 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 738 __func__, dmat, dmat->flags, ENOMEM); 739 return (ENOMEM); 740 } 741 742 (*mapp)->flags = DMAMAP_DMAMEM_ALLOC; 743 (*mapp)->sync_count = 0; 744 745 /* We may need bounce pages, even for allocated memory */ 746 error = allocate_bz_and_pages(dmat, *mapp); 747 if (error != 0) { 748 free(*mapp, M_DEVBUF); 749 *mapp = NULL; 750 return (error); 751 } 752 753 if (dmat->segments == NULL) { 754 dmat->segments = (bus_dma_segment_t *)malloc( 755 sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF, 756 mflags); 757 if (dmat->segments == NULL) { 758 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 759 __func__, dmat, dmat->flags, ENOMEM); 760 free(*mapp, M_DEVBUF); 761 *mapp = NULL; 762 return (ENOMEM); 763 } 764 } 765 766 if (flags & BUS_DMA_ZERO) 767 mflags |= M_ZERO; 768 if (flags & BUS_DMA_COHERENT) { 769 memattr = VM_MEMATTR_UNCACHEABLE; 770 ba = coherent_allocator; 771 (*mapp)->flags |= DMAMAP_COHERENT; 772 } else { 773 memattr = VM_MEMATTR_DEFAULT; 774 ba = standard_allocator; 775 } 776 777 /* 778 * Try to find a bufzone in the allocator that holds a cache of buffers 779 * of the right size for this request. If the buffer is too big to be 780 * held in the allocator cache, this returns NULL. 781 */ 782 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 783 784 /* 785 * Allocate the buffer from the uma(9) allocator if... 786 * - It's small enough to be in the allocator (bufzone not NULL). 787 * - The alignment constraint isn't larger than the allocation size 788 * (the allocator aligns buffers to their size boundaries). 789 * - There's no need to handle lowaddr/highaddr exclusion zones. 790 * else allocate non-contiguous pages if... 791 * - The page count that could get allocated doesn't exceed nsegments. 792 * - The alignment constraint isn't larger than a page boundary. 793 * - There are no boundary-crossing constraints. 794 * else allocate a block of contiguous pages because one or more of the 795 * constraints is something that only the contig allocator can fulfill. 796 */ 797 if (bufzone != NULL && dmat->alignment <= bufzone->size && 798 !exclusion_bounce(dmat)) { 799 *vaddr = uma_zalloc(bufzone->umazone, mflags); 800 } else if (dmat->nsegments >= btoc(dmat->maxsize) && 801 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 802 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 803 mflags, 0, dmat->lowaddr, memattr); 804 } else { 805 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 806 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 807 memattr); 808 } 809 810 811 if (*vaddr == NULL) { 812 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 813 __func__, dmat, dmat->flags, ENOMEM); 814 free(*mapp, M_DEVBUF); 815 *mapp = NULL; 816 return (ENOMEM); 817 } 818 dmat->map_count++; 819 820 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 821 __func__, dmat, dmat->flags, 0); 822 return (0); 823} 824 825/* 826 * Free a piece of memory and it's allociated dmamap, that was allocated 827 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 828 */ 829void 830bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 831{ 832 struct busdma_bufzone *bufzone; 833 busdma_bufalloc_t ba; 834 835 if (map->flags & DMAMAP_COHERENT) 836 ba = coherent_allocator; 837 else 838 ba = standard_allocator; 839 840 /* Be careful not to access map from here on. */ 841 842 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 843 844 if (bufzone != NULL && dmat->alignment <= bufzone->size && 845 !exclusion_bounce(dmat)) 846 uma_zfree(bufzone->umazone, vaddr); 847 else 848 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 849 850 dmat->map_count--; 851 free(map, M_DEVBUF); 852 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 853} 854 855static void 856_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 857 bus_size_t buflen, int flags) 858{ 859 bus_addr_t curaddr; 860 bus_size_t sgsize; 861 862 if (map->pagesneeded == 0) { 863 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 864 " map= %p, pagesneeded= %d", 865 dmat->lowaddr, dmat->boundary, dmat->alignment, 866 map, map->pagesneeded); 867 /* 868 * Count the number of bounce pages 869 * needed in order to complete this transfer 870 */ 871 curaddr = buf; 872 while (buflen != 0) { 873 sgsize = MIN(buflen, dmat->maxsegsz); 874 if (must_bounce(dmat, map, curaddr, sgsize) != 0) { 875 sgsize = MIN(sgsize, PAGE_SIZE); 876 map->pagesneeded++; 877 } 878 curaddr += sgsize; 879 buflen -= sgsize; 880 } 881 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 882 } 883} 884 885static void 886_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 887 void *buf, bus_size_t buflen, int flags) 888{ 889 vm_offset_t vaddr; 890 vm_offset_t vendaddr; 891 bus_addr_t paddr; 892 893 if (map->pagesneeded == 0) { 894 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 895 " map= %p, pagesneeded= %d", 896 dmat->lowaddr, dmat->boundary, dmat->alignment, 897 map, map->pagesneeded); 898 /* 899 * Count the number of bounce pages 900 * needed in order to complete this transfer 901 */ 902 vaddr = (vm_offset_t)buf; 903 vendaddr = (vm_offset_t)buf + buflen; 904 905 while (vaddr < vendaddr) { 906 if (__predict_true(map->pmap == kernel_pmap)) 907 paddr = pmap_kextract(vaddr); 908 else 909 paddr = pmap_extract(map->pmap, vaddr); 910 if (must_bounce(dmat, map, paddr, 911 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr & 912 PAGE_MASK)))) != 0) { 913 map->pagesneeded++; 914 } 915 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 916 917 } 918 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 919 } 920} 921 922static int 923_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 924{ 925 926 /* Reserve Necessary Bounce Pages */ 927 mtx_lock(&bounce_lock); 928 if (flags & BUS_DMA_NOWAIT) { 929 if (reserve_bounce_pages(dmat, map, 0) != 0) { 930 map->pagesneeded = 0; 931 mtx_unlock(&bounce_lock); 932 return (ENOMEM); 933 } 934 } else { 935 if (reserve_bounce_pages(dmat, map, 1) != 0) { 936 /* Queue us for resources */ 937 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 938 mtx_unlock(&bounce_lock); 939 return (EINPROGRESS); 940 } 941 } 942 mtx_unlock(&bounce_lock); 943 944 return (0); 945} 946 947/* 948 * Add a single contiguous physical range to the segment list. 949 */ 950static int 951_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 952 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 953{ 954 bus_addr_t baddr, bmask; 955 int seg; 956 957 /* 958 * Make sure we don't cross any boundaries. 959 */ 960 bmask = ~(dmat->boundary - 1); 961 if (dmat->boundary > 0) { 962 baddr = (curaddr + dmat->boundary) & bmask; 963 if (sgsize > (baddr - curaddr)) 964 sgsize = (baddr - curaddr); 965 } 966 967 if (dmat->ranges) { 968 struct arm32_dma_range *dr; 969 970 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 971 curaddr); 972 if (dr == NULL) { 973 _bus_dmamap_unload(dmat, map); 974 return (0); 975 } 976 /* 977 * In a valid DMA range. Translate the physical 978 * memory address to an address in the DMA window. 979 */ 980 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 981 } 982 983 /* 984 * Insert chunk into a segment, coalescing with 985 * previous segment if possible. 986 */ 987 seg = *segp; 988 if (seg == -1) { 989 seg = 0; 990 segs[seg].ds_addr = curaddr; 991 segs[seg].ds_len = sgsize; 992 } else { 993 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 994 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 995 (dmat->boundary == 0 || 996 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 997 segs[seg].ds_len += sgsize; 998 else { 999 if (++seg >= dmat->nsegments) 1000 return (0); 1001 segs[seg].ds_addr = curaddr; 1002 segs[seg].ds_len = sgsize; 1003 } 1004 } 1005 *segp = seg; 1006 return (sgsize); 1007} 1008 1009/* 1010 * Utility function to load a physical buffer. segp contains 1011 * the starting segment on entrace, and the ending segment on exit. 1012 */ 1013int 1014_bus_dmamap_load_phys(bus_dma_tag_t dmat, 1015 bus_dmamap_t map, 1016 vm_paddr_t buf, bus_size_t buflen, 1017 int flags, 1018 bus_dma_segment_t *segs, 1019 int *segp) 1020{ 1021 bus_addr_t curaddr; 1022 bus_size_t sgsize; 1023 int error; 1024 1025 if (segs == NULL) 1026 segs = dmat->segments; 1027 1028 if (might_bounce(dmat, map, buflen, buflen)) { 1029 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 1030 if (map->pagesneeded != 0) { 1031 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1032 if (error) 1033 return (error); 1034 } 1035 } 1036 1037 while (buflen > 0) { 1038 curaddr = buf; 1039 sgsize = MIN(buflen, dmat->maxsegsz); 1040 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1041 sgsize)) { 1042 sgsize = MIN(sgsize, PAGE_SIZE); 1043 curaddr = add_bounce_page(dmat, map, 0, curaddr, 1044 sgsize); 1045 } 1046 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1047 segp); 1048 if (sgsize == 0) 1049 break; 1050 buf += sgsize; 1051 buflen -= sgsize; 1052 } 1053 1054 /* 1055 * Did we fit? 1056 */ 1057 if (buflen != 0) { 1058 _bus_dmamap_unload(dmat, map); 1059 return (EFBIG); /* XXX better return value here? */ 1060 } 1061 return (0); 1062} 1063 1064int 1065_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 1066 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 1067 bus_dma_segment_t *segs, int *segp) 1068{ 1069 1070 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 1071 segs, segp)); 1072} 1073 1074/* 1075 * Utility function to load a linear buffer. segp contains 1076 * the starting segment on entrace, and the ending segment on exit. 1077 */ 1078int 1079_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1080 bus_dmamap_t map, 1081 void *buf, bus_size_t buflen, 1082 pmap_t pmap, 1083 int flags, 1084 bus_dma_segment_t *segs, 1085 int *segp) 1086{ 1087 bus_size_t sgsize; 1088 bus_addr_t curaddr; 1089 vm_offset_t vaddr; 1090 struct sync_list *sl; 1091 int error; 1092 1093 if (segs == NULL) 1094 segs = dmat->segments; 1095 1096 if (flags & BUS_DMA_LOAD_MBUF) 1097 map->flags |= DMAMAP_MBUF; 1098 1099 map->pmap = pmap; 1100 1101 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) { 1102 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1103 if (map->pagesneeded != 0) { 1104 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1105 if (error) 1106 return (error); 1107 } 1108 } 1109 1110 sl = NULL; 1111 vaddr = (vm_offset_t)buf; 1112 1113 while (buflen > 0) { 1114 /* 1115 * Get the physical address for this segment. 1116 */ 1117 if (__predict_true(map->pmap == kernel_pmap)) 1118 curaddr = pmap_kextract(vaddr); 1119 else 1120 curaddr = pmap_extract(map->pmap, vaddr); 1121 1122 /* 1123 * Compute the segment size, and adjust counts. 1124 */ 1125 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1126 if (sgsize > dmat->maxsegsz) 1127 sgsize = dmat->maxsegsz; 1128 if (buflen < sgsize) 1129 sgsize = buflen; 1130 1131 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1132 sgsize)) { 1133 curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1134 sgsize); 1135 } else { 1136 sl = &map->slist[map->sync_count - 1]; 1137 if (map->sync_count == 0 || 1138#ifdef ARM_L2_PIPT 1139 curaddr != sl->busaddr + sl->datacount || 1140#endif 1141 vaddr != sl->vaddr + sl->datacount) { 1142 if (++map->sync_count > dmat->nsegments) 1143 goto cleanup; 1144 sl++; 1145 sl->vaddr = vaddr; 1146 sl->datacount = sgsize; 1147 sl->busaddr = curaddr; 1148 } else 1149 sl->datacount += sgsize; 1150 } 1151 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1152 segp); 1153 if (sgsize == 0) 1154 break; 1155 vaddr += sgsize; 1156 buflen -= sgsize; 1157 } 1158 1159cleanup: 1160 /* 1161 * Did we fit? 1162 */ 1163 if (buflen != 0) { 1164 _bus_dmamap_unload(dmat, map); 1165 return (EFBIG); /* XXX better return value here? */ 1166 } 1167 return (0); 1168} 1169 1170 1171void 1172__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1173 struct memdesc *mem, bus_dmamap_callback_t *callback, 1174 void *callback_arg) 1175{ 1176 1177 map->mem = *mem; 1178 map->dmat = dmat; 1179 map->callback = callback; 1180 map->callback_arg = callback_arg; 1181} 1182 1183bus_dma_segment_t * 1184_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1185 bus_dma_segment_t *segs, int nsegs, int error) 1186{ 1187 1188 if (segs == NULL) 1189 segs = dmat->segments; 1190 return (segs); 1191} 1192 1193/* 1194 * Release the mapping held by map. 1195 */ 1196void 1197_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1198{ 1199 struct bounce_page *bpage; 1200 struct bounce_zone *bz; 1201 1202 if ((bz = dmat->bounce_zone) != NULL) { 1203 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1204 STAILQ_REMOVE_HEAD(&map->bpages, links); 1205 free_bounce_page(dmat, bpage); 1206 } 1207 1208 bz = dmat->bounce_zone; 1209 bz->free_bpages += map->pagesreserved; 1210 bz->reserved_bpages -= map->pagesreserved; 1211 map->pagesreserved = 0; 1212 map->pagesneeded = 0; 1213 } 1214 map->sync_count = 0; 1215 map->flags &= ~DMAMAP_MBUF; 1216} 1217 1218#ifdef notyetbounceuser 1219 /* If busdma uses user pages, then the interrupt handler could 1220 * be use the kernel vm mapping. Both bounce pages and sync list 1221 * do not cross page boundaries. 1222 * Below is a rough sequence that a person would do to fix the 1223 * user page reference in the kernel vmspace. This would be 1224 * done in the dma post routine. 1225 */ 1226void 1227_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1228 pmap_t pmap, int op) 1229{ 1230 bus_size_t sgsize; 1231 bus_addr_t curaddr; 1232 vm_offset_t va; 1233 1234 /* each synclist entry is contained within a single page. 1235 * 1236 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1237 */ 1238 curaddr = pmap_extract(pmap, buf); 1239 va = pmap_dma_map(curaddr); 1240 switch (op) { 1241 case SYNC_USER_INV: 1242 cpu_dcache_wb_range(va, sgsize); 1243 break; 1244 1245 case SYNC_USER_COPYTO: 1246 bcopy((void *)va, (void *)bounce, sgsize); 1247 break; 1248 1249 case SYNC_USER_COPYFROM: 1250 bcopy((void *) bounce, (void *)va, sgsize); 1251 break; 1252 1253 default: 1254 break; 1255 } 1256 1257 pmap_dma_unmap(va); 1258} 1259#endif 1260 1261#ifdef ARM_L2_PIPT 1262#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1263#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1264#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1265#else 1266#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1267#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1268#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1269#endif 1270 1271void 1272_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1273{ 1274 struct bounce_page *bpage; 1275 struct sync_list *sl, *end; 1276 /* 1277 * If the buffer was from user space, it is possible that this is not 1278 * the same vm map, especially on a POST operation. It's not clear that 1279 * dma on userland buffers can work at all right now, certainly not if a 1280 * partial cacheline flush has to be handled. To be safe, until we're 1281 * able to test direct userland dma, panic on a map mismatch. 1282 */ 1283 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1284 if (!pmap_dmap_iscurrent(map->pmap)) 1285 panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1286 /* Handle data bouncing. */ 1287 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1288 "performing bounce", __func__, dmat, dmat->flags, op); 1289 1290 if (op & BUS_DMASYNC_PREWRITE) { 1291 while (bpage != NULL) { 1292 if (bpage->datavaddr != 0) 1293 bcopy((void *)bpage->datavaddr, 1294 (void *)bpage->vaddr, 1295 bpage->datacount); 1296 else 1297 physcopyout(bpage->dataaddr, 1298 (void *)bpage->vaddr, 1299 bpage->datacount); 1300 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1301 bpage->datacount); 1302 l2cache_wb_range((vm_offset_t)bpage->vaddr, 1303 (vm_offset_t)bpage->busaddr, 1304 bpage->datacount); 1305 bpage = STAILQ_NEXT(bpage, links); 1306 } 1307 dmat->bounce_zone->total_bounced++; 1308 } 1309 1310 if (op & BUS_DMASYNC_PREREAD) { 1311 bpage = STAILQ_FIRST(&map->bpages); 1312 while (bpage != NULL) { 1313 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1314 bpage->datacount); 1315 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1316 (vm_offset_t)bpage->busaddr, 1317 bpage->datacount); 1318 bpage = STAILQ_NEXT(bpage, links); 1319 } 1320 } 1321 if (op & BUS_DMASYNC_POSTREAD) { 1322 while (bpage != NULL) { 1323 vm_offset_t startv; 1324 vm_paddr_t startp; 1325 int len; 1326 1327 startv = bpage->vaddr &~ arm_dcache_align_mask; 1328 startp = bpage->busaddr &~ arm_dcache_align_mask; 1329 len = bpage->datacount; 1330 1331 if (startv != bpage->vaddr) 1332 len += bpage->vaddr & arm_dcache_align_mask; 1333 if (len & arm_dcache_align_mask) 1334 len = (len - 1335 (len & arm_dcache_align_mask)) + 1336 arm_dcache_align; 1337 cpu_dcache_inv_range(startv, len); 1338 l2cache_inv_range(startv, startp, len); 1339 if (bpage->datavaddr != 0) 1340 bcopy((void *)bpage->vaddr, 1341 (void *)bpage->datavaddr, 1342 bpage->datacount); 1343 else 1344 physcopyin((void *)bpage->vaddr, 1345 bpage->dataaddr, 1346 bpage->datacount); 1347 bpage = STAILQ_NEXT(bpage, links); 1348 } 1349 dmat->bounce_zone->total_bounced++; 1350 } 1351 } 1352 if (map->flags & DMAMAP_COHERENT) 1353 return; 1354 1355 if (map->sync_count != 0) { 1356 if (!pmap_dmap_iscurrent(map->pmap)) 1357 panic("_bus_dmamap_sync: wrong user map for sync."); 1358 /* ARM caches are not self-snooping for dma */ 1359 1360 sl = &map->slist[0]; 1361 end = &map->slist[map->sync_count]; 1362 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1363 "performing sync", __func__, dmat, dmat->flags, op); 1364 1365 switch (op) { 1366 case BUS_DMASYNC_PREWRITE: 1367 while (sl != end) { 1368 cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1369 l2cache_wb_range(sl->vaddr, sl->busaddr, 1370 sl->datacount); 1371 sl++; 1372 } 1373 break; 1374 1375 case BUS_DMASYNC_PREREAD: 1376 while (sl != end) { 1377 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1378 l2cache_inv_range(sl->vaddr, sl->busaddr, 1379 sl->datacount); 1380 sl++; 1381 } 1382 break; 1383 1384 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1385 while (sl != end) { 1386 cpu_dcache_wbinv_range(sl->vaddr, sl->datacount); 1387 l2cache_wbinv_range(sl->vaddr, 1388 sl->busaddr, sl->datacount); 1389 sl++; 1390 } 1391 break; 1392 1393 case BUS_DMASYNC_POSTREAD: 1394 case BUS_DMASYNC_POSTWRITE: 1395 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1396 break; 1397 default: 1398 panic("unsupported combination of sync operations: 0x%08x\n", op); 1399 break; 1400 } 1401 } 1402} 1403 1404static void 1405init_bounce_pages(void *dummy __unused) 1406{ 1407 1408 total_bpages = 0; 1409 STAILQ_INIT(&bounce_zone_list); 1410 STAILQ_INIT(&bounce_map_waitinglist); 1411 STAILQ_INIT(&bounce_map_callbacklist); 1412 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1413} 1414SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1415 1416static struct sysctl_ctx_list * 1417busdma_sysctl_tree(struct bounce_zone *bz) 1418{ 1419 return (&bz->sysctl_tree); 1420} 1421 1422static struct sysctl_oid * 1423busdma_sysctl_tree_top(struct bounce_zone *bz) 1424{ 1425 return (bz->sysctl_tree_top); 1426} 1427 1428static int 1429alloc_bounce_zone(bus_dma_tag_t dmat) 1430{ 1431 struct bounce_zone *bz; 1432 1433 /* Check to see if we already have a suitable zone */ 1434 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1435 if ((dmat->alignment <= bz->alignment) && 1436 (dmat->lowaddr >= bz->lowaddr)) { 1437 dmat->bounce_zone = bz; 1438 return (0); 1439 } 1440 } 1441 1442 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1443 M_NOWAIT | M_ZERO)) == NULL) 1444 return (ENOMEM); 1445 1446 STAILQ_INIT(&bz->bounce_page_list); 1447 bz->free_bpages = 0; 1448 bz->reserved_bpages = 0; 1449 bz->active_bpages = 0; 1450 bz->lowaddr = dmat->lowaddr; 1451 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1452 bz->map_count = 0; 1453 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1454 busdma_zonecount++; 1455 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1456 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1457 dmat->bounce_zone = bz; 1458 1459 sysctl_ctx_init(&bz->sysctl_tree); 1460 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1461 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1462 CTLFLAG_RD, 0, ""); 1463 if (bz->sysctl_tree_top == NULL) { 1464 sysctl_ctx_free(&bz->sysctl_tree); 1465 return (0); /* XXX error code? */ 1466 } 1467 1468 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1469 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1470 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1471 "Total bounce pages"); 1472 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1473 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1474 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1475 "Free bounce pages"); 1476 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1477 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1478 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1479 "Reserved bounce pages"); 1480 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1481 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1482 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1483 "Active bounce pages"); 1484 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1485 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1486 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1487 "Total bounce requests"); 1488 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1489 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1490 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1491 "Total bounce requests that were deferred"); 1492 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1493 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1494 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1495 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1496 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1497 "alignment", CTLFLAG_RD, &bz->alignment, 0, ""); 1498 1499 return (0); 1500} 1501 1502static int 1503alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1504{ 1505 struct bounce_zone *bz; 1506 int count; 1507 1508 bz = dmat->bounce_zone; 1509 count = 0; 1510 while (numpages > 0) { 1511 struct bounce_page *bpage; 1512 1513 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1514 M_NOWAIT | M_ZERO); 1515 1516 if (bpage == NULL) 1517 break; 1518 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1519 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0); 1520 if (bpage->vaddr == 0) { 1521 free(bpage, M_DEVBUF); 1522 break; 1523 } 1524 bpage->busaddr = pmap_kextract(bpage->vaddr); 1525 mtx_lock(&bounce_lock); 1526 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1527 total_bpages++; 1528 bz->total_bpages++; 1529 bz->free_bpages++; 1530 mtx_unlock(&bounce_lock); 1531 count++; 1532 numpages--; 1533 } 1534 return (count); 1535} 1536 1537static int 1538reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1539{ 1540 struct bounce_zone *bz; 1541 int pages; 1542 1543 mtx_assert(&bounce_lock, MA_OWNED); 1544 bz = dmat->bounce_zone; 1545 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1546 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1547 return (map->pagesneeded - (map->pagesreserved + pages)); 1548 bz->free_bpages -= pages; 1549 bz->reserved_bpages += pages; 1550 map->pagesreserved += pages; 1551 pages = map->pagesneeded - map->pagesreserved; 1552 1553 return (pages); 1554} 1555 1556static bus_addr_t 1557add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1558 bus_addr_t addr, bus_size_t size) 1559{ 1560 struct bounce_zone *bz; 1561 struct bounce_page *bpage; 1562 1563 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1564 KASSERT(map != NULL, 1565 ("add_bounce_page: bad map %p", map)); 1566 1567 bz = dmat->bounce_zone; 1568 if (map->pagesneeded == 0) 1569 panic("add_bounce_page: map doesn't need any pages"); 1570 map->pagesneeded--; 1571 1572 if (map->pagesreserved == 0) 1573 panic("add_bounce_page: map doesn't need any pages"); 1574 map->pagesreserved--; 1575 1576 mtx_lock(&bounce_lock); 1577 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1578 if (bpage == NULL) 1579 panic("add_bounce_page: free page list is empty"); 1580 1581 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1582 bz->reserved_bpages--; 1583 bz->active_bpages++; 1584 mtx_unlock(&bounce_lock); 1585 1586 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1587 /* Page offset needs to be preserved. */ 1588 bpage->vaddr |= vaddr & PAGE_MASK; 1589 bpage->busaddr |= vaddr & PAGE_MASK; 1590 } 1591 bpage->datavaddr = vaddr; 1592 bpage->dataaddr = addr; 1593 bpage->datacount = size; 1594 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1595 return (bpage->busaddr); 1596} 1597 1598static void 1599free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1600{ 1601 struct bus_dmamap *map; 1602 struct bounce_zone *bz; 1603 1604 bz = dmat->bounce_zone; 1605 bpage->datavaddr = 0; 1606 bpage->datacount = 0; 1607 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1608 /* 1609 * Reset the bounce page to start at offset 0. Other uses 1610 * of this bounce page may need to store a full page of 1611 * data and/or assume it starts on a page boundary. 1612 */ 1613 bpage->vaddr &= ~PAGE_MASK; 1614 bpage->busaddr &= ~PAGE_MASK; 1615 } 1616 1617 mtx_lock(&bounce_lock); 1618 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1619 bz->free_bpages++; 1620 bz->active_bpages--; 1621 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1622 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1623 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1624 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1625 map, links); 1626 busdma_swi_pending = 1; 1627 bz->total_deferred++; 1628 swi_sched(vm_ih, 0); 1629 } 1630 } 1631 mtx_unlock(&bounce_lock); 1632} 1633 1634void 1635busdma_swi(void) 1636{ 1637 bus_dma_tag_t dmat; 1638 struct bus_dmamap *map; 1639 1640 mtx_lock(&bounce_lock); 1641 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1642 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1643 mtx_unlock(&bounce_lock); 1644 dmat = map->dmat; 1645 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK); 1646 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1647 map->callback_arg, BUS_DMA_WAITOK); 1648 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1649 mtx_lock(&bounce_lock); 1650 } 1651 mtx_unlock(&bounce_lock); 1652} 1653