busdma_machdep-v6.c revision 269206
1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 269206 2014-07-29 02:31:29Z ian $"); 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43#include <sys/bus.h> 44#include <sys/busdma_bufalloc.h> 45#include <sys/interrupt.h> 46#include <sys/kernel.h> 47#include <sys/ktr.h> 48#include <sys/lock.h> 49#include <sys/memdesc.h> 50#include <sys/proc.h> 51#include <sys/mutex.h> 52#include <sys/sysctl.h> 53#include <sys/uio.h> 54 55#include <vm/vm.h> 56#include <vm/vm_page.h> 57#include <vm/vm_map.h> 58#include <vm/vm_extern.h> 59#include <vm/vm_kern.h> 60 61#include <machine/atomic.h> 62#include <machine/bus.h> 63#include <machine/cpufunc.h> 64#include <machine/md_var.h> 65 66#define MAX_BPAGES 64 67#define BUS_DMA_COULD_BOUNCE BUS_DMA_BUS3 68#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 69 70struct bounce_zone; 71 72struct bus_dma_tag { 73 bus_dma_tag_t parent; 74 bus_size_t alignment; 75 bus_size_t boundary; 76 bus_addr_t lowaddr; 77 bus_addr_t highaddr; 78 bus_dma_filter_t *filter; 79 void *filterarg; 80 bus_size_t maxsize; 81 u_int nsegments; 82 bus_size_t maxsegsz; 83 int flags; 84 int ref_count; 85 int map_count; 86 bus_dma_lock_t *lockfunc; 87 void *lockfuncarg; 88 struct bounce_zone *bounce_zone; 89 /* 90 * DMA range for this tag. If the page doesn't fall within 91 * one of these ranges, an error is returned. The caller 92 * may then decide what to do with the transfer. If the 93 * range pointer is NULL, it is ignored. 94 */ 95 struct arm32_dma_range *ranges; 96 int _nranges; 97 /* 98 * Most tags need one or two segments, and can use the local tagsegs 99 * array. For tags with a larger limit, we'll allocate a bigger array 100 * on first use. 101 */ 102 bus_dma_segment_t *segments; 103 bus_dma_segment_t tagsegs[2]; 104 105 106}; 107 108struct bounce_page { 109 vm_offset_t vaddr; /* kva of bounce buffer */ 110 bus_addr_t busaddr; /* Physical address */ 111 vm_offset_t datavaddr; /* kva of client data */ 112 bus_addr_t dataaddr; /* client physical address */ 113 bus_size_t datacount; /* client data count */ 114 STAILQ_ENTRY(bounce_page) links; 115}; 116 117struct sync_list { 118 vm_offset_t vaddr; /* kva of bounce buffer */ 119 bus_addr_t busaddr; /* Physical address */ 120 bus_size_t datacount; /* client data count */ 121}; 122 123int busdma_swi_pending; 124 125struct bounce_zone { 126 STAILQ_ENTRY(bounce_zone) links; 127 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 128 int total_bpages; 129 int free_bpages; 130 int reserved_bpages; 131 int active_bpages; 132 int total_bounced; 133 int total_deferred; 134 int map_count; 135 bus_size_t alignment; 136 bus_addr_t lowaddr; 137 char zoneid[8]; 138 char lowaddrid[20]; 139 struct sysctl_ctx_list sysctl_tree; 140 struct sysctl_oid *sysctl_tree_top; 141}; 142 143static struct mtx bounce_lock; 144static int total_bpages; 145static int busdma_zonecount; 146static STAILQ_HEAD(, bounce_zone) bounce_zone_list; 147 148SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 149SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 150 "Total bounce pages"); 151 152struct bus_dmamap { 153 struct bp_list bpages; 154 int pagesneeded; 155 int pagesreserved; 156 bus_dma_tag_t dmat; 157 struct memdesc mem; 158 pmap_t pmap; 159 bus_dmamap_callback_t *callback; 160 void *callback_arg; 161 int flags; 162#define DMAMAP_COHERENT (1 << 0) 163 STAILQ_ENTRY(bus_dmamap) links; 164 int sync_count; 165 struct sync_list slist[]; 166}; 167 168static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 169static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 170 171static void init_bounce_pages(void *dummy); 172static int alloc_bounce_zone(bus_dma_tag_t dmat); 173static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 174static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 175 int commit); 176static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 177 vm_offset_t vaddr, bus_addr_t addr, 178 bus_size_t size); 179static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 180int run_filter(bus_dma_tag_t dmat, bus_addr_t paddr, bus_size_t size, int coherent); 181static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 182 void *buf, bus_size_t buflen, int flags); 183static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 184 vm_paddr_t buf, bus_size_t buflen, int flags); 185static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 186 int flags); 187 188static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 189static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 190static void 191busdma_init(void *dummy) 192{ 193 int uma_flags; 194 195 uma_flags = 0; 196 197 /* Create a cache of buffers in standard (cacheable) memory. */ 198 standard_allocator = busdma_bufalloc_create("buffer", 199 arm_dcache_align, /* minimum_alignment */ 200 NULL, /* uma_alloc func */ 201 NULL, /* uma_free func */ 202 uma_flags); /* uma_zcreate_flags */ 203 204#ifdef INVARIANTS 205 /* 206 * Force UMA zone to allocate service structures like 207 * slabs using own allocator. uma_debug code performs 208 * atomic ops on uma_slab_t fields and safety of this 209 * operation is not guaranteed for write-back caches 210 */ 211 uma_flags = UMA_ZONE_OFFPAGE; 212#endif 213 /* 214 * Create a cache of buffers in uncacheable memory, to implement the 215 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 216 */ 217 coherent_allocator = busdma_bufalloc_create("coherent", 218 arm_dcache_align, /* minimum_alignment */ 219 busdma_bufalloc_alloc_uncacheable, 220 busdma_bufalloc_free_uncacheable, 221 uma_flags); /* uma_zcreate_flags */ 222} 223 224/* 225 * This init historically used SI_SUB_VM, but now the init code requires 226 * malloc(9) using M_DEVBUF memory, which is set up later than SI_SUB_VM, by 227 * SI_SUB_KMEM and SI_ORDER_THIRD, so we'll go right after that by using 228 * SI_SUB_KMEM and SI_ORDER_FOURTH. 229 */ 230SYSINIT(busdma, SI_SUB_KMEM, SI_ORDER_FOURTH, busdma_init, NULL); 231 232/* 233 * This routine checks the exclusion zone constraints from a tag against the 234 * physical RAM available on the machine. If a tag specifies an exclusion zone 235 * but there's no RAM in that zone, then we avoid allocating resources to bounce 236 * a request, and we can use any memory allocator (as opposed to needing 237 * kmem_alloc_contig() just because it can allocate pages in an address range). 238 * 239 * Most tags have BUS_SPACE_MAXADDR or BUS_SPACE_MAXADDR_32BIT (they are the 240 * same value on 32-bit architectures) as their lowaddr constraint, and we can't 241 * possibly have RAM at an address higher than the highest address we can 242 * express, so we take a fast out. 243 */ 244static int 245exclusion_bounce(vm_offset_t lowaddr, vm_offset_t highaddr) 246{ 247 int i; 248 249 if (lowaddr >= BUS_SPACE_MAXADDR) 250 return (0); 251 252 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 253 if ((lowaddr >= phys_avail[i] && lowaddr <= phys_avail[i + 1]) 254 || (lowaddr < phys_avail[i] && 255 highaddr > phys_avail[i])) 256 return (1); 257 } 258 return (0); 259} 260 261/* 262 * Return true if the given address does not fall on the alignment boundary. 263 */ 264static __inline int 265alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr) 266{ 267 268 return (addr & (dmat->alignment - 1)); 269} 270 271/* 272 * Return true if the buffer start or end does not fall on a cacheline boundary. 273 */ 274static __inline int 275cacheline_bounce(bus_addr_t addr, bus_size_t size) 276{ 277 278 return ((addr | size) & arm_dcache_align_mask); 279} 280 281static __inline struct arm32_dma_range * 282_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 283 bus_addr_t curaddr) 284{ 285 struct arm32_dma_range *dr; 286 int i; 287 288 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 289 if (curaddr >= dr->dr_sysbase && 290 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 291 return (dr); 292 } 293 294 return (NULL); 295} 296 297/* 298 * Return true if a match is made. 299 * 300 * To find a match walk the chain of bus_dma_tag_t's looking for 'paddr'. 301 * 302 * If paddr is within the bounds of the dma tag then call the filter callback 303 * to check for a match, if there is no filter callback then assume a match. 304 */ 305int 306run_filter(bus_dma_tag_t dmat, bus_addr_t paddr, bus_size_t size, int coherent) 307{ 308 int retval; 309 310 retval = 0; 311 312 do { 313 if (((paddr > dmat->lowaddr && paddr <= dmat->highaddr) 314 || alignment_bounce(dmat, paddr) || 315 (!coherent && cacheline_bounce(paddr, size))) 316 && (dmat->filter == NULL 317 || (*dmat->filter)(dmat->filterarg, paddr) != 0)) 318 retval = 1; 319 320 dmat = dmat->parent; 321 } while (retval == 0 && dmat != NULL); 322 return (retval); 323} 324 325/* 326 * Convenience function for manipulating driver locks from busdma (during 327 * busdma_swi, for example). Drivers that don't provide their own locks 328 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 329 * non-mutex locking scheme don't have to use this at all. 330 */ 331void 332busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 333{ 334 struct mtx *dmtx; 335 336 dmtx = (struct mtx *)arg; 337 switch (op) { 338 case BUS_DMA_LOCK: 339 mtx_lock(dmtx); 340 break; 341 case BUS_DMA_UNLOCK: 342 mtx_unlock(dmtx); 343 break; 344 default: 345 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 346 } 347} 348 349/* 350 * dflt_lock should never get called. It gets put into the dma tag when 351 * lockfunc == NULL, which is only valid if the maps that are associated 352 * with the tag are meant to never be defered. 353 * XXX Should have a way to identify which driver is responsible here. 354 */ 355static void 356dflt_lock(void *arg, bus_dma_lock_op_t op) 357{ 358 panic("driver error: busdma dflt_lock called"); 359} 360 361/* 362 * Allocate a device specific dma_tag. 363 */ 364int 365bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 366 bus_size_t boundary, bus_addr_t lowaddr, 367 bus_addr_t highaddr, bus_dma_filter_t *filter, 368 void *filterarg, bus_size_t maxsize, int nsegments, 369 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 370 void *lockfuncarg, bus_dma_tag_t *dmat) 371{ 372 bus_dma_tag_t newtag; 373 int error = 0; 374 375#if 0 376 if (!parent) 377 parent = arm_root_dma_tag; 378#endif 379 380 /* Basic sanity checking */ 381 if (boundary != 0 && boundary < maxsegsz) 382 maxsegsz = boundary; 383 384 /* Return a NULL tag on failure */ 385 *dmat = NULL; 386 387 if (maxsegsz == 0) { 388 return (EINVAL); 389 } 390 391 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 392 M_ZERO | M_NOWAIT); 393 if (newtag == NULL) { 394 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 395 __func__, newtag, 0, error); 396 return (ENOMEM); 397 } 398 399 newtag->parent = parent; 400 newtag->alignment = alignment; 401 newtag->boundary = boundary; 402 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 403 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 404 (PAGE_SIZE - 1); 405 newtag->filter = filter; 406 newtag->filterarg = filterarg; 407 newtag->maxsize = maxsize; 408 newtag->nsegments = nsegments; 409 newtag->maxsegsz = maxsegsz; 410 newtag->flags = flags; 411 newtag->ref_count = 1; /* Count ourself */ 412 newtag->map_count = 0; 413 newtag->ranges = bus_dma_get_range(); 414 newtag->_nranges = bus_dma_get_range_nb(); 415 if (lockfunc != NULL) { 416 newtag->lockfunc = lockfunc; 417 newtag->lockfuncarg = lockfuncarg; 418 } else { 419 newtag->lockfunc = dflt_lock; 420 newtag->lockfuncarg = NULL; 421 } 422 /* 423 * If all the segments we need fit into the local tagsegs array, set the 424 * pointer now. Otherwise NULL the pointer and an array of segments 425 * will be allocated later, on first use. We don't pre-allocate now 426 * because some tags exist just to pass contraints to children in the 427 * device hierarchy, and they tend to use BUS_SPACE_UNRESTRICTED and we 428 * sure don't want to try to allocate an array for that. 429 */ 430 if (newtag->nsegments <= nitems(newtag->tagsegs)) 431 newtag->segments = newtag->tagsegs; 432 else 433 newtag->segments = NULL; 434 435 /* Take into account any restrictions imposed by our parent tag */ 436 if (parent != NULL) { 437 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 438 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 439 if (newtag->boundary == 0) 440 newtag->boundary = parent->boundary; 441 else if (parent->boundary != 0) 442 newtag->boundary = MIN(parent->boundary, 443 newtag->boundary); 444 if ((newtag->filter != NULL) || 445 ((parent->flags & BUS_DMA_COULD_BOUNCE) != 0)) 446 newtag->flags |= BUS_DMA_COULD_BOUNCE; 447 if (newtag->filter == NULL) { 448 /* 449 * Short circuit looking at our parent directly 450 * since we have encapsulated all of its information 451 */ 452 newtag->filter = parent->filter; 453 newtag->filterarg = parent->filterarg; 454 newtag->parent = parent->parent; 455 } 456 if (newtag->parent != NULL) 457 atomic_add_int(&parent->ref_count, 1); 458 } 459 460 if (exclusion_bounce(newtag->lowaddr, newtag->highaddr) 461 || alignment_bounce(newtag, 1)) 462 newtag->flags |= BUS_DMA_COULD_BOUNCE; 463 464 /* 465 * Any request can auto-bounce due to cacheline alignment, in addition 466 * to any alignment or boundary specifications in the tag, so if the 467 * ALLOCNOW flag is set, there's always work to do. 468 */ 469 if ((flags & BUS_DMA_ALLOCNOW) != 0) { 470 struct bounce_zone *bz; 471 /* 472 * Round size up to a full page, and add one more page because 473 * there can always be one more boundary crossing than the 474 * number of pages in a transfer. 475 */ 476 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 477 478 if ((error = alloc_bounce_zone(newtag)) != 0) { 479 free(newtag, M_DEVBUF); 480 return (error); 481 } 482 bz = newtag->bounce_zone; 483 484 if (ptoa(bz->total_bpages) < maxsize) { 485 int pages; 486 487 pages = atop(maxsize) - bz->total_bpages; 488 489 /* Add pages to our bounce pool */ 490 if (alloc_bounce_pages(newtag, pages) < pages) 491 error = ENOMEM; 492 } 493 /* Performed initial allocation */ 494 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 495 } else 496 newtag->bounce_zone = NULL; 497 498 if (error != 0) { 499 free(newtag, M_DEVBUF); 500 } else { 501 *dmat = newtag; 502 } 503 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 504 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 505 return (error); 506} 507 508int 509bus_dma_tag_destroy(bus_dma_tag_t dmat) 510{ 511 bus_dma_tag_t dmat_copy; 512 int error; 513 514 error = 0; 515 dmat_copy = dmat; 516 517 if (dmat != NULL) { 518 519 if (dmat->map_count != 0) { 520 error = EBUSY; 521 goto out; 522 } 523 524 while (dmat != NULL) { 525 bus_dma_tag_t parent; 526 527 parent = dmat->parent; 528 atomic_subtract_int(&dmat->ref_count, 1); 529 if (dmat->ref_count == 0) { 530 if (dmat->segments != NULL && 531 dmat->segments != dmat->tagsegs) 532 free(dmat->segments, M_DEVBUF); 533 free(dmat, M_DEVBUF); 534 /* 535 * Last reference count, so 536 * release our reference 537 * count on our parent. 538 */ 539 dmat = parent; 540 } else 541 dmat = NULL; 542 } 543 } 544out: 545 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 546 return (error); 547} 548 549static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 550{ 551 struct bounce_zone *bz; 552 int maxpages; 553 int error; 554 555 if (dmat->bounce_zone == NULL) 556 if ((error = alloc_bounce_zone(dmat)) != 0) 557 return (error); 558 bz = dmat->bounce_zone; 559 /* Initialize the new map */ 560 STAILQ_INIT(&(mapp->bpages)); 561 562 /* 563 * Attempt to add pages to our pool on a per-instance basis up to a sane 564 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 565 * alignment and boundary constraints, it could still auto-bounce due to 566 * cacheline alignment, which requires at most two bounce pages. 567 */ 568 if (dmat->flags & BUS_DMA_COULD_BOUNCE) 569 maxpages = MAX_BPAGES; 570 else 571 maxpages = 2 * bz->map_count; 572 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 573 || (bz->map_count > 0 && bz->total_bpages < maxpages)) { 574 int pages; 575 576 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 577 pages = MIN(maxpages - bz->total_bpages, pages); 578 pages = MAX(pages, 2); 579 if (alloc_bounce_pages(dmat, pages) < pages) 580 return (ENOMEM); 581 582 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 583 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 584 } 585 bz->map_count++; 586 return (0); 587} 588 589/* 590 * Allocate a handle for mapping from kva/uva/physical 591 * address space into bus device space. 592 */ 593int 594bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 595{ 596 int mapsize; 597 int error = 0; 598 599 mapsize = sizeof(**mapp) + (sizeof(struct sync_list) * dmat->nsegments); 600 *mapp = (bus_dmamap_t)malloc(mapsize, M_DEVBUF, M_NOWAIT | M_ZERO); 601 if (*mapp == NULL) { 602 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 603 return (ENOMEM); 604 } 605 (*mapp)->sync_count = 0; 606 607 if (dmat->segments == NULL) { 608 dmat->segments = (bus_dma_segment_t *)malloc( 609 sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF, 610 M_NOWAIT); 611 if (dmat->segments == NULL) { 612 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 613 __func__, dmat, ENOMEM); 614 free(*mapp, M_DEVBUF); 615 *mapp = NULL; 616 return (ENOMEM); 617 } 618 } 619 /* 620 * Bouncing might be required if the driver asks for an active 621 * exclusion region, a data alignment that is stricter than 1, and/or 622 * an active address boundary. 623 */ 624 error = allocate_bz_and_pages(dmat, *mapp); 625 if (error != 0) { 626 free(*mapp, M_DEVBUF); 627 *mapp = NULL; 628 return (error); 629 } 630 return (error); 631} 632 633/* 634 * Destroy a handle for mapping from kva/uva/physical 635 * address space into bus device space. 636 */ 637int 638bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 639{ 640 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 641 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 642 __func__, dmat, EBUSY); 643 return (EBUSY); 644 } 645 if (dmat->bounce_zone) 646 dmat->bounce_zone->map_count--; 647 free(map, M_DEVBUF); 648 dmat->map_count--; 649 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 650 return (0); 651} 652 653 654/* 655 * Allocate a piece of memory that can be efficiently mapped into 656 * bus device space based on the constraints lited in the dma tag. 657 * A dmamap to for use with dmamap_load is also allocated. 658 */ 659int 660bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 661 bus_dmamap_t *mapp) 662{ 663 busdma_bufalloc_t ba; 664 struct busdma_bufzone *bufzone; 665 vm_memattr_t memattr; 666 int mflags; 667 int mapsize; 668 int error; 669 670 if (flags & BUS_DMA_NOWAIT) 671 mflags = M_NOWAIT; 672 else 673 mflags = M_WAITOK; 674 675 /* ARM non-snooping caches need a map for the VA cache sync structure */ 676 677 mapsize = sizeof(**mapp) + (sizeof(struct sync_list) * dmat->nsegments); 678 *mapp = (bus_dmamap_t)malloc(mapsize, M_DEVBUF, M_NOWAIT | M_ZERO); 679 if (*mapp == NULL) { 680 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 681 __func__, dmat, dmat->flags, ENOMEM); 682 return (ENOMEM); 683 } 684 685 (*mapp)->sync_count = 0; 686 /* We may need bounce pages, even for allocated memory */ 687 error = allocate_bz_and_pages(dmat, *mapp); 688 if (error != 0) { 689 free(*mapp, M_DEVBUF); 690 *mapp = NULL; 691 return (error); 692 } 693 694 if (dmat->segments == NULL) { 695 dmat->segments = (bus_dma_segment_t *)malloc( 696 sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF, 697 mflags); 698 if (dmat->segments == NULL) { 699 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 700 __func__, dmat, dmat->flags, ENOMEM); 701 free(*mapp, M_DEVBUF); 702 *mapp = NULL; 703 return (ENOMEM); 704 } 705 } 706 707 if (flags & BUS_DMA_ZERO) 708 mflags |= M_ZERO; 709 if (flags & BUS_DMA_COHERENT) { 710 memattr = VM_MEMATTR_UNCACHEABLE; 711 ba = coherent_allocator; 712 (*mapp)->flags |= DMAMAP_COHERENT; 713 } else { 714 memattr = VM_MEMATTR_DEFAULT; 715 ba = standard_allocator; 716 (*mapp)->flags = 0; 717 } 718 719 /* 720 * Try to find a bufzone in the allocator that holds a cache of buffers 721 * of the right size for this request. If the buffer is too big to be 722 * held in the allocator cache, this returns NULL. 723 */ 724 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 725 726 /* 727 * Allocate the buffer from the uma(9) allocator if... 728 * - It's small enough to be in the allocator (bufzone not NULL). 729 * - The alignment constraint isn't larger than the allocation size 730 * (the allocator aligns buffers to their size boundaries). 731 * - There's no need to handle lowaddr/highaddr exclusion zones. 732 * else allocate non-contiguous pages if... 733 * - The page count that could get allocated doesn't exceed nsegments. 734 * - The alignment constraint isn't larger than a page boundary. 735 * - There are no boundary-crossing constraints. 736 * else allocate a block of contiguous pages because one or more of the 737 * constraints is something that only the contig allocator can fulfill. 738 */ 739 if (bufzone != NULL && dmat->alignment <= bufzone->size && 740 !exclusion_bounce(dmat->lowaddr, dmat->highaddr)) { 741 *vaddr = uma_zalloc(bufzone->umazone, mflags); 742 } else if (dmat->nsegments >= btoc(dmat->maxsize) && 743 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 744 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 745 mflags, 0, dmat->lowaddr, memattr); 746 } else { 747 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 748 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 749 memattr); 750 } 751 752 753 if (*vaddr == NULL) { 754 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 755 __func__, dmat, dmat->flags, ENOMEM); 756 free(*mapp, M_DEVBUF); 757 *mapp = NULL; 758 return (ENOMEM); 759 } 760 dmat->map_count++; 761 762 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 763 __func__, dmat, dmat->flags, 0); 764 return (0); 765} 766 767/* 768 * Free a piece of memory and it's allociated dmamap, that was allocated 769 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 770 */ 771void 772bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 773{ 774 struct busdma_bufzone *bufzone; 775 busdma_bufalloc_t ba; 776 777 if (map->flags & DMAMAP_COHERENT) 778 ba = coherent_allocator; 779 else 780 ba = standard_allocator; 781 782 /* Be careful not to access map from here on. */ 783 784 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 785 786 if (bufzone != NULL && dmat->alignment <= bufzone->size && 787 !exclusion_bounce(dmat->lowaddr, dmat->highaddr)) 788 uma_zfree(bufzone->umazone, vaddr); 789 else 790 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 791 792 dmat->map_count--; 793 free(map, M_DEVBUF); 794 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 795} 796 797static void 798_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 799 bus_size_t buflen, int flags) 800{ 801 bus_addr_t curaddr; 802 bus_size_t sgsize; 803 804 if (map->pagesneeded == 0) { 805 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 806 " map= %p, pagesneeded= %d", 807 dmat->lowaddr, dmat->boundary, dmat->alignment, 808 map, map->pagesneeded); 809 /* 810 * Count the number of bounce pages 811 * needed in order to complete this transfer 812 */ 813 curaddr = buf; 814 while (buflen != 0) { 815 sgsize = MIN(buflen, dmat->maxsegsz); 816 if (run_filter(dmat, curaddr, sgsize, 817 map->flags & DMAMAP_COHERENT) != 0) { 818 sgsize = MIN(sgsize, PAGE_SIZE); 819 map->pagesneeded++; 820 } 821 curaddr += sgsize; 822 buflen -= sgsize; 823 } 824 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 825 } 826} 827 828static void 829_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 830 void *buf, bus_size_t buflen, int flags) 831{ 832 vm_offset_t vaddr; 833 vm_offset_t vendaddr; 834 bus_addr_t paddr; 835 836 if (map->pagesneeded == 0) { 837 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 838 " map= %p, pagesneeded= %d", 839 dmat->lowaddr, dmat->boundary, dmat->alignment, 840 map, map->pagesneeded); 841 /* 842 * Count the number of bounce pages 843 * needed in order to complete this transfer 844 */ 845 vaddr = (vm_offset_t)buf; 846 vendaddr = (vm_offset_t)buf + buflen; 847 848 while (vaddr < vendaddr) { 849 if (__predict_true(map->pmap == kernel_pmap)) 850 paddr = pmap_kextract(vaddr); 851 else 852 paddr = pmap_extract(map->pmap, vaddr); 853 if (run_filter(dmat, paddr, 854 min(vendaddr - vaddr, 855 (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK))), 856 map->flags & DMAMAP_COHERENT) != 0) { 857 map->pagesneeded++; 858 } 859 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 860 861 } 862 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 863 } 864} 865 866static int 867_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 868{ 869 870 /* Reserve Necessary Bounce Pages */ 871 mtx_lock(&bounce_lock); 872 if (flags & BUS_DMA_NOWAIT) { 873 if (reserve_bounce_pages(dmat, map, 0) != 0) { 874 map->pagesneeded = 0; 875 mtx_unlock(&bounce_lock); 876 return (ENOMEM); 877 } 878 } else { 879 if (reserve_bounce_pages(dmat, map, 1) != 0) { 880 /* Queue us for resources */ 881 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 882 mtx_unlock(&bounce_lock); 883 return (EINPROGRESS); 884 } 885 } 886 mtx_unlock(&bounce_lock); 887 888 return (0); 889} 890 891/* 892 * Add a single contiguous physical range to the segment list. 893 */ 894static int 895_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 896 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 897{ 898 bus_addr_t baddr, bmask; 899 int seg; 900 901 /* 902 * Make sure we don't cross any boundaries. 903 */ 904 bmask = ~(dmat->boundary - 1); 905 if (dmat->boundary > 0) { 906 baddr = (curaddr + dmat->boundary) & bmask; 907 if (sgsize > (baddr - curaddr)) 908 sgsize = (baddr - curaddr); 909 } 910 911 if (dmat->ranges) { 912 struct arm32_dma_range *dr; 913 914 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 915 curaddr); 916 if (dr == NULL) { 917 _bus_dmamap_unload(dmat, map); 918 return (0); 919 } 920 /* 921 * In a valid DMA range. Translate the physical 922 * memory address to an address in the DMA window. 923 */ 924 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 925 } 926 927 /* 928 * Insert chunk into a segment, coalescing with 929 * previous segment if possible. 930 */ 931 seg = *segp; 932 if (seg == -1) { 933 seg = 0; 934 segs[seg].ds_addr = curaddr; 935 segs[seg].ds_len = sgsize; 936 } else { 937 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 938 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 939 (dmat->boundary == 0 || 940 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 941 segs[seg].ds_len += sgsize; 942 else { 943 if (++seg >= dmat->nsegments) 944 return (0); 945 segs[seg].ds_addr = curaddr; 946 segs[seg].ds_len = sgsize; 947 } 948 } 949 *segp = seg; 950 return (sgsize); 951} 952 953/* 954 * Utility function to load a physical buffer. segp contains 955 * the starting segment on entrace, and the ending segment on exit. 956 */ 957int 958_bus_dmamap_load_phys(bus_dma_tag_t dmat, 959 bus_dmamap_t map, 960 vm_paddr_t buf, bus_size_t buflen, 961 int flags, 962 bus_dma_segment_t *segs, 963 int *segp) 964{ 965 bus_addr_t curaddr; 966 bus_size_t sgsize; 967 int error; 968 969 if (segs == NULL) 970 segs = dmat->segments; 971 972 if (((map->flags & DMAMAP_COHERENT) == 0) || 973 (dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) { 974 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 975 if (map->pagesneeded != 0) { 976 error = _bus_dmamap_reserve_pages(dmat, map, flags); 977 if (error) 978 return (error); 979 } 980 } 981 982 while (buflen > 0) { 983 curaddr = buf; 984 sgsize = MIN(buflen, dmat->maxsegsz); 985 if ((((map->flags & DMAMAP_COHERENT) == 0) || 986 ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0)) && 987 map->pagesneeded != 0 && run_filter(dmat, curaddr, 988 sgsize, map->flags & DMAMAP_COHERENT)) { 989 sgsize = MIN(sgsize, PAGE_SIZE); 990 curaddr = add_bounce_page(dmat, map, 0, curaddr, 991 sgsize); 992 } 993 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 994 segp); 995 if (sgsize == 0) 996 break; 997 buf += sgsize; 998 buflen -= sgsize; 999 } 1000 1001 /* 1002 * Did we fit? 1003 */ 1004 if (buflen != 0) { 1005 _bus_dmamap_unload(dmat, map); 1006 return (EFBIG); /* XXX better return value here? */ 1007 } 1008 return (0); 1009} 1010 1011int 1012_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 1013 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 1014 bus_dma_segment_t *segs, int *segp) 1015{ 1016 1017 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 1018 segs, segp)); 1019} 1020 1021/* 1022 * Utility function to load a linear buffer. segp contains 1023 * the starting segment on entrace, and the ending segment on exit. 1024 */ 1025int 1026_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1027 bus_dmamap_t map, 1028 void *buf, bus_size_t buflen, 1029 pmap_t pmap, 1030 int flags, 1031 bus_dma_segment_t *segs, 1032 int *segp) 1033{ 1034 bus_size_t sgsize; 1035 bus_addr_t curaddr; 1036 vm_offset_t vaddr; 1037 struct sync_list *sl; 1038 int error; 1039 1040 if (segs == NULL) 1041 segs = dmat->segments; 1042 1043 map->pmap = pmap; 1044 1045 if (!(map->flags & DMAMAP_COHERENT) || 1046 (dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) { 1047 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1048 if (map->pagesneeded != 0) { 1049 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1050 if (error) 1051 return (error); 1052 } 1053 } 1054 1055 sl = NULL; 1056 vaddr = (vm_offset_t)buf; 1057 1058 while (buflen > 0) { 1059 /* 1060 * Get the physical address for this segment. 1061 */ 1062 if (__predict_true(map->pmap == kernel_pmap)) 1063 curaddr = pmap_kextract(vaddr); 1064 else 1065 curaddr = pmap_extract(map->pmap, vaddr); 1066 1067 /* 1068 * Compute the segment size, and adjust counts. 1069 */ 1070 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1071 if (sgsize > dmat->maxsegsz) 1072 sgsize = dmat->maxsegsz; 1073 if (buflen < sgsize) 1074 sgsize = buflen; 1075 1076 if ((((map->flags & DMAMAP_COHERENT) == 0) || 1077 ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0)) && 1078 map->pagesneeded != 0 && run_filter(dmat, curaddr, 1079 sgsize, map->flags & DMAMAP_COHERENT)) { 1080 curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1081 sgsize); 1082 } else { 1083 sl = &map->slist[map->sync_count - 1]; 1084 if (map->sync_count == 0 || 1085#ifdef ARM_L2_PIPT 1086 curaddr != sl->busaddr + sl->datacount || 1087#endif 1088 vaddr != sl->vaddr + sl->datacount) { 1089 if (++map->sync_count > dmat->nsegments) 1090 goto cleanup; 1091 sl++; 1092 sl->vaddr = vaddr; 1093 sl->datacount = sgsize; 1094 sl->busaddr = curaddr; 1095 } else 1096 sl->datacount += sgsize; 1097 } 1098 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1099 segp); 1100 if (sgsize == 0) 1101 break; 1102 vaddr += sgsize; 1103 buflen -= sgsize; 1104 } 1105 1106cleanup: 1107 /* 1108 * Did we fit? 1109 */ 1110 if (buflen != 0) { 1111 _bus_dmamap_unload(dmat, map); 1112 return (EFBIG); /* XXX better return value here? */ 1113 } 1114 return (0); 1115} 1116 1117 1118void 1119__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1120 struct memdesc *mem, bus_dmamap_callback_t *callback, 1121 void *callback_arg) 1122{ 1123 1124 map->mem = *mem; 1125 map->dmat = dmat; 1126 map->callback = callback; 1127 map->callback_arg = callback_arg; 1128} 1129 1130bus_dma_segment_t * 1131_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1132 bus_dma_segment_t *segs, int nsegs, int error) 1133{ 1134 1135 if (segs == NULL) 1136 segs = dmat->segments; 1137 return (segs); 1138} 1139 1140/* 1141 * Release the mapping held by map. 1142 */ 1143void 1144_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1145{ 1146 struct bounce_page *bpage; 1147 struct bounce_zone *bz; 1148 1149 if ((bz = dmat->bounce_zone) != NULL) { 1150 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1151 STAILQ_REMOVE_HEAD(&map->bpages, links); 1152 free_bounce_page(dmat, bpage); 1153 } 1154 1155 bz = dmat->bounce_zone; 1156 bz->free_bpages += map->pagesreserved; 1157 bz->reserved_bpages -= map->pagesreserved; 1158 map->pagesreserved = 0; 1159 map->pagesneeded = 0; 1160 } 1161 map->sync_count = 0; 1162} 1163 1164#ifdef notyetbounceuser 1165 /* If busdma uses user pages, then the interrupt handler could 1166 * be use the kernel vm mapping. Both bounce pages and sync list 1167 * do not cross page boundaries. 1168 * Below is a rough sequence that a person would do to fix the 1169 * user page reference in the kernel vmspace. This would be 1170 * done in the dma post routine. 1171 */ 1172void 1173_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1174 pmap_t pmap, int op) 1175{ 1176 bus_size_t sgsize; 1177 bus_addr_t curaddr; 1178 vm_offset_t va; 1179 1180 /* each synclist entry is contained within a single page. 1181 * 1182 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1183 */ 1184 curaddr = pmap_extract(pmap, buf); 1185 va = pmap_dma_map(curaddr); 1186 switch (op) { 1187 case SYNC_USER_INV: 1188 cpu_dcache_wb_range(va, sgsize); 1189 break; 1190 1191 case SYNC_USER_COPYTO: 1192 bcopy((void *)va, (void *)bounce, sgsize); 1193 break; 1194 1195 case SYNC_USER_COPYFROM: 1196 bcopy((void *) bounce, (void *)va, sgsize); 1197 break; 1198 1199 default: 1200 break; 1201 } 1202 1203 pmap_dma_unmap(va); 1204} 1205#endif 1206 1207#ifdef ARM_L2_PIPT 1208#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1209#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1210#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1211#else 1212#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1213#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1214#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1215#endif 1216 1217void 1218_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1219{ 1220 struct bounce_page *bpage; 1221 struct sync_list *sl, *end; 1222 /* 1223 * If the buffer was from user space, it is possible that this is not 1224 * the same vm map, especially on a POST operation. It's not clear that 1225 * dma on userland buffers can work at all right now, certainly not if a 1226 * partial cacheline flush has to be handled. To be safe, until we're 1227 * able to test direct userland dma, panic on a map mismatch. 1228 */ 1229 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1230 if (!pmap_dmap_iscurrent(map->pmap)) 1231 panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1232 /* Handle data bouncing. */ 1233 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1234 "performing bounce", __func__, dmat, dmat->flags, op); 1235 1236 if (op & BUS_DMASYNC_PREWRITE) { 1237 while (bpage != NULL) { 1238 if (bpage->datavaddr != 0) 1239 bcopy((void *)bpage->datavaddr, 1240 (void *)bpage->vaddr, 1241 bpage->datacount); 1242 else 1243 physcopyout(bpage->dataaddr, 1244 (void *)bpage->vaddr, 1245 bpage->datacount); 1246 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1247 bpage->datacount); 1248 l2cache_wb_range((vm_offset_t)bpage->vaddr, 1249 (vm_offset_t)bpage->busaddr, 1250 bpage->datacount); 1251 bpage = STAILQ_NEXT(bpage, links); 1252 } 1253 dmat->bounce_zone->total_bounced++; 1254 } 1255 1256 if (op & BUS_DMASYNC_PREREAD) { 1257 bpage = STAILQ_FIRST(&map->bpages); 1258 while (bpage != NULL) { 1259 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1260 bpage->datacount); 1261 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1262 (vm_offset_t)bpage->busaddr, 1263 bpage->datacount); 1264 bpage = STAILQ_NEXT(bpage, links); 1265 } 1266 } 1267 if (op & BUS_DMASYNC_POSTREAD) { 1268 while (bpage != NULL) { 1269 vm_offset_t startv; 1270 vm_paddr_t startp; 1271 int len; 1272 1273 startv = bpage->vaddr &~ arm_dcache_align_mask; 1274 startp = bpage->busaddr &~ arm_dcache_align_mask; 1275 len = bpage->datacount; 1276 1277 if (startv != bpage->vaddr) 1278 len += bpage->vaddr & arm_dcache_align_mask; 1279 if (len & arm_dcache_align_mask) 1280 len = (len - 1281 (len & arm_dcache_align_mask)) + 1282 arm_dcache_align; 1283 cpu_dcache_inv_range(startv, len); 1284 l2cache_inv_range(startv, startp, len); 1285 if (bpage->datavaddr != 0) 1286 bcopy((void *)bpage->vaddr, 1287 (void *)bpage->datavaddr, 1288 bpage->datacount); 1289 else 1290 physcopyin((void *)bpage->vaddr, 1291 bpage->dataaddr, 1292 bpage->datacount); 1293 bpage = STAILQ_NEXT(bpage, links); 1294 } 1295 dmat->bounce_zone->total_bounced++; 1296 } 1297 } 1298 if (map->flags & DMAMAP_COHERENT) 1299 return; 1300 1301 if (map->sync_count != 0) { 1302 if (!pmap_dmap_iscurrent(map->pmap)) 1303 panic("_bus_dmamap_sync: wrong user map for sync."); 1304 /* ARM caches are not self-snooping for dma */ 1305 1306 sl = &map->slist[0]; 1307 end = &map->slist[map->sync_count]; 1308 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1309 "performing sync", __func__, dmat, dmat->flags, op); 1310 1311 switch (op) { 1312 case BUS_DMASYNC_PREWRITE: 1313 while (sl != end) { 1314 cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1315 l2cache_wb_range(sl->vaddr, sl->busaddr, 1316 sl->datacount); 1317 sl++; 1318 } 1319 break; 1320 1321 case BUS_DMASYNC_PREREAD: 1322 while (sl != end) { 1323 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1324 l2cache_inv_range(sl->vaddr, sl->busaddr, 1325 sl->datacount); 1326 sl++; 1327 } 1328 break; 1329 1330 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1331 while (sl != end) { 1332 cpu_dcache_wbinv_range(sl->vaddr, sl->datacount); 1333 l2cache_wbinv_range(sl->vaddr, 1334 sl->busaddr, sl->datacount); 1335 sl++; 1336 } 1337 break; 1338 1339 case BUS_DMASYNC_POSTREAD: 1340 case BUS_DMASYNC_POSTWRITE: 1341 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1342 break; 1343 default: 1344 panic("unsupported combination of sync operations: 0x%08x\n", op); 1345 break; 1346 } 1347 } 1348} 1349 1350static void 1351init_bounce_pages(void *dummy __unused) 1352{ 1353 1354 total_bpages = 0; 1355 STAILQ_INIT(&bounce_zone_list); 1356 STAILQ_INIT(&bounce_map_waitinglist); 1357 STAILQ_INIT(&bounce_map_callbacklist); 1358 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1359} 1360SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1361 1362static struct sysctl_ctx_list * 1363busdma_sysctl_tree(struct bounce_zone *bz) 1364{ 1365 return (&bz->sysctl_tree); 1366} 1367 1368static struct sysctl_oid * 1369busdma_sysctl_tree_top(struct bounce_zone *bz) 1370{ 1371 return (bz->sysctl_tree_top); 1372} 1373 1374static int 1375alloc_bounce_zone(bus_dma_tag_t dmat) 1376{ 1377 struct bounce_zone *bz; 1378 1379 /* Check to see if we already have a suitable zone */ 1380 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1381 if ((dmat->alignment <= bz->alignment) 1382 && (dmat->lowaddr >= bz->lowaddr)) { 1383 dmat->bounce_zone = bz; 1384 return (0); 1385 } 1386 } 1387 1388 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1389 M_NOWAIT | M_ZERO)) == NULL) 1390 return (ENOMEM); 1391 1392 STAILQ_INIT(&bz->bounce_page_list); 1393 bz->free_bpages = 0; 1394 bz->reserved_bpages = 0; 1395 bz->active_bpages = 0; 1396 bz->lowaddr = dmat->lowaddr; 1397 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1398 bz->map_count = 0; 1399 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1400 busdma_zonecount++; 1401 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1402 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1403 dmat->bounce_zone = bz; 1404 1405 sysctl_ctx_init(&bz->sysctl_tree); 1406 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1407 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1408 CTLFLAG_RD, 0, ""); 1409 if (bz->sysctl_tree_top == NULL) { 1410 sysctl_ctx_free(&bz->sysctl_tree); 1411 return (0); /* XXX error code? */ 1412 } 1413 1414 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1415 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1416 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1417 "Total bounce pages"); 1418 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1419 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1420 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1421 "Free bounce pages"); 1422 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1423 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1424 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1425 "Reserved bounce pages"); 1426 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1427 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1428 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1429 "Active bounce pages"); 1430 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1431 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1432 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1433 "Total bounce requests"); 1434 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1435 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1436 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1437 "Total bounce requests that were deferred"); 1438 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1439 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1440 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1441 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1442 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1443 "alignment", CTLFLAG_RD, &bz->alignment, 0, ""); 1444 1445 return (0); 1446} 1447 1448static int 1449alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1450{ 1451 struct bounce_zone *bz; 1452 int count; 1453 1454 bz = dmat->bounce_zone; 1455 count = 0; 1456 while (numpages > 0) { 1457 struct bounce_page *bpage; 1458 1459 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1460 M_NOWAIT | M_ZERO); 1461 1462 if (bpage == NULL) 1463 break; 1464 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1465 M_NOWAIT, 0ul, 1466 bz->lowaddr, 1467 PAGE_SIZE, 1468 0); 1469 if (bpage->vaddr == 0) { 1470 free(bpage, M_DEVBUF); 1471 break; 1472 } 1473 bpage->busaddr = pmap_kextract(bpage->vaddr); 1474 mtx_lock(&bounce_lock); 1475 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1476 total_bpages++; 1477 bz->total_bpages++; 1478 bz->free_bpages++; 1479 mtx_unlock(&bounce_lock); 1480 count++; 1481 numpages--; 1482 } 1483 return (count); 1484} 1485 1486static int 1487reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1488{ 1489 struct bounce_zone *bz; 1490 int pages; 1491 1492 mtx_assert(&bounce_lock, MA_OWNED); 1493 bz = dmat->bounce_zone; 1494 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1495 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1496 return (map->pagesneeded - (map->pagesreserved + pages)); 1497 bz->free_bpages -= pages; 1498 bz->reserved_bpages += pages; 1499 map->pagesreserved += pages; 1500 pages = map->pagesneeded - map->pagesreserved; 1501 1502 return (pages); 1503} 1504 1505static bus_addr_t 1506add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1507 bus_addr_t addr, bus_size_t size) 1508{ 1509 struct bounce_zone *bz; 1510 struct bounce_page *bpage; 1511 1512 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1513 KASSERT(map != NULL, 1514 ("add_bounce_page: bad map %p", map)); 1515 1516 bz = dmat->bounce_zone; 1517 if (map->pagesneeded == 0) 1518 panic("add_bounce_page: map doesn't need any pages"); 1519 map->pagesneeded--; 1520 1521 if (map->pagesreserved == 0) 1522 panic("add_bounce_page: map doesn't need any pages"); 1523 map->pagesreserved--; 1524 1525 mtx_lock(&bounce_lock); 1526 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1527 if (bpage == NULL) 1528 panic("add_bounce_page: free page list is empty"); 1529 1530 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1531 bz->reserved_bpages--; 1532 bz->active_bpages++; 1533 mtx_unlock(&bounce_lock); 1534 1535 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1536 /* Page offset needs to be preserved. */ 1537 bpage->vaddr |= vaddr & PAGE_MASK; 1538 bpage->busaddr |= vaddr & PAGE_MASK; 1539 } 1540 bpage->datavaddr = vaddr; 1541 bpage->dataaddr = addr; 1542 bpage->datacount = size; 1543 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1544 return (bpage->busaddr); 1545} 1546 1547static void 1548free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1549{ 1550 struct bus_dmamap *map; 1551 struct bounce_zone *bz; 1552 1553 bz = dmat->bounce_zone; 1554 bpage->datavaddr = 0; 1555 bpage->datacount = 0; 1556 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1557 /* 1558 * Reset the bounce page to start at offset 0. Other uses 1559 * of this bounce page may need to store a full page of 1560 * data and/or assume it starts on a page boundary. 1561 */ 1562 bpage->vaddr &= ~PAGE_MASK; 1563 bpage->busaddr &= ~PAGE_MASK; 1564 } 1565 1566 mtx_lock(&bounce_lock); 1567 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1568 bz->free_bpages++; 1569 bz->active_bpages--; 1570 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1571 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1572 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1573 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1574 map, links); 1575 busdma_swi_pending = 1; 1576 bz->total_deferred++; 1577 swi_sched(vm_ih, 0); 1578 } 1579 } 1580 mtx_unlock(&bounce_lock); 1581} 1582 1583void 1584busdma_swi(void) 1585{ 1586 bus_dma_tag_t dmat; 1587 struct bus_dmamap *map; 1588 1589 mtx_lock(&bounce_lock); 1590 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1591 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1592 mtx_unlock(&bounce_lock); 1593 dmat = map->dmat; 1594 (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_LOCK); 1595 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1596 map->callback_arg, BUS_DMA_WAITOK); 1597 (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1598 mtx_lock(&bounce_lock); 1599 } 1600 mtx_unlock(&bounce_lock); 1601} 1602