busdma_machdep-v6.c revision 269136
1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 269136 2014-07-26 18:19:43Z ian $"); 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43#include <sys/bus.h> 44#include <sys/busdma_bufalloc.h> 45#include <sys/interrupt.h> 46#include <sys/kernel.h> 47#include <sys/ktr.h> 48#include <sys/lock.h> 49#include <sys/memdesc.h> 50#include <sys/proc.h> 51#include <sys/mutex.h> 52#include <sys/sysctl.h> 53#include <sys/uio.h> 54 55#include <vm/vm.h> 56#include <vm/vm_page.h> 57#include <vm/vm_map.h> 58#include <vm/vm_extern.h> 59#include <vm/vm_kern.h> 60 61#include <machine/atomic.h> 62#include <machine/bus.h> 63#include <machine/cpufunc.h> 64#include <machine/md_var.h> 65 66#define MAX_BPAGES 64 67#define BUS_DMA_COULD_BOUNCE BUS_DMA_BUS3 68#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 69 70struct bounce_zone; 71 72struct bus_dma_tag { 73 bus_dma_tag_t parent; 74 bus_size_t alignment; 75 bus_size_t boundary; 76 bus_addr_t lowaddr; 77 bus_addr_t highaddr; 78 bus_dma_filter_t *filter; 79 void *filterarg; 80 bus_size_t maxsize; 81 u_int nsegments; 82 bus_size_t maxsegsz; 83 int flags; 84 int ref_count; 85 int map_count; 86 bus_dma_lock_t *lockfunc; 87 void *lockfuncarg; 88 struct bounce_zone *bounce_zone; 89 /* 90 * DMA range for this tag. If the page doesn't fall within 91 * one of these ranges, an error is returned. The caller 92 * may then decide what to do with the transfer. If the 93 * range pointer is NULL, it is ignored. 94 */ 95 struct arm32_dma_range *ranges; 96 int _nranges; 97 /* 98 * Most tags need one or two segments, and can use the local tagsegs 99 * array. For tags with a larger limit, we'll allocate a bigger array 100 * on first use. 101 */ 102 bus_dma_segment_t *segments; 103 bus_dma_segment_t tagsegs[2]; 104 105 106}; 107 108struct bounce_page { 109 vm_offset_t vaddr; /* kva of bounce buffer */ 110 bus_addr_t busaddr; /* Physical address */ 111 vm_offset_t datavaddr; /* kva of client data */ 112 bus_addr_t dataaddr; /* client physical address */ 113 bus_size_t datacount; /* client data count */ 114 STAILQ_ENTRY(bounce_page) links; 115}; 116 117struct sync_list { 118 vm_offset_t vaddr; /* kva of bounce buffer */ 119 bus_addr_t busaddr; /* Physical address */ 120 bus_size_t datacount; /* client data count */ 121}; 122 123int busdma_swi_pending; 124 125struct bounce_zone { 126 STAILQ_ENTRY(bounce_zone) links; 127 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 128 int total_bpages; 129 int free_bpages; 130 int reserved_bpages; 131 int active_bpages; 132 int total_bounced; 133 int total_deferred; 134 int map_count; 135 bus_size_t alignment; 136 bus_addr_t lowaddr; 137 char zoneid[8]; 138 char lowaddrid[20]; 139 struct sysctl_ctx_list sysctl_tree; 140 struct sysctl_oid *sysctl_tree_top; 141}; 142 143static struct mtx bounce_lock; 144static int total_bpages; 145static int busdma_zonecount; 146static STAILQ_HEAD(, bounce_zone) bounce_zone_list; 147 148SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 149SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 150 "Total bounce pages"); 151 152struct bus_dmamap { 153 struct bp_list bpages; 154 int pagesneeded; 155 int pagesreserved; 156 bus_dma_tag_t dmat; 157 struct memdesc mem; 158 pmap_t pmap; 159 bus_dmamap_callback_t *callback; 160 void *callback_arg; 161 int flags; 162#define DMAMAP_COHERENT (1 << 0) 163 STAILQ_ENTRY(bus_dmamap) links; 164 int sync_count; 165 struct sync_list slist[]; 166}; 167 168static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 169static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 170 171static void init_bounce_pages(void *dummy); 172static int alloc_bounce_zone(bus_dma_tag_t dmat); 173static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 174static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 175 int commit); 176static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 177 vm_offset_t vaddr, bus_addr_t addr, 178 bus_size_t size); 179static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 180int run_filter(bus_dma_tag_t dmat, bus_addr_t paddr, bus_size_t size, int coherent); 181static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 182 void *buf, bus_size_t buflen, int flags); 183static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 184 vm_paddr_t buf, bus_size_t buflen, int flags); 185static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 186 int flags); 187 188static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 189static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 190static void 191busdma_init(void *dummy) 192{ 193 int uma_flags; 194 195 uma_flags = 0; 196 197 /* Create a cache of buffers in standard (cacheable) memory. */ 198 standard_allocator = busdma_bufalloc_create("buffer", 199 arm_dcache_align, /* minimum_alignment */ 200 NULL, /* uma_alloc func */ 201 NULL, /* uma_free func */ 202 uma_flags); /* uma_zcreate_flags */ 203 204#ifdef INVARIANTS 205 /* 206 * Force UMA zone to allocate service structures like 207 * slabs using own allocator. uma_debug code performs 208 * atomic ops on uma_slab_t fields and safety of this 209 * operation is not guaranteed for write-back caches 210 */ 211 uma_flags = UMA_ZONE_OFFPAGE; 212#endif 213 /* 214 * Create a cache of buffers in uncacheable memory, to implement the 215 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 216 */ 217 coherent_allocator = busdma_bufalloc_create("coherent", 218 arm_dcache_align, /* minimum_alignment */ 219 busdma_bufalloc_alloc_uncacheable, 220 busdma_bufalloc_free_uncacheable, 221 uma_flags); /* uma_zcreate_flags */ 222} 223 224/* 225 * This init historically used SI_SUB_VM, but now the init code requires 226 * malloc(9) using M_DEVBUF memory, which is set up later than SI_SUB_VM, by 227 * SI_SUB_KMEM and SI_ORDER_THIRD, so we'll go right after that by using 228 * SI_SUB_KMEM and SI_ORDER_FOURTH. 229 */ 230SYSINIT(busdma, SI_SUB_KMEM, SI_ORDER_FOURTH, busdma_init, NULL); 231 232/* 233 * This routine checks the exclusion zone constraints from a tag against the 234 * physical RAM available on the machine. If a tag specifies an exclusion zone 235 * but there's no RAM in that zone, then we avoid allocating resources to bounce 236 * a request, and we can use any memory allocator (as opposed to needing 237 * kmem_alloc_contig() just because it can allocate pages in an address range). 238 * 239 * Most tags have BUS_SPACE_MAXADDR or BUS_SPACE_MAXADDR_32BIT (they are the 240 * same value on 32-bit architectures) as their lowaddr constraint, and we can't 241 * possibly have RAM at an address higher than the highest address we can 242 * express, so we take a fast out. 243 */ 244static __inline int 245_bus_dma_can_bounce(vm_offset_t lowaddr, vm_offset_t highaddr) 246{ 247 int i; 248 249 if (lowaddr >= BUS_SPACE_MAXADDR) 250 return (0); 251 252 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 253 if ((lowaddr >= phys_avail[i] && lowaddr <= phys_avail[i + 1]) 254 || (lowaddr < phys_avail[i] && 255 highaddr > phys_avail[i])) 256 return (1); 257 } 258 return (0); 259} 260 261static __inline struct arm32_dma_range * 262_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 263 bus_addr_t curaddr) 264{ 265 struct arm32_dma_range *dr; 266 int i; 267 268 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 269 if (curaddr >= dr->dr_sysbase && 270 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 271 return (dr); 272 } 273 274 return (NULL); 275} 276 277/* 278 * Return true if a match is made. 279 * 280 * To find a match walk the chain of bus_dma_tag_t's looking for 'paddr'. 281 * 282 * If paddr is within the bounds of the dma tag then call the filter callback 283 * to check for a match, if there is no filter callback then assume a match. 284 */ 285int 286run_filter(bus_dma_tag_t dmat, bus_addr_t paddr, bus_size_t size, int coherent) 287{ 288 int retval; 289 290 retval = 0; 291 292 do { 293 if (((paddr > dmat->lowaddr && paddr <= dmat->highaddr) 294 || ((paddr & (dmat->alignment - 1)) != 0) || 295 (!coherent && (size & arm_dcache_align_mask)) || 296 (!coherent && (paddr & arm_dcache_align_mask))) 297 && (dmat->filter == NULL 298 || (*dmat->filter)(dmat->filterarg, paddr) != 0)) 299 retval = 1; 300 301 dmat = dmat->parent; 302 } while (retval == 0 && dmat != NULL); 303 return (retval); 304} 305 306/* 307 * Convenience function for manipulating driver locks from busdma (during 308 * busdma_swi, for example). Drivers that don't provide their own locks 309 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 310 * non-mutex locking scheme don't have to use this at all. 311 */ 312void 313busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 314{ 315 struct mtx *dmtx; 316 317 dmtx = (struct mtx *)arg; 318 switch (op) { 319 case BUS_DMA_LOCK: 320 mtx_lock(dmtx); 321 break; 322 case BUS_DMA_UNLOCK: 323 mtx_unlock(dmtx); 324 break; 325 default: 326 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 327 } 328} 329 330/* 331 * dflt_lock should never get called. It gets put into the dma tag when 332 * lockfunc == NULL, which is only valid if the maps that are associated 333 * with the tag are meant to never be defered. 334 * XXX Should have a way to identify which driver is responsible here. 335 */ 336static void 337dflt_lock(void *arg, bus_dma_lock_op_t op) 338{ 339 panic("driver error: busdma dflt_lock called"); 340} 341 342/* 343 * Allocate a device specific dma_tag. 344 */ 345int 346bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 347 bus_size_t boundary, bus_addr_t lowaddr, 348 bus_addr_t highaddr, bus_dma_filter_t *filter, 349 void *filterarg, bus_size_t maxsize, int nsegments, 350 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 351 void *lockfuncarg, bus_dma_tag_t *dmat) 352{ 353 bus_dma_tag_t newtag; 354 int error = 0; 355 356#if 0 357 if (!parent) 358 parent = arm_root_dma_tag; 359#endif 360 361 /* Basic sanity checking */ 362 if (boundary != 0 && boundary < maxsegsz) 363 maxsegsz = boundary; 364 365 /* Return a NULL tag on failure */ 366 *dmat = NULL; 367 368 if (maxsegsz == 0) { 369 return (EINVAL); 370 } 371 372 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 373 M_ZERO | M_NOWAIT); 374 if (newtag == NULL) { 375 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 376 __func__, newtag, 0, error); 377 return (ENOMEM); 378 } 379 380 newtag->parent = parent; 381 newtag->alignment = alignment; 382 newtag->boundary = boundary; 383 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 384 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 385 (PAGE_SIZE - 1); 386 newtag->filter = filter; 387 newtag->filterarg = filterarg; 388 newtag->maxsize = maxsize; 389 newtag->nsegments = nsegments; 390 newtag->maxsegsz = maxsegsz; 391 newtag->flags = flags; 392 newtag->ref_count = 1; /* Count ourself */ 393 newtag->map_count = 0; 394 newtag->ranges = bus_dma_get_range(); 395 newtag->_nranges = bus_dma_get_range_nb(); 396 if (lockfunc != NULL) { 397 newtag->lockfunc = lockfunc; 398 newtag->lockfuncarg = lockfuncarg; 399 } else { 400 newtag->lockfunc = dflt_lock; 401 newtag->lockfuncarg = NULL; 402 } 403 /* 404 * If all the segments we need fit into the local tagsegs array, set the 405 * pointer now. Otherwise NULL the pointer and an array of segments 406 * will be allocated later, on first use. We don't pre-allocate now 407 * because some tags exist just to pass contraints to children in the 408 * device hierarchy, and they tend to use BUS_SPACE_UNRESTRICTED and we 409 * sure don't want to try to allocate an array for that. 410 */ 411 if (newtag->nsegments <= nitems(newtag->tagsegs)) 412 newtag->segments = newtag->tagsegs; 413 else 414 newtag->segments = NULL; 415 416 /* Take into account any restrictions imposed by our parent tag */ 417 if (parent != NULL) { 418 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 419 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 420 if (newtag->boundary == 0) 421 newtag->boundary = parent->boundary; 422 else if (parent->boundary != 0) 423 newtag->boundary = MIN(parent->boundary, 424 newtag->boundary); 425 if ((newtag->filter != NULL) || 426 ((parent->flags & BUS_DMA_COULD_BOUNCE) != 0)) 427 newtag->flags |= BUS_DMA_COULD_BOUNCE; 428 if (newtag->filter == NULL) { 429 /* 430 * Short circuit looking at our parent directly 431 * since we have encapsulated all of its information 432 */ 433 newtag->filter = parent->filter; 434 newtag->filterarg = parent->filterarg; 435 newtag->parent = parent->parent; 436 } 437 if (newtag->parent != NULL) 438 atomic_add_int(&parent->ref_count, 1); 439 } 440 441 if (_bus_dma_can_bounce(newtag->lowaddr, newtag->highaddr) 442 || newtag->alignment > 1) 443 newtag->flags |= BUS_DMA_COULD_BOUNCE; 444 445 /* 446 * Any request can auto-bounce due to cacheline alignment, in addition 447 * to any alignment or boundary specifications in the tag, so if the 448 * ALLOCNOW flag is set, there's always work to do. 449 */ 450 if ((flags & BUS_DMA_ALLOCNOW) != 0) { 451 struct bounce_zone *bz; 452 /* 453 * Round size up to a full page, and add one more page because 454 * there can always be one more boundary crossing than the 455 * number of pages in a transfer. 456 */ 457 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 458 459 if ((error = alloc_bounce_zone(newtag)) != 0) { 460 free(newtag, M_DEVBUF); 461 return (error); 462 } 463 bz = newtag->bounce_zone; 464 465 if (ptoa(bz->total_bpages) < maxsize) { 466 int pages; 467 468 pages = atop(maxsize) - bz->total_bpages; 469 470 /* Add pages to our bounce pool */ 471 if (alloc_bounce_pages(newtag, pages) < pages) 472 error = ENOMEM; 473 } 474 /* Performed initial allocation */ 475 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 476 } else 477 newtag->bounce_zone = NULL; 478 479 if (error != 0) { 480 free(newtag, M_DEVBUF); 481 } else { 482 *dmat = newtag; 483 } 484 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 485 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 486 return (error); 487} 488 489int 490bus_dma_tag_destroy(bus_dma_tag_t dmat) 491{ 492 bus_dma_tag_t dmat_copy; 493 int error; 494 495 error = 0; 496 dmat_copy = dmat; 497 498 if (dmat != NULL) { 499 500 if (dmat->map_count != 0) { 501 error = EBUSY; 502 goto out; 503 } 504 505 while (dmat != NULL) { 506 bus_dma_tag_t parent; 507 508 parent = dmat->parent; 509 atomic_subtract_int(&dmat->ref_count, 1); 510 if (dmat->ref_count == 0) { 511 if (dmat->segments != NULL && 512 dmat->segments != dmat->tagsegs) 513 free(dmat->segments, M_DEVBUF); 514 free(dmat, M_DEVBUF); 515 /* 516 * Last reference count, so 517 * release our reference 518 * count on our parent. 519 */ 520 dmat = parent; 521 } else 522 dmat = NULL; 523 } 524 } 525out: 526 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 527 return (error); 528} 529 530static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 531{ 532 struct bounce_zone *bz; 533 int maxpages; 534 int error; 535 536 if (dmat->bounce_zone == NULL) 537 if ((error = alloc_bounce_zone(dmat)) != 0) 538 return (error); 539 bz = dmat->bounce_zone; 540 /* Initialize the new map */ 541 STAILQ_INIT(&(mapp->bpages)); 542 543 /* 544 * Attempt to add pages to our pool on a per-instance basis up to a sane 545 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 546 * alignment and boundary constraints, it could still auto-bounce due to 547 * cacheline alignment, which requires at most two bounce pages. 548 */ 549 if (dmat->flags & BUS_DMA_COULD_BOUNCE) 550 maxpages = MAX_BPAGES; 551 else 552 maxpages = 2 * bz->map_count; 553 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 554 || (bz->map_count > 0 && bz->total_bpages < maxpages)) { 555 int pages; 556 557 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 558 pages = MIN(maxpages - bz->total_bpages, pages); 559 pages = MAX(pages, 2); 560 if (alloc_bounce_pages(dmat, pages) < pages) 561 return (ENOMEM); 562 563 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 564 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 565 } 566 bz->map_count++; 567 return (0); 568} 569 570/* 571 * Allocate a handle for mapping from kva/uva/physical 572 * address space into bus device space. 573 */ 574int 575bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 576{ 577 int mapsize; 578 int error = 0; 579 580 mapsize = sizeof(**mapp) + (sizeof(struct sync_list) * dmat->nsegments); 581 *mapp = (bus_dmamap_t)malloc(mapsize, M_DEVBUF, M_NOWAIT | M_ZERO); 582 if (*mapp == NULL) { 583 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 584 return (ENOMEM); 585 } 586 (*mapp)->sync_count = 0; 587 588 if (dmat->segments == NULL) { 589 dmat->segments = (bus_dma_segment_t *)malloc( 590 sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF, 591 M_NOWAIT); 592 if (dmat->segments == NULL) { 593 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 594 __func__, dmat, ENOMEM); 595 free(*mapp, M_DEVBUF); 596 *mapp = NULL; 597 return (ENOMEM); 598 } 599 } 600 /* 601 * Bouncing might be required if the driver asks for an active 602 * exclusion region, a data alignment that is stricter than 1, and/or 603 * an active address boundary. 604 */ 605 error = allocate_bz_and_pages(dmat, *mapp); 606 if (error != 0) { 607 free(*mapp, M_DEVBUF); 608 *mapp = NULL; 609 return (error); 610 } 611 return (error); 612} 613 614/* 615 * Destroy a handle for mapping from kva/uva/physical 616 * address space into bus device space. 617 */ 618int 619bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 620{ 621 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 622 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 623 __func__, dmat, EBUSY); 624 return (EBUSY); 625 } 626 if (dmat->bounce_zone) 627 dmat->bounce_zone->map_count--; 628 free(map, M_DEVBUF); 629 dmat->map_count--; 630 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 631 return (0); 632} 633 634 635/* 636 * Allocate a piece of memory that can be efficiently mapped into 637 * bus device space based on the constraints lited in the dma tag. 638 * A dmamap to for use with dmamap_load is also allocated. 639 */ 640int 641bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 642 bus_dmamap_t *mapp) 643{ 644 busdma_bufalloc_t ba; 645 struct busdma_bufzone *bufzone; 646 vm_memattr_t memattr; 647 int mflags; 648 int mapsize; 649 int error; 650 651 if (flags & BUS_DMA_NOWAIT) 652 mflags = M_NOWAIT; 653 else 654 mflags = M_WAITOK; 655 656 /* ARM non-snooping caches need a map for the VA cache sync structure */ 657 658 mapsize = sizeof(**mapp) + (sizeof(struct sync_list) * dmat->nsegments); 659 *mapp = (bus_dmamap_t)malloc(mapsize, M_DEVBUF, M_NOWAIT | M_ZERO); 660 if (*mapp == NULL) { 661 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 662 __func__, dmat, dmat->flags, ENOMEM); 663 return (ENOMEM); 664 } 665 666 (*mapp)->sync_count = 0; 667 /* We may need bounce pages, even for allocated memory */ 668 error = allocate_bz_and_pages(dmat, *mapp); 669 if (error != 0) { 670 free(*mapp, M_DEVBUF); 671 *mapp = NULL; 672 return (error); 673 } 674 675 if (dmat->segments == NULL) { 676 dmat->segments = (bus_dma_segment_t *)malloc( 677 sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF, 678 mflags); 679 if (dmat->segments == NULL) { 680 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 681 __func__, dmat, dmat->flags, ENOMEM); 682 free(*mapp, M_DEVBUF); 683 *mapp = NULL; 684 return (ENOMEM); 685 } 686 } 687 688 if (flags & BUS_DMA_ZERO) 689 mflags |= M_ZERO; 690 if (flags & BUS_DMA_COHERENT) { 691 memattr = VM_MEMATTR_UNCACHEABLE; 692 ba = coherent_allocator; 693 (*mapp)->flags |= DMAMAP_COHERENT; 694 } else { 695 memattr = VM_MEMATTR_DEFAULT; 696 ba = standard_allocator; 697 (*mapp)->flags = 0; 698 } 699 700 /* 701 * Try to find a bufzone in the allocator that holds a cache of buffers 702 * of the right size for this request. If the buffer is too big to be 703 * held in the allocator cache, this returns NULL. 704 */ 705 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 706 707 /* 708 * Allocate the buffer from the uma(9) allocator if... 709 * - It's small enough to be in the allocator (bufzone not NULL). 710 * - The alignment constraint isn't larger than the allocation size 711 * (the allocator aligns buffers to their size boundaries). 712 * - There's no need to handle lowaddr/highaddr exclusion zones. 713 * else allocate non-contiguous pages if... 714 * - The page count that could get allocated doesn't exceed nsegments. 715 * - The alignment constraint isn't larger than a page boundary. 716 * - There are no boundary-crossing constraints. 717 * else allocate a block of contiguous pages because one or more of the 718 * constraints is something that only the contig allocator can fulfill. 719 */ 720 if (bufzone != NULL && dmat->alignment <= bufzone->size && 721 !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr)) { 722 *vaddr = uma_zalloc(bufzone->umazone, mflags); 723 } else if (dmat->nsegments >= btoc(dmat->maxsize) && 724 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 725 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 726 mflags, 0, dmat->lowaddr, memattr); 727 } else { 728 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 729 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 730 memattr); 731 } 732 733 734 if (*vaddr == NULL) { 735 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 736 __func__, dmat, dmat->flags, ENOMEM); 737 free(*mapp, M_DEVBUF); 738 *mapp = NULL; 739 return (ENOMEM); 740 } 741 dmat->map_count++; 742 743 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 744 __func__, dmat, dmat->flags, 0); 745 return (0); 746} 747 748/* 749 * Free a piece of memory and it's allociated dmamap, that was allocated 750 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 751 */ 752void 753bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 754{ 755 struct busdma_bufzone *bufzone; 756 busdma_bufalloc_t ba; 757 758 if (map->flags & DMAMAP_COHERENT) 759 ba = coherent_allocator; 760 else 761 ba = standard_allocator; 762 763 /* Be careful not to access map from here on. */ 764 765 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 766 767 if (bufzone != NULL && dmat->alignment <= bufzone->size && 768 !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr)) 769 uma_zfree(bufzone->umazone, vaddr); 770 else 771 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 772 773 dmat->map_count--; 774 free(map, M_DEVBUF); 775 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 776} 777 778static void 779_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 780 bus_size_t buflen, int flags) 781{ 782 bus_addr_t curaddr; 783 bus_size_t sgsize; 784 785 if (map->pagesneeded == 0) { 786 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 787 " map= %p, pagesneeded= %d", 788 dmat->lowaddr, dmat->boundary, dmat->alignment, 789 map, map->pagesneeded); 790 /* 791 * Count the number of bounce pages 792 * needed in order to complete this transfer 793 */ 794 curaddr = buf; 795 while (buflen != 0) { 796 sgsize = MIN(buflen, dmat->maxsegsz); 797 if (run_filter(dmat, curaddr, sgsize, 798 map->flags & DMAMAP_COHERENT) != 0) { 799 sgsize = MIN(sgsize, PAGE_SIZE); 800 map->pagesneeded++; 801 } 802 curaddr += sgsize; 803 buflen -= sgsize; 804 } 805 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 806 } 807} 808 809static void 810_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 811 void *buf, bus_size_t buflen, int flags) 812{ 813 vm_offset_t vaddr; 814 vm_offset_t vendaddr; 815 bus_addr_t paddr; 816 817 if (map->pagesneeded == 0) { 818 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 819 " map= %p, pagesneeded= %d", 820 dmat->lowaddr, dmat->boundary, dmat->alignment, 821 map, map->pagesneeded); 822 /* 823 * Count the number of bounce pages 824 * needed in order to complete this transfer 825 */ 826 vaddr = (vm_offset_t)buf; 827 vendaddr = (vm_offset_t)buf + buflen; 828 829 while (vaddr < vendaddr) { 830 if (__predict_true(map->pmap == kernel_pmap)) 831 paddr = pmap_kextract(vaddr); 832 else 833 paddr = pmap_extract(map->pmap, vaddr); 834 if (run_filter(dmat, paddr, 835 min(vendaddr - vaddr, 836 (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK))), 837 map->flags & DMAMAP_COHERENT) != 0) { 838 map->pagesneeded++; 839 } 840 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 841 842 } 843 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 844 } 845} 846 847static int 848_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 849{ 850 851 /* Reserve Necessary Bounce Pages */ 852 mtx_lock(&bounce_lock); 853 if (flags & BUS_DMA_NOWAIT) { 854 if (reserve_bounce_pages(dmat, map, 0) != 0) { 855 map->pagesneeded = 0; 856 mtx_unlock(&bounce_lock); 857 return (ENOMEM); 858 } 859 } else { 860 if (reserve_bounce_pages(dmat, map, 1) != 0) { 861 /* Queue us for resources */ 862 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 863 mtx_unlock(&bounce_lock); 864 return (EINPROGRESS); 865 } 866 } 867 mtx_unlock(&bounce_lock); 868 869 return (0); 870} 871 872/* 873 * Add a single contiguous physical range to the segment list. 874 */ 875static int 876_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 877 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 878{ 879 bus_addr_t baddr, bmask; 880 int seg; 881 882 /* 883 * Make sure we don't cross any boundaries. 884 */ 885 bmask = ~(dmat->boundary - 1); 886 if (dmat->boundary > 0) { 887 baddr = (curaddr + dmat->boundary) & bmask; 888 if (sgsize > (baddr - curaddr)) 889 sgsize = (baddr - curaddr); 890 } 891 892 if (dmat->ranges) { 893 struct arm32_dma_range *dr; 894 895 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 896 curaddr); 897 if (dr == NULL) { 898 _bus_dmamap_unload(dmat, map); 899 return (0); 900 } 901 /* 902 * In a valid DMA range. Translate the physical 903 * memory address to an address in the DMA window. 904 */ 905 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 906 } 907 908 /* 909 * Insert chunk into a segment, coalescing with 910 * previous segment if possible. 911 */ 912 seg = *segp; 913 if (seg == -1) { 914 seg = 0; 915 segs[seg].ds_addr = curaddr; 916 segs[seg].ds_len = sgsize; 917 } else { 918 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 919 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 920 (dmat->boundary == 0 || 921 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 922 segs[seg].ds_len += sgsize; 923 else { 924 if (++seg >= dmat->nsegments) 925 return (0); 926 segs[seg].ds_addr = curaddr; 927 segs[seg].ds_len = sgsize; 928 } 929 } 930 *segp = seg; 931 return (sgsize); 932} 933 934/* 935 * Utility function to load a physical buffer. segp contains 936 * the starting segment on entrace, and the ending segment on exit. 937 */ 938int 939_bus_dmamap_load_phys(bus_dma_tag_t dmat, 940 bus_dmamap_t map, 941 vm_paddr_t buf, bus_size_t buflen, 942 int flags, 943 bus_dma_segment_t *segs, 944 int *segp) 945{ 946 bus_addr_t curaddr; 947 bus_size_t sgsize; 948 int error; 949 950 if (segs == NULL) 951 segs = dmat->segments; 952 953 if (((map->flags & DMAMAP_COHERENT) == 0) || 954 (dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) { 955 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 956 if (map->pagesneeded != 0) { 957 error = _bus_dmamap_reserve_pages(dmat, map, flags); 958 if (error) 959 return (error); 960 } 961 } 962 963 while (buflen > 0) { 964 curaddr = buf; 965 sgsize = MIN(buflen, dmat->maxsegsz); 966 if ((((map->flags & DMAMAP_COHERENT) == 0) || 967 ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0)) && 968 map->pagesneeded != 0 && run_filter(dmat, curaddr, 969 sgsize, map->flags & DMAMAP_COHERENT)) { 970 sgsize = MIN(sgsize, PAGE_SIZE); 971 curaddr = add_bounce_page(dmat, map, 0, curaddr, 972 sgsize); 973 } 974 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 975 segp); 976 if (sgsize == 0) 977 break; 978 buf += sgsize; 979 buflen -= sgsize; 980 } 981 982 /* 983 * Did we fit? 984 */ 985 if (buflen != 0) { 986 _bus_dmamap_unload(dmat, map); 987 return (EFBIG); /* XXX better return value here? */ 988 } 989 return (0); 990} 991 992int 993_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 994 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 995 bus_dma_segment_t *segs, int *segp) 996{ 997 998 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 999 segs, segp)); 1000} 1001 1002/* 1003 * Utility function to load a linear buffer. segp contains 1004 * the starting segment on entrace, and the ending segment on exit. 1005 */ 1006int 1007_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1008 bus_dmamap_t map, 1009 void *buf, bus_size_t buflen, 1010 pmap_t pmap, 1011 int flags, 1012 bus_dma_segment_t *segs, 1013 int *segp) 1014{ 1015 bus_size_t sgsize; 1016 bus_addr_t curaddr; 1017 vm_offset_t vaddr; 1018 struct sync_list *sl; 1019 int error; 1020 1021 if (segs == NULL) 1022 segs = dmat->segments; 1023 1024 map->pmap = pmap; 1025 1026 if (!(map->flags & DMAMAP_COHERENT) || 1027 (dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) { 1028 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1029 if (map->pagesneeded != 0) { 1030 error = _bus_dmamap_reserve_pages(dmat, map, flags); 1031 if (error) 1032 return (error); 1033 } 1034 } 1035 1036 sl = NULL; 1037 vaddr = (vm_offset_t)buf; 1038 1039 while (buflen > 0) { 1040 /* 1041 * Get the physical address for this segment. 1042 */ 1043 if (__predict_true(map->pmap == kernel_pmap)) 1044 curaddr = pmap_kextract(vaddr); 1045 else 1046 curaddr = pmap_extract(map->pmap, vaddr); 1047 1048 /* 1049 * Compute the segment size, and adjust counts. 1050 */ 1051 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1052 if (sgsize > dmat->maxsegsz) 1053 sgsize = dmat->maxsegsz; 1054 if (buflen < sgsize) 1055 sgsize = buflen; 1056 1057 if ((((map->flags & DMAMAP_COHERENT) == 0) || 1058 ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0)) && 1059 map->pagesneeded != 0 && run_filter(dmat, curaddr, 1060 sgsize, map->flags & DMAMAP_COHERENT)) { 1061 curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1062 sgsize); 1063 } else { 1064 sl = &map->slist[map->sync_count - 1]; 1065 if (map->sync_count == 0 || 1066#ifdef ARM_L2_PIPT 1067 curaddr != sl->busaddr + sl->datacount || 1068#endif 1069 vaddr != sl->vaddr + sl->datacount) { 1070 if (++map->sync_count > dmat->nsegments) 1071 goto cleanup; 1072 sl++; 1073 sl->vaddr = vaddr; 1074 sl->datacount = sgsize; 1075 sl->busaddr = curaddr; 1076 } else 1077 sl->datacount += sgsize; 1078 } 1079 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1080 segp); 1081 if (sgsize == 0) 1082 break; 1083 vaddr += sgsize; 1084 buflen -= sgsize; 1085 } 1086 1087cleanup: 1088 /* 1089 * Did we fit? 1090 */ 1091 if (buflen != 0) { 1092 _bus_dmamap_unload(dmat, map); 1093 return (EFBIG); /* XXX better return value here? */ 1094 } 1095 return (0); 1096} 1097 1098 1099void 1100__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1101 struct memdesc *mem, bus_dmamap_callback_t *callback, 1102 void *callback_arg) 1103{ 1104 1105 map->mem = *mem; 1106 map->dmat = dmat; 1107 map->callback = callback; 1108 map->callback_arg = callback_arg; 1109} 1110 1111bus_dma_segment_t * 1112_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1113 bus_dma_segment_t *segs, int nsegs, int error) 1114{ 1115 1116 if (segs == NULL) 1117 segs = dmat->segments; 1118 return (segs); 1119} 1120 1121/* 1122 * Release the mapping held by map. 1123 */ 1124void 1125_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1126{ 1127 struct bounce_page *bpage; 1128 struct bounce_zone *bz; 1129 1130 if ((bz = dmat->bounce_zone) != NULL) { 1131 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1132 STAILQ_REMOVE_HEAD(&map->bpages, links); 1133 free_bounce_page(dmat, bpage); 1134 } 1135 1136 bz = dmat->bounce_zone; 1137 bz->free_bpages += map->pagesreserved; 1138 bz->reserved_bpages -= map->pagesreserved; 1139 map->pagesreserved = 0; 1140 map->pagesneeded = 0; 1141 } 1142 map->sync_count = 0; 1143} 1144 1145#ifdef notyetbounceuser 1146 /* If busdma uses user pages, then the interrupt handler could 1147 * be use the kernel vm mapping. Both bounce pages and sync list 1148 * do not cross page boundaries. 1149 * Below is a rough sequence that a person would do to fix the 1150 * user page reference in the kernel vmspace. This would be 1151 * done in the dma post routine. 1152 */ 1153void 1154_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1155 pmap_t pmap, int op) 1156{ 1157 bus_size_t sgsize; 1158 bus_addr_t curaddr; 1159 vm_offset_t va; 1160 1161 /* each synclist entry is contained within a single page. 1162 * 1163 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1164 */ 1165 curaddr = pmap_extract(pmap, buf); 1166 va = pmap_dma_map(curaddr); 1167 switch (op) { 1168 case SYNC_USER_INV: 1169 cpu_dcache_wb_range(va, sgsize); 1170 break; 1171 1172 case SYNC_USER_COPYTO: 1173 bcopy((void *)va, (void *)bounce, sgsize); 1174 break; 1175 1176 case SYNC_USER_COPYFROM: 1177 bcopy((void *) bounce, (void *)va, sgsize); 1178 break; 1179 1180 default: 1181 break; 1182 } 1183 1184 pmap_dma_unmap(va); 1185} 1186#endif 1187 1188#ifdef ARM_L2_PIPT 1189#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1190#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1191#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1192#else 1193#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1194#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1195#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1196#endif 1197 1198void 1199_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1200{ 1201 struct bounce_page *bpage; 1202 struct sync_list *sl, *end; 1203 /* 1204 * If the buffer was from user space, it is possible that this is not 1205 * the same vm map, especially on a POST operation. It's not clear that 1206 * dma on userland buffers can work at all right now, certainly not if a 1207 * partial cacheline flush has to be handled. To be safe, until we're 1208 * able to test direct userland dma, panic on a map mismatch. 1209 */ 1210 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1211 if (!pmap_dmap_iscurrent(map->pmap)) 1212 panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1213 /* Handle data bouncing. */ 1214 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1215 "performing bounce", __func__, dmat, dmat->flags, op); 1216 1217 if (op & BUS_DMASYNC_PREWRITE) { 1218 while (bpage != NULL) { 1219 if (bpage->datavaddr != 0) 1220 bcopy((void *)bpage->datavaddr, 1221 (void *)bpage->vaddr, 1222 bpage->datacount); 1223 else 1224 physcopyout(bpage->dataaddr, 1225 (void *)bpage->vaddr, 1226 bpage->datacount); 1227 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1228 bpage->datacount); 1229 l2cache_wb_range((vm_offset_t)bpage->vaddr, 1230 (vm_offset_t)bpage->busaddr, 1231 bpage->datacount); 1232 bpage = STAILQ_NEXT(bpage, links); 1233 } 1234 dmat->bounce_zone->total_bounced++; 1235 } 1236 1237 if (op & BUS_DMASYNC_PREREAD) { 1238 bpage = STAILQ_FIRST(&map->bpages); 1239 while (bpage != NULL) { 1240 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1241 bpage->datacount); 1242 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1243 (vm_offset_t)bpage->busaddr, 1244 bpage->datacount); 1245 bpage = STAILQ_NEXT(bpage, links); 1246 } 1247 } 1248 if (op & BUS_DMASYNC_POSTREAD) { 1249 while (bpage != NULL) { 1250 vm_offset_t startv; 1251 vm_paddr_t startp; 1252 int len; 1253 1254 startv = bpage->vaddr &~ arm_dcache_align_mask; 1255 startp = bpage->busaddr &~ arm_dcache_align_mask; 1256 len = bpage->datacount; 1257 1258 if (startv != bpage->vaddr) 1259 len += bpage->vaddr & arm_dcache_align_mask; 1260 if (len & arm_dcache_align_mask) 1261 len = (len - 1262 (len & arm_dcache_align_mask)) + 1263 arm_dcache_align; 1264 cpu_dcache_inv_range(startv, len); 1265 l2cache_inv_range(startv, startp, len); 1266 if (bpage->datavaddr != 0) 1267 bcopy((void *)bpage->vaddr, 1268 (void *)bpage->datavaddr, 1269 bpage->datacount); 1270 else 1271 physcopyin((void *)bpage->vaddr, 1272 bpage->dataaddr, 1273 bpage->datacount); 1274 bpage = STAILQ_NEXT(bpage, links); 1275 } 1276 dmat->bounce_zone->total_bounced++; 1277 } 1278 } 1279 if (map->flags & DMAMAP_COHERENT) 1280 return; 1281 1282 if (map->sync_count != 0) { 1283 if (!pmap_dmap_iscurrent(map->pmap)) 1284 panic("_bus_dmamap_sync: wrong user map for sync."); 1285 /* ARM caches are not self-snooping for dma */ 1286 1287 sl = &map->slist[0]; 1288 end = &map->slist[map->sync_count]; 1289 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1290 "performing sync", __func__, dmat, dmat->flags, op); 1291 1292 switch (op) { 1293 case BUS_DMASYNC_PREWRITE: 1294 while (sl != end) { 1295 cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1296 l2cache_wb_range(sl->vaddr, sl->busaddr, 1297 sl->datacount); 1298 sl++; 1299 } 1300 break; 1301 1302 case BUS_DMASYNC_PREREAD: 1303 while (sl != end) { 1304 cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1305 l2cache_inv_range(sl->vaddr, sl->busaddr, 1306 sl->datacount); 1307 sl++; 1308 } 1309 break; 1310 1311 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1312 while (sl != end) { 1313 cpu_dcache_wbinv_range(sl->vaddr, sl->datacount); 1314 l2cache_wbinv_range(sl->vaddr, 1315 sl->busaddr, sl->datacount); 1316 sl++; 1317 } 1318 break; 1319 1320 case BUS_DMASYNC_POSTREAD: 1321 case BUS_DMASYNC_POSTWRITE: 1322 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1323 break; 1324 default: 1325 panic("unsupported combination of sync operations: 0x%08x\n", op); 1326 break; 1327 } 1328 } 1329} 1330 1331static void 1332init_bounce_pages(void *dummy __unused) 1333{ 1334 1335 total_bpages = 0; 1336 STAILQ_INIT(&bounce_zone_list); 1337 STAILQ_INIT(&bounce_map_waitinglist); 1338 STAILQ_INIT(&bounce_map_callbacklist); 1339 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1340} 1341SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1342 1343static struct sysctl_ctx_list * 1344busdma_sysctl_tree(struct bounce_zone *bz) 1345{ 1346 return (&bz->sysctl_tree); 1347} 1348 1349static struct sysctl_oid * 1350busdma_sysctl_tree_top(struct bounce_zone *bz) 1351{ 1352 return (bz->sysctl_tree_top); 1353} 1354 1355static int 1356alloc_bounce_zone(bus_dma_tag_t dmat) 1357{ 1358 struct bounce_zone *bz; 1359 1360 /* Check to see if we already have a suitable zone */ 1361 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1362 if ((dmat->alignment <= bz->alignment) 1363 && (dmat->lowaddr >= bz->lowaddr)) { 1364 dmat->bounce_zone = bz; 1365 return (0); 1366 } 1367 } 1368 1369 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1370 M_NOWAIT | M_ZERO)) == NULL) 1371 return (ENOMEM); 1372 1373 STAILQ_INIT(&bz->bounce_page_list); 1374 bz->free_bpages = 0; 1375 bz->reserved_bpages = 0; 1376 bz->active_bpages = 0; 1377 bz->lowaddr = dmat->lowaddr; 1378 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1379 bz->map_count = 0; 1380 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1381 busdma_zonecount++; 1382 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1383 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1384 dmat->bounce_zone = bz; 1385 1386 sysctl_ctx_init(&bz->sysctl_tree); 1387 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1388 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1389 CTLFLAG_RD, 0, ""); 1390 if (bz->sysctl_tree_top == NULL) { 1391 sysctl_ctx_free(&bz->sysctl_tree); 1392 return (0); /* XXX error code? */ 1393 } 1394 1395 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1396 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1397 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1398 "Total bounce pages"); 1399 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1400 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1401 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1402 "Free bounce pages"); 1403 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1404 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1405 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1406 "Reserved bounce pages"); 1407 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1408 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1409 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1410 "Active bounce pages"); 1411 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1412 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1413 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1414 "Total bounce requests"); 1415 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1416 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1417 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1418 "Total bounce requests that were deferred"); 1419 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1420 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1421 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1422 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1423 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1424 "alignment", CTLFLAG_RD, &bz->alignment, 0, ""); 1425 1426 return (0); 1427} 1428 1429static int 1430alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1431{ 1432 struct bounce_zone *bz; 1433 int count; 1434 1435 bz = dmat->bounce_zone; 1436 count = 0; 1437 while (numpages > 0) { 1438 struct bounce_page *bpage; 1439 1440 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1441 M_NOWAIT | M_ZERO); 1442 1443 if (bpage == NULL) 1444 break; 1445 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1446 M_NOWAIT, 0ul, 1447 bz->lowaddr, 1448 PAGE_SIZE, 1449 0); 1450 if (bpage->vaddr == 0) { 1451 free(bpage, M_DEVBUF); 1452 break; 1453 } 1454 bpage->busaddr = pmap_kextract(bpage->vaddr); 1455 mtx_lock(&bounce_lock); 1456 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1457 total_bpages++; 1458 bz->total_bpages++; 1459 bz->free_bpages++; 1460 mtx_unlock(&bounce_lock); 1461 count++; 1462 numpages--; 1463 } 1464 return (count); 1465} 1466 1467static int 1468reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1469{ 1470 struct bounce_zone *bz; 1471 int pages; 1472 1473 mtx_assert(&bounce_lock, MA_OWNED); 1474 bz = dmat->bounce_zone; 1475 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1476 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1477 return (map->pagesneeded - (map->pagesreserved + pages)); 1478 bz->free_bpages -= pages; 1479 bz->reserved_bpages += pages; 1480 map->pagesreserved += pages; 1481 pages = map->pagesneeded - map->pagesreserved; 1482 1483 return (pages); 1484} 1485 1486static bus_addr_t 1487add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1488 bus_addr_t addr, bus_size_t size) 1489{ 1490 struct bounce_zone *bz; 1491 struct bounce_page *bpage; 1492 1493 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1494 KASSERT(map != NULL, 1495 ("add_bounce_page: bad map %p", map)); 1496 1497 bz = dmat->bounce_zone; 1498 if (map->pagesneeded == 0) 1499 panic("add_bounce_page: map doesn't need any pages"); 1500 map->pagesneeded--; 1501 1502 if (map->pagesreserved == 0) 1503 panic("add_bounce_page: map doesn't need any pages"); 1504 map->pagesreserved--; 1505 1506 mtx_lock(&bounce_lock); 1507 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1508 if (bpage == NULL) 1509 panic("add_bounce_page: free page list is empty"); 1510 1511 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1512 bz->reserved_bpages--; 1513 bz->active_bpages++; 1514 mtx_unlock(&bounce_lock); 1515 1516 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1517 /* Page offset needs to be preserved. */ 1518 bpage->vaddr |= vaddr & PAGE_MASK; 1519 bpage->busaddr |= vaddr & PAGE_MASK; 1520 } 1521 bpage->datavaddr = vaddr; 1522 bpage->dataaddr = addr; 1523 bpage->datacount = size; 1524 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1525 return (bpage->busaddr); 1526} 1527 1528static void 1529free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1530{ 1531 struct bus_dmamap *map; 1532 struct bounce_zone *bz; 1533 1534 bz = dmat->bounce_zone; 1535 bpage->datavaddr = 0; 1536 bpage->datacount = 0; 1537 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1538 /* 1539 * Reset the bounce page to start at offset 0. Other uses 1540 * of this bounce page may need to store a full page of 1541 * data and/or assume it starts on a page boundary. 1542 */ 1543 bpage->vaddr &= ~PAGE_MASK; 1544 bpage->busaddr &= ~PAGE_MASK; 1545 } 1546 1547 mtx_lock(&bounce_lock); 1548 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1549 bz->free_bpages++; 1550 bz->active_bpages--; 1551 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1552 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1553 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1554 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1555 map, links); 1556 busdma_swi_pending = 1; 1557 bz->total_deferred++; 1558 swi_sched(vm_ih, 0); 1559 } 1560 } 1561 mtx_unlock(&bounce_lock); 1562} 1563 1564void 1565busdma_swi(void) 1566{ 1567 bus_dma_tag_t dmat; 1568 struct bus_dmamap *map; 1569 1570 mtx_lock(&bounce_lock); 1571 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1572 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1573 mtx_unlock(&bounce_lock); 1574 dmat = map->dmat; 1575 (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_LOCK); 1576 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1577 map->callback_arg, BUS_DMA_WAITOK); 1578 (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1579 mtx_lock(&bounce_lock); 1580 } 1581 mtx_unlock(&bounce_lock); 1582} 1583