1177888Sraj/* $NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */ 2177888Sraj 3177888Sraj/*- 4177888Sraj * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 5177888Sraj * All rights reserved. 6177888Sraj * 7177888Sraj * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8177888Sraj * 9177888Sraj * Redistribution and use in source and binary forms, with or without 10177888Sraj * modification, are permitted provided that the following conditions 11177888Sraj * are met: 12177888Sraj * 1. Redistributions of source code must retain the above copyright 13177888Sraj * notice, this list of conditions and the following disclaimer. 14177888Sraj * 2. Redistributions in binary form must reproduce the above copyright 15177888Sraj * notice, this list of conditions and the following disclaimer in the 16177888Sraj * documentation and/or other materials provided with the distribution. 17177888Sraj * 3. All advertising materials mentioning features or use of this software 18177888Sraj * must display the following acknowledgement: 19177888Sraj * This product includes software developed for the NetBSD Project by 20177888Sraj * Wasabi Systems, Inc. 21177888Sraj * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22177888Sraj * or promote products derived from this software without specific prior 23177888Sraj * written permission. 24177888Sraj * 25177888Sraj * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26177888Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27177888Sraj * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28177888Sraj * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29177888Sraj * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30177888Sraj * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31177888Sraj * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32177888Sraj * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33177888Sraj * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34177888Sraj * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35177888Sraj * POSSIBILITY OF SUCH DAMAGE. 36177888Sraj */ 37177888Sraj 38177888Sraj#include <sys/cdefs.h> 39177888Sraj__FBSDID("$FreeBSD$"); 40177888Sraj 41177888Sraj#include <sys/param.h> 42177888Sraj#include <sys/systm.h> 43177888Sraj#include <sys/bus.h> 44177888Sraj#include <sys/kernel.h> 45177888Sraj#include <sys/malloc.h> 46298627Sbr#include <sys/devmap.h> 47177888Sraj 48177888Sraj#include <vm/vm.h> 49177888Sraj#include <vm/pmap.h> 50177888Sraj#include <vm/vm_kern.h> 51177888Sraj#include <vm/vm_extern.h> 52177888Sraj 53177888Sraj#include <machine/bus.h> 54265870Sian#include <machine/cpufunc.h> 55177888Sraj 56277470Sianvoid 57277470Siangeneric_bs_unimplemented(void) 58277470Sian{ 59277470Sian 60277470Sian panic("unimplemented bus_space function called"); 61277470Sian} 62277470Sian 63177888Sraj/* Prototypes for all the bus_space structure functions */ 64177888Srajbs_protos(generic); 65177888Sraj 66177888Srajint 67277460Siangeneric_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 68177888Sraj bus_space_handle_t *bshp) 69177888Sraj{ 70257648Sian void *va; 71177888Sraj 72257648Sian /* 73257648Sian * We don't even examine the passed-in flags. For ARM, the CACHEABLE 74295694Sskra * flag doesn't make sense (we create VM_MEMATTR_DEVICE mappings), and 75295694Sskra * the LINEAR flag is just implied because we use kva_alloc(size). 76257648Sian */ 77260373Sian if ((va = pmap_mapdev(bpa, size)) == NULL) 78260373Sian return (ENOMEM); 79257648Sian *bshp = (bus_space_handle_t)va; 80177888Sraj return (0); 81177888Sraj} 82177888Sraj 83177888Srajint 84277460Siangeneric_bs_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 85177888Sraj bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap, 86177888Sraj bus_space_handle_t *bshp) 87177888Sraj{ 88177888Sraj 89177888Sraj panic("generic_bs_alloc(): not implemented"); 90177888Sraj} 91177888Sraj 92177888Sraj 93177888Srajvoid 94277460Siangeneric_bs_unmap(bus_space_tag_t t, bus_space_handle_t h, bus_size_t size) 95177888Sraj{ 96177888Sraj 97260373Sian pmap_unmapdev((vm_offset_t)h, size); 98177888Sraj} 99177888Sraj 100177888Srajvoid 101277460Siangeneric_bs_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 102177888Sraj{ 103177888Sraj 104177888Sraj panic("generic_bs_free(): not implemented"); 105177888Sraj} 106177888Sraj 107177888Srajint 108277460Siangeneric_bs_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, 109177888Sraj bus_size_t size, bus_space_handle_t *nbshp) 110177888Sraj{ 111177888Sraj 112177888Sraj *nbshp = bsh + offset; 113177888Sraj return (0); 114177888Sraj} 115177888Sraj 116177888Srajvoid 117277460Siangeneric_bs_barrier(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, 118177888Sraj bus_size_t len, int flags) 119177888Sraj{ 120177888Sraj 121265870Sian /* 122265870Sian * dsb() will drain the L1 write buffer and establish a memory access 123265870Sian * barrier point on platforms where that has meaning. On a write we 124265870Sian * also need to drain the L2 write buffer, because most on-chip memory 125265870Sian * mapped devices are downstream of the L2 cache. Note that this needs 126265870Sian * to be done even for memory mapped as Device type, because while 127265870Sian * Device memory is not cached, writes to it are still buffered. 128265870Sian */ 129265870Sian dsb(); 130265870Sian if (flags & BUS_SPACE_BARRIER_WRITE) { 131265870Sian cpu_l2cache_drain_writebuf(); 132265870Sian } 133177888Sraj} 134