bus_space_asm_generic.S revision 139735 
1/*	$NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $	*/
2
3/*-
4 * Copyright (c) 1997 Causality Limited.
5 * Copyright (c) 1997 Mark Brinicombe.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *	This product includes software developed by Mark Brinicombe
19 *	for the NetBSD Project.
20 * 4. The name of the company nor the name of the author may be used to
21 *    endorse or promote products derived from this software without specific
22 *    prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 */
37
38#include <machine/asm.h>
39#include <machine/cpuconf.h>
40__FBSDID("$FreeBSD: head/sys/arm/arm/bus_space_asm_generic.S 139735 2005-01-05 21:58:49Z imp $");
41
42/*
43 * Generic bus_space functions.
44 */
45
46/*
47 * read single
48 */
49
50ENTRY(generic_bs_r_1)
51	ldrb	r0, [r1, r2]
52	RET
53
54#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
55ENTRY(generic_armv4_bs_r_2)
56	ldrh	r0, [r1, r2]
57	RET
58#endif
59
60ENTRY(generic_bs_r_4)
61	ldr	r0, [r1, r2]
62	RET
63
64/*
65 * write single
66 */
67
68ENTRY(generic_bs_w_1)
69	strb	r3, [r1, r2]
70	RET
71
72#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
73ENTRY(generic_armv4_bs_w_2)
74	strh	r3, [r1, r2]
75	RET
76#endif
77
78ENTRY(generic_bs_w_4)
79	str	r3, [r1, r2]
80	RET
81
82/*
83 * read multiple
84 */
85
86ENTRY(generic_bs_rm_1)
87	add	r0, r1, r2
88	mov	r1, r3
89	ldr	r2, [sp, #0]
90	teq	r2, #0
91	RETeq
92
931:	ldrb	r3, [r0]
94	strb	r3, [r1], #1
95	subs	r2, r2, #1
96	bne	1b
97
98	RET
99
100#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
101ENTRY(generic_armv4_bs_rm_2)
102	add	r0, r1, r2
103	mov	r1, r3
104	ldr	r2, [sp, #0]
105	teq	r2, #0
106	RETeq
107
1081:	ldrh	r3, [r0]
109	strh	r3, [r1], #2
110	subs	r2, r2, #1
111	bne	1b
112
113	RET
114#endif
115
116ENTRY(generic_bs_rm_4)
117	add	r0, r1, r2
118	mov	r1, r3
119	ldr	r2, [sp, #0]
120	teq	r2, #0
121	RETeq
122
1231:	ldr	r3, [r0]
124	str	r3, [r1], #4
125	subs	r2, r2, #1
126	bne	1b
127
128	RET
129
130/*
131 * write multiple
132 */
133
134ENTRY(generic_bs_wm_1)
135	add	r0, r1, r2
136	mov	r1, r3
137	ldr	r2, [sp, #0]
138	teq	r2, #0
139	RETeq
140
1411:	ldrb	r3, [r1], #1
142	strb	r3, [r0]
143	subs	r2, r2, #1
144	bne	1b
145
146	RET
147
148#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
149ENTRY(generic_armv4_bs_wm_2)
150	add	r0, r1, r2
151	mov	r1, r3
152	ldr	r2, [sp, #0]
153	teq	r2, #0
154	RETeq
155
1561:	ldrh	r3, [r1], #2
157	strh	r3, [r0]
158	subs	r2, r2, #1
159	bne	1b
160
161	RET
162#endif
163
164ENTRY(generic_bs_wm_4)
165	add	r0, r1, r2
166	mov	r1, r3
167	ldr	r2, [sp, #0]
168	teq	r2, #0
169	RETeq
170
1711:	ldr	r3, [r1], #4
172	str	r3, [r0]
173	subs	r2, r2, #1
174	bne	1b
175
176	RET
177
178/*
179 * read region
180 */
181
182ENTRY(generic_bs_rr_1)
183	add	r0, r1, r2
184	mov	r1, r3
185	ldr	r2, [sp, #0]
186	teq	r2, #0
187	RETeq
188
1891:	ldrb	r3, [r0], #1
190	strb	r3, [r1], #1
191	subs	r2, r2, #1
192	bne	1b
193
194	RET
195
196#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
197ENTRY(generic_armv4_bs_rr_2)
198	add	r0, r1, r2
199	mov	r1, r3
200	ldr	r2, [sp, #0]
201	teq	r2, #0
202	RETeq
203
2041:	ldrh	r3, [r0], #2
205	strh	r3, [r1], #2
206	subs	r2, r2, #1
207	bne	1b
208
209	RET
210#endif
211
212ENTRY(generic_bs_rr_4)
213	add	r0, r1, r2
214	mov	r1, r3
215	ldr	r2, [sp, #0]
216	teq	r2, #0
217	RETeq
218
2191:	ldr	r3, [r0], #4
220	str	r3, [r1], #4
221	subs	r2, r2, #1
222	bne	1b
223
224	RET
225
226/*
227 * write region.
228 */
229
230ENTRY(generic_bs_wr_1)
231	add	r0, r1, r2
232	mov	r1, r3
233	ldr	r2, [sp, #0]
234	teq	r2, #0
235	RETeq
236
2371:	ldrb	r3, [r1], #1
238	strb	r3, [r0], #1
239	subs	r2, r2, #1
240	bne	1b
241
242	RET
243
244#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
245ENTRY(generic_armv4_bs_wr_2)
246	add	r0, r1, r2
247	mov	r1, r3
248	ldr	r2, [sp, #0]
249	teq	r2, #0
250	RETeq
251
2521:	ldrh	r3, [r1], #2
253	strh	r3, [r0], #2
254	subs	r2, r2, #1
255	bne	1b
256
257	RET
258#endif
259
260ENTRY(generic_bs_wr_4)
261	add	r0, r1, r2
262	mov	r1, r3
263	ldr	r2, [sp, #0]
264	teq	r2, #0
265	RETeq
266
2671:	ldr	r3, [r1], #4
268	str	r3, [r0], #4
269	subs	r2, r2, #1
270	bne	1b
271
272	RET
273
274/*
275 * set region
276 */
277
278ENTRY(generic_bs_sr_1)
279	add	r0, r1, r2
280	mov	r1, r3
281	ldr	r2, [sp, #0]
282	teq	r2, #0
283	RETeq
284
2851:	strb	r1, [r0], #1
286	subs	r2, r2, #1
287	bne	1b
288
289	RET
290
291#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
292ENTRY(generic_armv4_bs_sr_2)
293	add	r0, r1, r2
294	mov	r1, r3
295	ldr	r2, [sp, #0]
296	teq	r2, #0
297	RETeq
298
2991:	strh	r1, [r0], #2
300	subs	r2, r2, #1
301	bne	1b
302
303	RET
304#endif
305
306ENTRY(generic_bs_sr_4)
307	add	r0, r1, r2
308	mov	r1, r3
309	ldr	r2, [sp, #0]
310	teq	r2, #0
311	RETeq
312
3131:	str	r1, [r0], #4
314	subs	r2, r2, #1
315	bne	1b
316
317	RET
318
319/*
320 * copy region
321 */
322
323#if (ARM_ARCH_4 + ARM_ARCH_5) > 0
324ENTRY(generic_armv4_bs_c_2)
325	add	r0, r1, r2
326	ldr	r2, [sp, #0]
327	add	r1, r2, r3
328	ldr	r2, [sp, #4]
329	teq	r2, #0
330	RETeq
331
332	cmp	r0, r1
333	blt	2f
334
3351:	ldrh	r3, [r0], #2
336	strh	r3, [r1], #2
337	subs	r2, r2, #1
338	bne	1b
339
340	RET
341
3422:	add	r0, r0, r2, lsl #1
343	add	r1, r1, r2, lsl #1
344	sub	r0, r0, #2
345	sub	r1, r1, #2
346
3473:	ldrh	r3, [r0], #-2
348	strh	r3, [r1], #-2
349	subs	r2, r2, #1
350	bne	3b
351
352	RET
353#endif
354