1280905Sganbold/*- 2280905Sganbold * Copyright 2013-2015 John Wehle <john@feith.com> 3280905Sganbold * All rights reserved. 4280905Sganbold * 5280905Sganbold * Redistribution and use in source and binary forms, with or without 6280905Sganbold * modification, are permitted provided that the following conditions 7280905Sganbold * are met: 8280905Sganbold * 1. Redistributions of source code must retain the above copyright 9280905Sganbold * notice, this list of conditions and the following disclaimer. 10280905Sganbold * 2. Redistributions in binary form must reproduce the above copyright 11280905Sganbold * notice, this list of conditions and the following disclaimer in the 12280905Sganbold * documentation and/or other materials provided with the distribution. 13280905Sganbold * 14280905Sganbold * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15280905Sganbold * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16280905Sganbold * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17280905Sganbold * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18280905Sganbold * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19280905Sganbold * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20280905Sganbold * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21280905Sganbold * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22280905Sganbold * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23280905Sganbold * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24280905Sganbold * SUCH DAMAGE. 25280905Sganbold * 26280905Sganbold * $FreeBSD$ 27280905Sganbold */ 28280905Sganbold 29280905Sganbold#ifndef _ARM_AMLOGIC_AML8726_UART_H 30280905Sganbold#define _ARM_AMLOGIC_AML8726_UART_H 31280905Sganbold 32280905Sganbold#define AML_UART_WFIFO_REG 0 33280905Sganbold 34280905Sganbold#define AML_UART_RFIFO_REG 4 35280905Sganbold 36280905Sganbold#define AML_UART_CONTROL_REG 8 37280905Sganbold#define AML_UART_CONTROL_TX_INT_EN (1 << 28) 38280905Sganbold#define AML_UART_CONTROL_RX_INT_EN (1 << 27) 39280905Sganbold#define AML_UART_CONTROL_CLR_ERR (1 << 24) 40280905Sganbold#define AML_UART_CONTROL_RX_RST (1 << 23) 41280905Sganbold#define AML_UART_CONTROL_TX_RST (1 << 22) 42280905Sganbold#define AML_UART_CONTROL_DB_MASK (3 << 20) 43280905Sganbold#define AML_UART_CONTROL_8_DB (0 << 20) 44280905Sganbold#define AML_UART_CONTROL_7_DB (1 << 20) 45280905Sganbold#define AML_UART_CONTROL_6_DB (2 << 20) 46280905Sganbold#define AML_UART_CONTROL_5_DB (3 << 20) 47280905Sganbold#define AML_UART_CONTROL_P_MASK (3 << 18) 48280905Sganbold#define AML_UART_CONTROL_P_EN (1 << 19) 49280905Sganbold#define AML_UART_CONTROL_P_EVEN (0 << 18) 50280905Sganbold#define AML_UART_CONTROL_P_ODD (1 << 18) 51280905Sganbold#define AML_UART_CONTROL_SB_MASK (3 << 16) 52280905Sganbold#define AML_UART_CONTROL_1_SB (0 << 16) 53280905Sganbold#define AML_UART_CONTROL_2_SB (1 << 16) 54280905Sganbold#define AML_UART_CONTROL_TWO_WIRE_EN (1 << 15) 55280905Sganbold#define AML_UART_CONTROL_RX_EN (1 << 13) 56280905Sganbold#define AML_UART_CONTROL_TX_EN (1 << 12) 57280905Sganbold#define AML_UART_CONTROL_BAUD_MASK 0xfff 58280905Sganbold#define AML_UART_CONTROL_BAUD_WIDTH 12 59280905Sganbold 60280905Sganbold#define AML_UART_STATUS_REG 12 61280905Sganbold#define AML_UART_STATUS_RECV_BUSY (1 << 26) 62280905Sganbold#define AML_UART_STATUS_XMIT_BUSY (1 << 25) 63280905Sganbold#define AML_UART_STATUS_RX_FIFO_OVERFLOW (1 << 24) 64280905Sganbold#define AML_UART_STATUS_TX_FIFO_EMPTY (1 << 22) 65280905Sganbold#define AML_UART_STATUS_TX_FIFO_FULL (1 << 21) 66280905Sganbold#define AML_UART_STATUS_RX_FIFO_EMPTY (1 << 20) 67280905Sganbold#define AML_UART_STATUS_RX_FIFO_FULL (1 << 19) 68280905Sganbold#define AML_UART_STATUS_TX_FIFO_WRITE_ERR (1 << 18) 69280905Sganbold#define AML_UART_STATUS_FRAME_ERR (1 << 17) 70280905Sganbold#define AML_UART_STATUS_PARITY_ERR (1 << 16) 71280905Sganbold#define AML_UART_STATUS_TX_FIFO_CNT_MASK (0x7f << 8) 72280905Sganbold#define AML_UART_STATUS_TX_FIFO_CNT_SHIFT 8 73280905Sganbold#define AML_UART_STATUS_RX_FIFO_CNT_MASK (0x7f << 0) 74280905Sganbold#define AML_UART_STATUS_RX_FIFO_CNT_SHIFT 0 75280905Sganbold 76280905Sganbold#define AML_UART_MISC_REG 16 77280905Sganbold#define AML_UART_MISC_OLD_RX_BAUD (1 << 30) 78280905Sganbold#define AML_UART_MISC_BAUD_EXT_MASK (0xf << 20) 79280905Sganbold#define AML_UART_MISC_BAUD_EXT_SHIFT 20 80280905Sganbold 81280905Sganbold/* 82280905Sganbold * The documentation appears to be incorrect as the 83280905Sganbold * IRQ is actually generated when TX FIFO count is 84280905Sganbold * * equal to * or less than the selected threshold. 85280905Sganbold */ 86280905Sganbold#define AML_UART_MISC_XMIT_IRQ_CNT_MASK (0xff << 8) 87280905Sganbold#define AML_UART_MISC_XMIT_IRQ_CNT_SHIFT 8 88280905Sganbold 89280905Sganbold/* 90280905Sganbold * The documentation appears to be incorrect as the 91280905Sganbold * IRQ is actually generated when RX FIFO count is 92280905Sganbold * * equal to * or greater than the selected threshold. 93280905Sganbold */ 94280905Sganbold#define AML_UART_MISC_RECV_IRQ_CNT_MASK 0xff 95280905Sganbold#define AML_UART_MISC_RECV_IRQ_CNT_SHIFT 0 96280905Sganbold 97282517Sganbold/* 98282517Sganbold * The new baud rate register is available on the 99282517Sganbold * aml8726-m6 and later. 100282517Sganbold */ 101282517Sganbold#define AML_UART_NEW_BAUD_REG 20 102282517Sganbold#define AML_UART_NEW_BAUD_USE_XTAL_CLK (1 << 24) 103282517Sganbold#define AML_UART_NEW_BAUD_RATE_EN (1 << 23) 104282517Sganbold#define AML_UART_NEW_BAUD_RATE_MASK (0x7fffff << 0) 105282517Sganbold#define AML_UART_NEW_BAUD_RATE_SHIFT 0 106282517Sganbold 107280905Sganbold#endif /* _ARM_AMLOGIC_AML8726_UART_H */ 108