aw_debeclk.c revision 297627 
1/*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/arm/allwinner/clk/aw_debeclk.c 297627 2016-04-06 23:11:03Z jmcneill $
27 */
28
29/*
30 * Allwinner display backend clocks
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/arm/allwinner/clk/aw_debeclk.c 297627 2016-04-06 23:11:03Z jmcneill $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/rman.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <machine/bus.h>
43
44#include <dev/ofw/ofw_bus.h>
45#include <dev/ofw/ofw_bus_subr.h>
46#include <dev/ofw/ofw_subr.h>
47
48#include <dev/extres/clk/clk.h>
49#include <dev/extres/hwreset/hwreset.h>
50
51#include "clkdev_if.h"
52#include "hwreset_if.h"
53
54#define	SCLK_GATING		(1 << 31)
55#define	BE_RST			(1 << 30)
56#define	CLK_SRC_SEL		(0x3 << 24)
57#define	CLK_SRC_SEL_SHIFT	24
58#define	CLK_SRC_SEL_MAX		2
59#define	CLK_SRC_SEL_PLL3	0
60#define	CLK_SRC_SEL_PLL7	1
61#define	CLK_SRC_SEL_PLL5	2
62#define	CLK_RATIO_M		(0xf << 0)
63#define	CLK_RATIO_M_SHIFT	0
64#define	CLK_RATIO_M_MAX		0xf
65
66static struct ofw_compat_data compat_data[] = {
67	{ "allwinner,sun4i-a10-de-be-clk",	1 },
68	{ NULL, 0 }
69};
70
71struct aw_debeclk_softc {
72	device_t	clkdev;
73	bus_addr_t	reg;
74};
75
76#define	DEBECLK_READ(sc, val)	CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
77#define	DEBECLK_WRITE(sc, val)	CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
78#define	DEBECLK_MODIFY(sc, clr, set)	\
79	CLKDEV_MODIFY_4((sc)->clkdev, (sc)->reg, (clr), (set))
80#define	DEVICE_LOCK(sc)		CLKDEV_DEVICE_LOCK((sc)->clkdev)
81#define	DEVICE_UNLOCK(sc)	CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
82
83static int
84aw_debeclk_hwreset_assert(device_t dev, intptr_t id, bool value)
85{
86	struct aw_debeclk_softc *sc;
87	int error;
88
89	sc = device_get_softc(dev);
90
91	DEVICE_LOCK(sc);
92	error = DEBECLK_MODIFY(sc, BE_RST, value ? 0 : BE_RST);
93	DEVICE_UNLOCK(sc);
94
95	return (error);
96}
97
98static int
99aw_debeclk_hwreset_is_asserted(device_t dev, intptr_t id, bool *value)
100{
101	struct aw_debeclk_softc *sc;
102	uint32_t val;
103	int error;
104
105	sc = device_get_softc(dev);
106
107	DEVICE_LOCK(sc);
108	error = DEBECLK_READ(sc, &val);
109	DEVICE_UNLOCK(sc);
110
111	if (error)
112		return (error);
113
114	*value = (val & BE_RST) != 0 ? false : true;
115
116	return (0);
117}
118
119static int
120aw_debeclk_init(struct clknode *clk, device_t dev)
121{
122	struct aw_debeclk_softc *sc;
123	uint32_t val, index;
124
125	sc = clknode_get_softc(clk);
126
127	/* Set BE source to PLL5 (DDR external peripheral clock) */
128	index = CLK_SRC_SEL_PLL5;
129
130	DEVICE_LOCK(sc);
131	DEBECLK_READ(sc, &val);
132	val &= ~CLK_SRC_SEL;
133	val |= (index << CLK_SRC_SEL_SHIFT);
134	DEBECLK_WRITE(sc, val);
135	DEVICE_UNLOCK(sc);
136
137	clknode_init_parent_idx(clk, index);
138	return (0);
139}
140
141static int
142aw_debeclk_set_mux(struct clknode *clk, int index)
143{
144	struct aw_debeclk_softc *sc;
145	uint32_t val;
146
147	sc = clknode_get_softc(clk);
148
149	if (index < 0 || index > CLK_SRC_SEL_MAX)
150		return (ERANGE);
151
152	DEVICE_LOCK(sc);
153	DEBECLK_READ(sc, &val);
154	val &= ~CLK_SRC_SEL;
155	val |= (index << CLK_SRC_SEL_SHIFT);
156	DEBECLK_WRITE(sc, val);
157	DEVICE_UNLOCK(sc);
158
159	return (0);
160}
161
162static int
163aw_debeclk_set_gate(struct clknode *clk, bool enable)
164{
165	struct aw_debeclk_softc *sc;
166	uint32_t val;
167
168	sc = clknode_get_softc(clk);
169
170	DEVICE_LOCK(sc);
171	DEBECLK_READ(sc, &val);
172	if (enable)
173		val |= SCLK_GATING;
174	else
175		val &= ~SCLK_GATING;
176	DEBECLK_WRITE(sc, val);
177	DEVICE_UNLOCK(sc);
178
179	return (0);
180}
181
182static int
183aw_debeclk_recalc_freq(struct clknode *clk, uint64_t *freq)
184{
185	struct aw_debeclk_softc *sc;
186	uint32_t val, m;
187
188	sc = clknode_get_softc(clk);
189
190	DEVICE_LOCK(sc);
191	DEBECLK_READ(sc, &val);
192	DEVICE_UNLOCK(sc);
193
194	m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1;
195
196	*freq = *freq / m;
197
198	return (0);
199}
200
201static int
202aw_debeclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
203    int flags, int *stop)
204{
205	struct aw_debeclk_softc *sc;
206	uint32_t val, m;
207
208	sc = clknode_get_softc(clk);
209
210	m = howmany(fin, *fout) - 1;
211
212	DEVICE_LOCK(sc);
213	DEBECLK_READ(sc, &val);
214	val &= ~CLK_RATIO_M;
215	val |= (m << CLK_RATIO_M_SHIFT);
216	DEBECLK_WRITE(sc, val);
217	DEVICE_UNLOCK(sc);
218
219	*fout = fin / (m + 1);
220	*stop = 1;
221
222	return (0);
223}
224
225static clknode_method_t aw_debeclk_clknode_methods[] = {
226	/* Device interface */
227	CLKNODEMETHOD(clknode_init,		aw_debeclk_init),
228	CLKNODEMETHOD(clknode_set_gate,		aw_debeclk_set_gate),
229	CLKNODEMETHOD(clknode_set_mux,		aw_debeclk_set_mux),
230	CLKNODEMETHOD(clknode_recalc_freq,	aw_debeclk_recalc_freq),
231	CLKNODEMETHOD(clknode_set_freq,		aw_debeclk_set_freq),
232	CLKNODEMETHOD_END
233};
234DEFINE_CLASS_1(aw_debeclk_clknode, aw_debeclk_clknode_class,
235    aw_debeclk_clknode_methods, sizeof(struct aw_debeclk_softc), clknode_class);
236
237static int
238aw_debeclk_probe(device_t dev)
239{
240	if (!ofw_bus_status_okay(dev))
241		return (ENXIO);
242
243	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
244		return (ENXIO);
245
246	device_set_desc(dev, "Allwinner Display Engine Backend Clock");
247	return (BUS_PROBE_DEFAULT);
248}
249
250static int
251aw_debeclk_attach(device_t dev)
252{
253	struct clknode_init_def def;
254	struct aw_debeclk_softc *sc, *clk_sc;
255	struct clkdom *clkdom;
256	struct clknode *clk;
257	clk_t clk_parent;
258	bus_size_t psize;
259	phandle_t node;
260	int error, ncells, i;
261
262	sc = device_get_softc(dev);
263	sc->clkdev = device_get_parent(dev);
264	node = ofw_bus_get_node(dev);
265
266	if (ofw_reg_to_paddr(node, 0, &sc->reg, &psize, NULL) != 0) {
267		device_printf(dev, "cannot parse 'reg' property\n");
268		return (ENXIO);
269	}
270
271	error = ofw_bus_parse_xref_list_get_length(node, "clocks",
272	    "#clock-cells", &ncells);
273	if (error != 0) {
274		device_printf(dev, "cannot get clock count\n");
275		return (error);
276	}
277
278	clkdom = clkdom_create(dev);
279
280	memset(&def, 0, sizeof(def));
281	error = clk_parse_ofw_clk_name(dev, node, &def.name);
282	if (error != 0) {
283		device_printf(dev, "cannot parse clock name\n");
284		error = ENXIO;
285		goto fail;
286	}
287	def.id = 1;
288	def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
289	for (i = 0; i < ncells; i++) {
290		error = clk_get_by_ofw_index(dev, i, &clk_parent);
291		if (error != 0) {
292			device_printf(dev, "cannot get clock %d\n", i);
293			goto fail;
294		}
295		def.parent_names[i] = clk_get_name(clk_parent);
296		clk_release(clk_parent);
297	}
298	def.parent_cnt = ncells;
299
300	clk = clknode_create(clkdom, &aw_debeclk_clknode_class, &def);
301	if (clk == NULL) {
302		device_printf(dev, "cannot create clknode\n");
303		error = ENXIO;
304		goto fail;
305	}
306
307	clk_sc = clknode_get_softc(clk);
308	clk_sc->reg = sc->reg;
309	clk_sc->clkdev = device_get_parent(dev);
310
311	clknode_register(clkdom, clk);
312
313	if (clkdom_finit(clkdom) != 0) {
314		device_printf(dev, "cannot finalize clkdom initialization\n");
315		error = ENXIO;
316		goto fail;
317	}
318
319	if (bootverbose)
320		clkdom_dump(clkdom);
321
322	hwreset_register_ofw_provider(dev);
323
324	return (0);
325
326fail:
327	return (error);
328}
329
330static device_method_t aw_debeclk_methods[] = {
331	/* Device interface */
332	DEVMETHOD(device_probe,		aw_debeclk_probe),
333	DEVMETHOD(device_attach,	aw_debeclk_attach),
334
335	/* Reset interface */
336	DEVMETHOD(hwreset_assert,	aw_debeclk_hwreset_assert),
337	DEVMETHOD(hwreset_is_asserted,	aw_debeclk_hwreset_is_asserted),
338
339	DEVMETHOD_END
340};
341
342static driver_t aw_debeclk_driver = {
343	"aw_debeclk",
344	aw_debeclk_methods,
345	sizeof(struct aw_debeclk_softc)
346};
347
348static devclass_t aw_debeclk_devclass;
349
350EARLY_DRIVER_MODULE(aw_debeclk, simplebus, aw_debeclk_driver,
351    aw_debeclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
352