a10_mmc.h revision 283253
1283253Sloos/*- 2283253Sloos * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com> 3283253Sloos * All rights reserved. 4283253Sloos * 5283253Sloos * Redistribution and use in source and binary forms, with or without 6283253Sloos * modification, are permitted provided that the following conditions 7283253Sloos * are met: 8283253Sloos * 1. Redistributions of source code must retain the above copyright 9283253Sloos * notice, this list of conditions and the following disclaimer. 10283253Sloos * 2. Redistributions in binary form must reproduce the above copyright 11283253Sloos * notice, this list of conditions and the following disclaimer in the 12283253Sloos * documentation and/or other materials provided with the distribution. 13283253Sloos * 14283253Sloos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15283253Sloos * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16283253Sloos * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17283253Sloos * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18283253Sloos * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19283253Sloos * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20283253Sloos * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21283253Sloos * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22283253Sloos * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23283253Sloos * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24283253Sloos * SUCH DAMAGE. 25283253Sloos * 26283253Sloos * $FreeBSD: head/sys/arm/allwinner/a10_mmc.h 283253 2015-05-21 17:39:42Z loos $ 27283253Sloos */ 28283253Sloos 29283253Sloos#ifndef _A10_MMC_H_ 30283253Sloos#define _A10_MMC_H_ 31283253Sloos 32283253Sloos#define A10_MMC_GCTRL 0x00 /* Global Control Register */ 33283253Sloos#define A10_MMC_CLKCR 0x04 /* Clock Control Register */ 34283253Sloos#define A10_MMC_TIMEOUT 0x08 /* Timeout Register */ 35283253Sloos#define A10_MMC_WIDTH 0x0C /* Bus Width Register */ 36283253Sloos#define A10_MMC_BLKSZ 0x10 /* Block Size Register */ 37283253Sloos#define A10_MMC_BCNTR 0x14 /* Byte Count Register */ 38283253Sloos#define A10_MMC_CMDR 0x18 /* Command Register */ 39283253Sloos#define A10_MMC_CARG 0x1C /* Argument Register */ 40283253Sloos#define A10_MMC_RESP0 0x20 /* Response Register 0 */ 41283253Sloos#define A10_MMC_RESP1 0x24 /* Response Register 1 */ 42283253Sloos#define A10_MMC_RESP2 0x28 /* Response Register 2 */ 43283253Sloos#define A10_MMC_RESP3 0x2C /* Response Register 3 */ 44283253Sloos#define A10_MMC_IMASK 0x30 /* Interrupt Mask Register */ 45283253Sloos#define A10_MMC_MISTA 0x34 /* Masked Interrupt Status Register */ 46283253Sloos#define A10_MMC_RINTR 0x38 /* Raw Interrupt Status Register */ 47283253Sloos#define A10_MMC_STAS 0x3C /* Status Register */ 48283253Sloos#define A10_MMC_FTRGL 0x40 /* FIFO Threshold Watermark Register */ 49283253Sloos#define A10_MMC_FUNS 0x44 /* Function Select Register */ 50283253Sloos#define A10_MMC_CBCR 0x48 /* CIU Byte Count Register */ 51283253Sloos#define A10_MMC_BBCR 0x4C /* BIU Byte Count Register */ 52283253Sloos#define A10_MMC_DBGC 0x50 /* Debug Enable Register */ 53283253Sloos#define A10_MMC_DMAC 0x80 /* IDMAC Control Register */ 54283253Sloos#define A10_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */ 55283253Sloos#define A10_MMC_IDST 0x88 /* IDMAC Status Register */ 56283253Sloos#define A10_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */ 57283253Sloos#define A10_MMC_CHDA 0x90 58283253Sloos#define A10_MMC_CBDA 0x94 59283253Sloos#define A10_MMC_FIFO 0x100 /* FIFO Access Address */ 60283253Sloos 61283253Sloos/* A10_MMC_GCTRL */ 62283253Sloos#define A10_MMC_SOFT_RESET (1U << 0) 63283253Sloos#define A10_MMC_FIFO_RESET (1U << 1) 64283253Sloos#define A10_MMC_DMA_RESET (1U << 2) 65283253Sloos#define A10_MMC_INT_ENABLE (1U << 4) 66283253Sloos#define A10_MMC_DMA_ENABLE (1U << 5) 67283253Sloos#define A10_MMC_DEBOUNCE_ENABLE (1U << 8) 68283253Sloos#define A10_MMC_DDR_MODE (1U << 10) 69283253Sloos#define A10_MMC_ACCESS_BY_DMA (1U << 30) 70283253Sloos#define A10_MMC_ACCESS_BY_AHB (1U << 31) 71283253Sloos#define A10_MMC_RESET \ 72283253Sloos (A10_MMC_SOFT_RESET | A10_MMC_FIFO_RESET | A10_MMC_DMA_RESET) 73283253Sloos 74283253Sloos/* A10_MMC_CLKCR */ 75283253Sloos#define A10_MMC_CARD_CLK_ON (1U << 16) 76283253Sloos#define A10_MMC_LOW_POWER_ON (1U << 17) 77283253Sloos#define A10_MMC_CLKCR_DIV 0xff 78283253Sloos 79283253Sloos/* A10_MMC_WIDTH */ 80283253Sloos#define A10_MMC_WIDTH1 0 81283253Sloos#define A10_MMC_WIDTH4 1 82283253Sloos#define A10_MMC_WIDTH8 2 83283253Sloos 84283253Sloos/* A10_MMC_CMDR */ 85283253Sloos#define A10_MMC_RESP_EXP (1U << 6) 86283253Sloos#define A10_MMC_LONG_RESP (1U << 7) 87283253Sloos#define A10_MMC_CHECK_RESP_CRC (1U << 8) 88283253Sloos#define A10_MMC_DATA_EXP (1U << 9) 89283253Sloos#define A10_MMC_WRITE (1U << 10) 90283253Sloos#define A10_MMC_SEQ_MODE (1U << 11) 91283253Sloos#define A10_MMC_SEND_AUTOSTOP (1U << 12) 92283253Sloos#define A10_MMC_WAIT_PREOVER (1U << 13) 93283253Sloos#define A10_MMC_STOP_ABORT_CMD (1U << 14) 94283253Sloos#define A10_MMC_SEND_INIT_SEQ (1U << 15) 95283253Sloos#define A10_MMC_UPCLK_ONLY (1U << 21) 96283253Sloos#define A10_MMC_RDCEATADEV (1U << 22) 97283253Sloos#define A10_MMC_CCS_EXP (1U << 23) 98283253Sloos#define A10_MMC_ENB_BOOT (1U << 24) 99283253Sloos#define A10_MMC_ALT_BOOT_OPT (1U << 25) 100283253Sloos#define A10_MMC_BOOT_ACK_EXP (1U << 26) 101283253Sloos#define A10_MMC_DISABLE_BOOT (1U << 27) 102283253Sloos#define A10_MMC_VOL_SWITCH (1U << 28) 103283253Sloos#define A10_MMC_START (1U << 31) 104283253Sloos 105283253Sloos/* A10_MMC_IMASK and A10_MMC_RINTR */ 106283253Sloos#define A10_MMC_RESP_ERR (1U << 1) 107283253Sloos#define A10_MMC_CMD_DONE (1U << 2) 108283253Sloos#define A10_MMC_DATA_OVER (1U << 3) 109283253Sloos#define A10_MMC_TX_DATA_REQ (1U << 4) 110283253Sloos#define A10_MMC_RX_DATA_REQ (1U << 5) 111283253Sloos#define A10_MMC_RESP_CRC_ERR (1U << 6) 112283253Sloos#define A10_MMC_DATA_CRC_ERR (1U << 7) 113283253Sloos#define A10_MMC_RESP_TIMEOUT (1U << 8) 114283253Sloos#define A10_MMC_ACK_RECV (1U << 8) 115283253Sloos#define A10_MMC_DATA_TIMEOUT (1U << 9) 116283253Sloos#define A10_MMC_BOOT_START (1U << 9) 117283253Sloos#define A10_MMC_DATA_STARVE (1U << 10) 118283253Sloos#define A10_MMC_VOL_CHG_DONE (1U << 10) 119283253Sloos#define A10_MMC_FIFO_RUN_ERR (1U << 11) 120283253Sloos#define A10_MMC_HARDW_LOCKED (1U << 12) 121283253Sloos#define A10_MMC_START_BIT_ERR (1U << 13) 122283253Sloos#define A10_MMC_AUTOCMD_DONE (1U << 14) 123283253Sloos#define A10_MMC_END_BIT_ERR (1U << 15) 124283253Sloos#define A10_MMC_SDIO_INT (1U << 16) 125283253Sloos#define A10_MMC_CARD_INSERT (1U << 30) 126283253Sloos#define A10_MMC_CARD_REMOVE (1U << 31) 127283253Sloos#define A10_MMC_INT_ERR_BIT \ 128283253Sloos (A10_MMC_RESP_ERR | A10_MMC_RESP_CRC_ERR | \ 129283253Sloos A10_MMC_DATA_CRC_ERR | A10_MMC_RESP_TIMEOUT | \ 130283253Sloos A10_MMC_FIFO_RUN_ERR | A10_MMC_HARDW_LOCKED | \ 131283253Sloos A10_MMC_START_BIT_ERR | A10_MMC_END_BIT_ERR) 132283253Sloos 133283253Sloos/* A10_MMC_STAS */ 134283253Sloos#define A10_MMC_RX_WLFLAG (1U << 0) 135283253Sloos#define A10_MMC_TX_WLFLAG (1U << 1) 136283253Sloos#define A10_MMC_FIFO_EMPTY (1U << 2) 137283253Sloos#define A10_MMC_FIFO_FULL (1U << 3) 138283253Sloos#define A10_MMC_CARD_PRESENT (1U << 8) 139283253Sloos#define A10_MMC_CARD_DATA_BUSY (1U << 9) 140283253Sloos#define A10_MMC_DATA_FSM_BUSY (1U << 10) 141283253Sloos#define A10_MMC_DMA_REQ (1U << 31) 142283253Sloos#define A10_MMC_FIFO_SIZE 16 143283253Sloos 144283253Sloos/* A10_MMC_FUNS */ 145283253Sloos#define A10_MMC_CE_ATA_ON (0xceaaU << 16) 146283253Sloos#define A10_MMC_SEND_IRQ_RESP (1U << 0) 147283253Sloos#define A10_MMC_SDIO_RD_WAIT (1U << 1) 148283253Sloos#define A10_MMC_ABT_RD_DATA (1U << 2) 149283253Sloos#define A10_MMC_SEND_CC_SD (1U << 8) 150283253Sloos#define A10_MMC_SEND_AUTOSTOP_CC_SD (1U << 9) 151283253Sloos#define A10_MMC_CE_ATA_DEV_INT_ENB (1U << 10) 152283253Sloos 153283253Sloos/* IDMA CONTROLLER BUS MOD BIT FIELD */ 154283253Sloos#define A10_MMC_IDMAC_SOFT_RST (1U << 0) 155283253Sloos#define A10_MMC_IDMAC_FIX_BURST (1U << 1) 156283253Sloos#define A10_MMC_IDMAC_IDMA_ON (1U << 7) 157283253Sloos#define A10_MMC_IDMAC_REFETCH_DES (1U << 31) 158283253Sloos 159283253Sloos/* A10_MMC_IDST */ 160283253Sloos#define A10_MMC_IDMAC_TRANSMIT_INT (1U << 0) 161283253Sloos#define A10_MMC_IDMAC_RECEIVE_INT (1U << 1) 162283253Sloos#define A10_MMC_IDMAC_FATAL_BUS_ERR (1U << 2) 163283253Sloos#define A10_MMC_IDMAC_DES_INVALID (1U << 4) 164283253Sloos#define A10_MMC_IDMAC_CARD_ERR_SUM (1U << 5) 165283253Sloos#define A10_MMC_IDMAC_NORMAL_INT_SUM (1U << 8) 166283253Sloos#define A10_MMC_IDMAC_ABNORMAL_INT_SUM (1U << 9) 167283253Sloos#define A10_MMC_IDMAC_HOST_ABT_INTX (1U << 10) 168283253Sloos#define A10_MMC_IDMAC_HOST_ABT_INRX (1U << 10) 169283253Sloos#define A10_MMC_IDMAC_IDLE (0U << 13) 170283253Sloos#define A10_MMC_IDMAC_SUSPEND (1U << 13) 171283253Sloos#define A10_MMC_IDMAC_DESC_RD (2U << 13) 172283253Sloos#define A10_MMC_IDMAC_DESC_CHECK (3U << 13) 173283253Sloos#define A10_MMC_IDMAC_RD_REQ_WAIT (4U << 13) 174283253Sloos#define A10_MMC_IDMAC_WR_REQ_WAIT (5U << 13) 175283253Sloos#define A10_MMC_IDMAC_RD (6U << 13) 176283253Sloos#define A10_MMC_IDMAC_WR (7U << 13) 177283253Sloos#define A10_MMC_IDMAC_DESC_CLOSE (8U << 13) 178283253Sloos 179283253Sloos#endif /* _A10_MMC_H_ */ 180