a10_hdmi.c revision 296789
1296064Sjmcneill/*- 2296064Sjmcneill * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3296064Sjmcneill * All rights reserved. 4296064Sjmcneill * 5296064Sjmcneill * Redistribution and use in source and binary forms, with or without 6296064Sjmcneill * modification, are permitted provided that the following conditions 7296064Sjmcneill * are met: 8296064Sjmcneill * 1. Redistributions of source code must retain the above copyright 9296064Sjmcneill * notice, this list of conditions and the following disclaimer. 10296064Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 11296064Sjmcneill * notice, this list of conditions and the following disclaimer in the 12296064Sjmcneill * documentation and/or other materials provided with the distribution. 13296064Sjmcneill * 14296064Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15296064Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16296064Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17296064Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18296064Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19296064Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20296064Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21296064Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22296064Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23296064Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24296064Sjmcneill * SUCH DAMAGE. 25296064Sjmcneill * 26296064Sjmcneill * $FreeBSD: head/sys/arm/allwinner/a10_hdmi.c 296789 2016-03-13 01:47:42Z jmcneill $ 27296064Sjmcneill */ 28296064Sjmcneill 29296064Sjmcneill/* 30296064Sjmcneill * Allwinner A10/A20 HDMI TX 31296064Sjmcneill */ 32296064Sjmcneill 33296064Sjmcneill#include <sys/cdefs.h> 34296064Sjmcneill__FBSDID("$FreeBSD: head/sys/arm/allwinner/a10_hdmi.c 296789 2016-03-13 01:47:42Z jmcneill $"); 35296064Sjmcneill 36296064Sjmcneill#include <sys/param.h> 37296064Sjmcneill#include <sys/systm.h> 38296064Sjmcneill#include <sys/bus.h> 39296064Sjmcneill#include <sys/rman.h> 40296064Sjmcneill#include <sys/condvar.h> 41296064Sjmcneill#include <sys/kernel.h> 42296064Sjmcneill#include <sys/module.h> 43296064Sjmcneill 44296064Sjmcneill#include <machine/bus.h> 45296064Sjmcneill 46296064Sjmcneill#include <dev/ofw/ofw_bus.h> 47296064Sjmcneill#include <dev/ofw/ofw_bus_subr.h> 48296064Sjmcneill 49296064Sjmcneill#include <dev/videomode/videomode.h> 50296064Sjmcneill#include <dev/videomode/edidvar.h> 51296064Sjmcneill 52296064Sjmcneill#include <arm/allwinner/a10_clk.h> 53296064Sjmcneill 54296064Sjmcneill#include "hdmi_if.h" 55296064Sjmcneill 56296064Sjmcneill#define HDMI_CTRL 0x004 57296064Sjmcneill#define CTRL_MODULE_EN (1 << 31) 58296064Sjmcneill#define HDMI_INT_STATUS 0x008 59296064Sjmcneill#define HDMI_HPD 0x00c 60296064Sjmcneill#define HPD_DET (1 << 0) 61296064Sjmcneill#define HDMI_VID_CTRL 0x010 62296064Sjmcneill#define VID_CTRL_VIDEO_EN (1 << 31) 63296064Sjmcneill#define VID_CTRL_HDMI_MODE (1 << 30) 64296064Sjmcneill#define VID_CTRL_INTERLACE (1 << 4) 65296064Sjmcneill#define VID_CTRL_REPEATER_2X (1 << 0) 66296064Sjmcneill#define HDMI_VID_TIMING0 0x014 67296064Sjmcneill#define VID_ACT_V(v) (((v) - 1) << 16) 68296064Sjmcneill#define VID_ACT_H(h) (((h) - 1) << 0) 69296064Sjmcneill#define HDMI_VID_TIMING1 0x018 70296064Sjmcneill#define VID_VBP(vbp) (((vbp) - 1) << 16) 71296064Sjmcneill#define VID_HBP(hbp) (((hbp) - 1) << 0) 72296064Sjmcneill#define HDMI_VID_TIMING2 0x01c 73296064Sjmcneill#define VID_VFP(vfp) (((vfp) - 1) << 16) 74296064Sjmcneill#define VID_HFP(hfp) (((hfp) - 1) << 0) 75296064Sjmcneill#define HDMI_VID_TIMING3 0x020 76296064Sjmcneill#define VID_VSPW(vspw) (((vspw) - 1) << 16) 77296064Sjmcneill#define VID_HSPW(hspw) (((hspw) - 1) << 0) 78296064Sjmcneill#define HDMI_VID_TIMING4 0x024 79296064Sjmcneill#define TX_CLOCK_NORMAL 0x03e00000 80296064Sjmcneill#define VID_VSYNC_ACTSEL (1 << 1) 81296064Sjmcneill#define VID_HSYNC_ACTSEL (1 << 0) 82296064Sjmcneill#define HDMI_AUD_CTRL 0x040 83296064Sjmcneill#define AUD_CTRL_EN (1 << 31) 84296064Sjmcneill#define AUD_CTRL_RST (1 << 30) 85296064Sjmcneill#define HDMI_ADMA_CTRL 0x044 86296064Sjmcneill#define HDMI_ADMA_MODE (1 << 31) 87296064Sjmcneill#define HDMI_ADMA_MODE_DDMA (0 << 31) 88296064Sjmcneill#define HDMI_ADMA_MODE_NDMA (1 << 31) 89296064Sjmcneill#define HDMI_AUD_FMT 0x048 90296064Sjmcneill#define AUD_FMT_CH(n) ((n) - 1) 91296064Sjmcneill#define HDMI_PCM_CTRL 0x04c 92296064Sjmcneill#define HDMI_AUD_CTS 0x050 93296064Sjmcneill#define HDMI_AUD_N 0x054 94296064Sjmcneill#define HDMI_AUD_CH_STATUS0 0x058 95296064Sjmcneill#define CH_STATUS0_FS_FREQ (0xf << 24) 96296064Sjmcneill#define CH_STATUS0_FS_FREQ_48 (2 << 24) 97296064Sjmcneill#define HDMI_AUD_CH_STATUS1 0x05c 98296064Sjmcneill#define CH_STATUS1_WORD_LEN (0x7 << 1) 99296064Sjmcneill#define CH_STATUS1_WORD_LEN_16 (1 << 1) 100296064Sjmcneill#define HDMI_AUDIO_RESET_RETRY 1000 101296064Sjmcneill#define HDMI_AUDIO_CHANNELS 2 102296064Sjmcneill#define HDMI_AUDIO_CHANNELMAP 0x76543210 103296064Sjmcneill#define HDMI_AUDIO_N 6144 /* 48 kHz */ 104296064Sjmcneill#define HDMI_AUDIO_CTS(r, n) ((((r) * 10) * ((n) / 128)) / 480) 105296064Sjmcneill#define HDMI_PADCTRL0 0x200 106296064Sjmcneill#define PADCTRL0_BIASEN (1 << 31) 107296064Sjmcneill#define PADCTRL0_LDOCEN (1 << 30) 108296064Sjmcneill#define PADCTRL0_LDODEN (1 << 29) 109296064Sjmcneill#define PADCTRL0_PWENC (1 << 28) 110296064Sjmcneill#define PADCTRL0_PWEND (1 << 27) 111296064Sjmcneill#define PADCTRL0_PWENG (1 << 26) 112296064Sjmcneill#define PADCTRL0_CKEN (1 << 25) 113296064Sjmcneill#define PADCTRL0_SEN (1 << 24) 114296064Sjmcneill#define PADCTRL0_TXEN (1 << 23) 115296064Sjmcneill#define HDMI_PADCTRL1 0x204 116296064Sjmcneill#define PADCTRL1_AMP_OPT (1 << 23) 117296064Sjmcneill#define PADCTRL1_AMPCK_OPT (1 << 22) 118296064Sjmcneill#define PADCTRL1_DMP_OPT (1 << 21) 119296064Sjmcneill#define PADCTRL1_EMP_OPT (1 << 20) 120296064Sjmcneill#define PADCTRL1_EMPCK_OPT (1 << 19) 121296064Sjmcneill#define PADCTRL1_PWSCK (1 << 18) 122296064Sjmcneill#define PADCTRL1_PWSDT (1 << 17) 123296064Sjmcneill#define PADCTRL1_REG_CSMPS (1 << 16) 124296064Sjmcneill#define PADCTRL1_REG_DEN (1 << 15) 125296064Sjmcneill#define PADCTRL1_REG_DENCK (1 << 14) 126296064Sjmcneill#define PADCTRL1_REG_PLRCK (1 << 13) 127296064Sjmcneill#define PADCTRL1_REG_EMP (0x7 << 10) 128296064Sjmcneill#define PADCTRL1_REG_EMP_EN (0x2 << 10) 129296064Sjmcneill#define PADCTRL1_REG_CD (0x3 << 8) 130296064Sjmcneill#define PADCTRL1_REG_CKSS (0x3 << 6) 131296064Sjmcneill#define PADCTRL1_REG_CKSS_1X (0x1 << 6) 132296064Sjmcneill#define PADCTRL1_REG_CKSS_2X (0x0 << 6) 133296064Sjmcneill#define PADCTRL1_REG_AMP (0x7 << 3) 134296064Sjmcneill#define PADCTRL1_REG_AMP_EN (0x6 << 3) 135296064Sjmcneill#define PADCTRL1_REG_PLR (0x7 << 0) 136296064Sjmcneill#define HDMI_PLLCTRL0 0x208 137296064Sjmcneill#define PLLCTRL0_PLL_EN (1 << 31) 138296064Sjmcneill#define PLLCTRL0_BWS (1 << 30) 139296064Sjmcneill#define PLLCTRL0_HV_IS_33 (1 << 29) 140296064Sjmcneill#define PLLCTRL0_LDO1_EN (1 << 28) 141296064Sjmcneill#define PLLCTRL0_LDO2_EN (1 << 27) 142296064Sjmcneill#define PLLCTRL0_SDIV2 (1 << 25) 143296064Sjmcneill#define PLLCTRL0_VCO_GAIN (0x1 << 22) 144296064Sjmcneill#define PLLCTRL0_S (0x7 << 17) 145296064Sjmcneill#define PLLCTRL0_CP_S (0xf << 12) 146296064Sjmcneill#define PLLCTRL0_CS (0x7 << 8) 147296064Sjmcneill#define PLLCTRL0_PREDIV(x) ((x) << 4) 148296064Sjmcneill#define PLLCTRL0_VCO_S (0x8 << 0) 149296064Sjmcneill#define HDMI_PLLDBG0 0x20c 150296064Sjmcneill#define PLLDBG0_CKIN_SEL (1 << 21) 151296064Sjmcneill#define PLLDBG0_CKIN_SEL_PLL3 (0 << 21) 152296064Sjmcneill#define PLLDBG0_CKIN_SEL_PLL7 (1 << 21) 153296064Sjmcneill#define HDMI_PKTCTRL0 0x2f0 154296064Sjmcneill#define HDMI_PKTCTRL1 0x2f4 155296064Sjmcneill#define PKTCTRL_PACKET(n,t) ((t) << ((n) << 2)) 156296064Sjmcneill#define PKT_NULL 0 157296064Sjmcneill#define PKT_GC 1 158296064Sjmcneill#define PKT_AVI 2 159296064Sjmcneill#define PKT_AI 3 160296064Sjmcneill#define PKT_SPD 5 161296064Sjmcneill#define PKT_END 15 162296064Sjmcneill#define DDC_CTRL 0x500 163296064Sjmcneill#define CTRL_DDC_EN (1 << 31) 164296064Sjmcneill#define CTRL_DDC_ACMD_START (1 << 30) 165296064Sjmcneill#define CTRL_DDC_FIFO_DIR (1 << 8) 166296064Sjmcneill#define CTRL_DDC_FIFO_DIR_READ (0 << 8) 167296064Sjmcneill#define CTRL_DDC_FIFO_DIR_WRITE (1 << 8) 168296064Sjmcneill#define CTRL_DDC_SWRST (1 << 0) 169296064Sjmcneill#define DDC_SLAVE_ADDR 0x504 170296064Sjmcneill#define SLAVE_ADDR_SEG_SHIFT 24 171296064Sjmcneill#define SLAVE_ADDR_EDDC_SHIFT 16 172296064Sjmcneill#define SLAVE_ADDR_OFFSET_SHIFT 8 173296064Sjmcneill#define SLAVE_ADDR_SHIFT 0 174296064Sjmcneill#define DDC_INT_STATUS 0x50c 175296064Sjmcneill#define INT_STATUS_XFER_DONE (1 << 0) 176296064Sjmcneill#define DDC_FIFO_CTRL 0x510 177296064Sjmcneill#define FIFO_CTRL_CLEAR (1 << 31) 178296064Sjmcneill#define DDC_BYTE_COUNTER 0x51c 179296064Sjmcneill#define DDC_COMMAND 0x520 180296064Sjmcneill#define COMMAND_EOREAD (4 << 0) 181296064Sjmcneill#define DDC_CLOCK 0x528 182296064Sjmcneill#define DDC_CLOCK_M (1 << 3) 183296064Sjmcneill#define DDC_CLOCK_N (5 << 0) 184296064Sjmcneill#define DDC_FIFO 0x518 185296064Sjmcneill#define SWRST_DELAY 1000 186296064Sjmcneill#define DDC_DELAY 1000 187296064Sjmcneill#define DDC_RETRY 1000 188296064Sjmcneill#define DDC_BLKLEN 16 189296064Sjmcneill#define DDC_ADDR 0x50 190296064Sjmcneill#define EDDC_ADDR 0x60 191296064Sjmcneill#define EDID_LENGTH 128 192296064Sjmcneill#define HDMI_ENABLE_DELAY 50000 193296064Sjmcneill#define DDC_READ_RETRY 4 194296064Sjmcneill#define EXT_TAG 0x00 195296064Sjmcneill#define CEA_TAG_ID 0x02 196296064Sjmcneill#define CEA_DTD 0x03 197296064Sjmcneill#define DTD_BASIC_AUDIO (1 << 6) 198296064Sjmcneill 199296064Sjmcneillstruct a10hdmi_softc { 200296064Sjmcneill struct resource *res; 201296064Sjmcneill 202296064Sjmcneill struct intr_config_hook mode_hook; 203296064Sjmcneill 204296064Sjmcneill uint8_t edid[EDID_LENGTH]; 205296064Sjmcneill 206296789Sjmcneill int has_hdmi; 207296064Sjmcneill int has_audio; 208296064Sjmcneill}; 209296064Sjmcneill 210296064Sjmcneillstatic struct resource_spec a10hdmi_spec[] = { 211296064Sjmcneill { SYS_RES_MEMORY, 0, RF_ACTIVE }, 212296064Sjmcneill { -1, 0 } 213296064Sjmcneill}; 214296064Sjmcneill 215296064Sjmcneill#define HDMI_READ(sc, reg) bus_read_4((sc)->res, (reg)) 216296064Sjmcneill#define HDMI_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) 217296064Sjmcneill 218296064Sjmcneillstatic void 219296064Sjmcneilla10hdmi_init(struct a10hdmi_softc *sc) 220296064Sjmcneill{ 221296064Sjmcneill /* Enable the HDMI module */ 222296064Sjmcneill HDMI_WRITE(sc, HDMI_CTRL, CTRL_MODULE_EN); 223296064Sjmcneill 224296064Sjmcneill /* Configure PLL/DRV settings */ 225296064Sjmcneill HDMI_WRITE(sc, HDMI_PADCTRL0, PADCTRL0_BIASEN | PADCTRL0_LDOCEN | 226296064Sjmcneill PADCTRL0_LDODEN | PADCTRL0_PWENC | PADCTRL0_PWEND | 227296064Sjmcneill PADCTRL0_PWENG | PADCTRL0_CKEN | PADCTRL0_TXEN); 228296064Sjmcneill HDMI_WRITE(sc, HDMI_PADCTRL1, PADCTRL1_AMP_OPT | PADCTRL1_AMPCK_OPT | 229296064Sjmcneill PADCTRL1_EMP_OPT | PADCTRL1_EMPCK_OPT | PADCTRL1_REG_DEN | 230296064Sjmcneill PADCTRL1_REG_DENCK | PADCTRL1_REG_EMP_EN | PADCTRL1_REG_AMP_EN); 231296064Sjmcneill 232296064Sjmcneill /* Select PLL3 as input clock */ 233296064Sjmcneill HDMI_WRITE(sc, HDMI_PLLDBG0, PLLDBG0_CKIN_SEL_PLL3); 234296064Sjmcneill 235296064Sjmcneill DELAY(HDMI_ENABLE_DELAY); 236296064Sjmcneill} 237296064Sjmcneill 238296064Sjmcneillstatic void 239296064Sjmcneilla10hdmi_hpd(void *arg) 240296064Sjmcneill{ 241296064Sjmcneill struct a10hdmi_softc *sc; 242296064Sjmcneill device_t dev; 243296064Sjmcneill uint32_t hpd; 244296064Sjmcneill 245296064Sjmcneill dev = arg; 246296064Sjmcneill sc = device_get_softc(dev); 247296064Sjmcneill 248296064Sjmcneill hpd = HDMI_READ(sc, HDMI_HPD); 249296064Sjmcneill if ((hpd & HPD_DET) == HPD_DET) 250296064Sjmcneill EVENTHANDLER_INVOKE(hdmi_event, dev, HDMI_EVENT_CONNECTED); 251296064Sjmcneill 252296064Sjmcneill config_intrhook_disestablish(&sc->mode_hook); 253296064Sjmcneill} 254296064Sjmcneill 255296064Sjmcneillstatic int 256296064Sjmcneilla10hdmi_probe(device_t dev) 257296064Sjmcneill{ 258296064Sjmcneill if (!ofw_bus_status_okay(dev)) 259296064Sjmcneill return (ENXIO); 260296064Sjmcneill 261296064Sjmcneill if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-hdmi")) 262296064Sjmcneill return (ENXIO); 263296064Sjmcneill 264296064Sjmcneill device_set_desc(dev, "Allwinner HDMI TX"); 265296064Sjmcneill return (BUS_PROBE_DEFAULT); 266296064Sjmcneill} 267296064Sjmcneill 268296064Sjmcneillstatic int 269296064Sjmcneilla10hdmi_attach(device_t dev) 270296064Sjmcneill{ 271296064Sjmcneill struct a10hdmi_softc *sc; 272296064Sjmcneill int error; 273296064Sjmcneill 274296064Sjmcneill sc = device_get_softc(dev); 275296064Sjmcneill 276296064Sjmcneill if (bus_alloc_resources(dev, a10hdmi_spec, &sc->res)) { 277296064Sjmcneill device_printf(dev, "cannot allocate resources for device\n"); 278296064Sjmcneill return (ENXIO); 279296064Sjmcneill } 280296064Sjmcneill 281296064Sjmcneill a10_clk_hdmi_activate(); 282296064Sjmcneill 283296064Sjmcneill a10hdmi_init(sc); 284296064Sjmcneill 285296064Sjmcneill sc->mode_hook.ich_func = a10hdmi_hpd; 286296064Sjmcneill sc->mode_hook.ich_arg = dev; 287296064Sjmcneill 288296064Sjmcneill error = config_intrhook_establish(&sc->mode_hook); 289296064Sjmcneill if (error != 0) 290296064Sjmcneill return (error); 291296064Sjmcneill 292296064Sjmcneill return (0); 293296064Sjmcneill} 294296064Sjmcneill 295296064Sjmcneillstatic int 296296064Sjmcneilla10hdmi_ddc_xfer(struct a10hdmi_softc *sc, uint16_t addr, uint8_t seg, 297296064Sjmcneill uint8_t off, int len) 298296064Sjmcneill{ 299296064Sjmcneill uint32_t val; 300296064Sjmcneill int retry; 301296064Sjmcneill 302296064Sjmcneill /* Set FIFO direction to read */ 303296064Sjmcneill val = HDMI_READ(sc, DDC_CTRL); 304296064Sjmcneill val &= ~CTRL_DDC_FIFO_DIR; 305296064Sjmcneill val |= CTRL_DDC_FIFO_DIR_READ; 306296064Sjmcneill HDMI_WRITE(sc, DDC_CTRL, val); 307296064Sjmcneill 308296064Sjmcneill /* Setup DDC slave address */ 309296064Sjmcneill val = (addr << SLAVE_ADDR_SHIFT) | (seg << SLAVE_ADDR_SEG_SHIFT) | 310296064Sjmcneill (EDDC_ADDR << SLAVE_ADDR_EDDC_SHIFT) | 311296064Sjmcneill (off << SLAVE_ADDR_OFFSET_SHIFT); 312296064Sjmcneill HDMI_WRITE(sc, DDC_SLAVE_ADDR, val); 313296064Sjmcneill 314296064Sjmcneill /* Clear FIFO */ 315296064Sjmcneill val = HDMI_READ(sc, DDC_FIFO_CTRL); 316296064Sjmcneill val |= FIFO_CTRL_CLEAR; 317296064Sjmcneill HDMI_WRITE(sc, DDC_FIFO_CTRL, val); 318296064Sjmcneill 319296064Sjmcneill /* Set transfer length */ 320296064Sjmcneill HDMI_WRITE(sc, DDC_BYTE_COUNTER, len); 321296064Sjmcneill 322296064Sjmcneill /* Set command to "Explicit Offset Address Read" */ 323296064Sjmcneill HDMI_WRITE(sc, DDC_COMMAND, COMMAND_EOREAD); 324296064Sjmcneill 325296064Sjmcneill /* Start transfer */ 326296064Sjmcneill val = HDMI_READ(sc, DDC_CTRL); 327296064Sjmcneill val |= CTRL_DDC_ACMD_START; 328296064Sjmcneill HDMI_WRITE(sc, DDC_CTRL, val); 329296064Sjmcneill 330296064Sjmcneill /* Wait for command to start */ 331296064Sjmcneill retry = DDC_RETRY; 332296064Sjmcneill while (--retry > 0) { 333296064Sjmcneill val = HDMI_READ(sc, DDC_CTRL); 334296064Sjmcneill if ((val & CTRL_DDC_ACMD_START) == 0) 335296064Sjmcneill break; 336296064Sjmcneill DELAY(DDC_DELAY); 337296064Sjmcneill } 338296064Sjmcneill if (retry == 0) 339296064Sjmcneill return (ETIMEDOUT); 340296064Sjmcneill 341296064Sjmcneill /* Ensure that the transfer completed */ 342296064Sjmcneill val = HDMI_READ(sc, DDC_INT_STATUS); 343296064Sjmcneill if ((val & INT_STATUS_XFER_DONE) == 0) 344296064Sjmcneill return (EIO); 345296064Sjmcneill 346296064Sjmcneill return (0); 347296064Sjmcneill} 348296064Sjmcneill 349296064Sjmcneillstatic int 350296064Sjmcneilla10hdmi_ddc_read(struct a10hdmi_softc *sc, int block, uint8_t *edid) 351296064Sjmcneill{ 352296064Sjmcneill int resid, off, len, error; 353296064Sjmcneill uint8_t *pbuf; 354296064Sjmcneill 355296064Sjmcneill pbuf = edid; 356296064Sjmcneill resid = EDID_LENGTH; 357296064Sjmcneill off = (block & 1) ? EDID_LENGTH : 0; 358296064Sjmcneill 359296064Sjmcneill while (resid > 0) { 360296064Sjmcneill len = min(resid, DDC_BLKLEN); 361296064Sjmcneill error = a10hdmi_ddc_xfer(sc, DDC_ADDR, block >> 1, off, len); 362296064Sjmcneill if (error != 0) 363296064Sjmcneill return (error); 364296064Sjmcneill 365296064Sjmcneill bus_read_multi_1(sc->res, DDC_FIFO, pbuf, len); 366296064Sjmcneill 367296064Sjmcneill pbuf += len; 368296064Sjmcneill off += len; 369296064Sjmcneill resid -= len; 370296064Sjmcneill } 371296064Sjmcneill 372296064Sjmcneill return (0); 373296064Sjmcneill} 374296064Sjmcneill 375296789Sjmcneillstatic void 376296789Sjmcneilla10hdmi_detect_hdmi(struct a10hdmi_softc *sc, int *phdmi, int *paudio) 377296064Sjmcneill{ 378296064Sjmcneill struct edid_info ei; 379296064Sjmcneill uint8_t edid[EDID_LENGTH]; 380296064Sjmcneill int block; 381296064Sjmcneill 382296789Sjmcneill *phdmi = *paudio = 0; 383296789Sjmcneill 384296064Sjmcneill if (edid_parse(sc->edid, &ei) != 0) 385296789Sjmcneill return; 386296064Sjmcneill 387296064Sjmcneill /* Scan through extension blocks, looking for a CEA-861 block. */ 388296064Sjmcneill for (block = 1; block <= ei.edid_ext_block_count; block++) { 389296064Sjmcneill if (a10hdmi_ddc_read(sc, block, edid) != 0) 390296789Sjmcneill return; 391296064Sjmcneill 392296789Sjmcneill if (edid[EXT_TAG] == CEA_TAG_ID) { 393296789Sjmcneill *phdmi = 1; 394296789Sjmcneill *paudio = ((edid[CEA_DTD] & DTD_BASIC_AUDIO) != 0); 395296789Sjmcneill return; 396296789Sjmcneill } 397296064Sjmcneill } 398296064Sjmcneill} 399296064Sjmcneill 400296064Sjmcneillstatic int 401296064Sjmcneilla10hdmi_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len) 402296064Sjmcneill{ 403296064Sjmcneill struct a10hdmi_softc *sc; 404296064Sjmcneill int error, retry; 405296064Sjmcneill 406296064Sjmcneill sc = device_get_softc(dev); 407296064Sjmcneill retry = DDC_READ_RETRY; 408296064Sjmcneill 409296064Sjmcneill while (--retry > 0) { 410296064Sjmcneill /* I2C software reset */ 411296064Sjmcneill HDMI_WRITE(sc, DDC_FIFO_CTRL, 0); 412296064Sjmcneill HDMI_WRITE(sc, DDC_CTRL, CTRL_DDC_EN | CTRL_DDC_SWRST); 413296064Sjmcneill DELAY(SWRST_DELAY); 414296064Sjmcneill if (HDMI_READ(sc, DDC_CTRL) & CTRL_DDC_SWRST) { 415296064Sjmcneill device_printf(dev, "DDC software reset failed\n"); 416296064Sjmcneill return (ENXIO); 417296064Sjmcneill } 418296064Sjmcneill 419296064Sjmcneill /* Configure DDC clock */ 420296064Sjmcneill HDMI_WRITE(sc, DDC_CLOCK, DDC_CLOCK_M | DDC_CLOCK_N); 421296064Sjmcneill 422296064Sjmcneill /* Read EDID block */ 423296064Sjmcneill error = a10hdmi_ddc_read(sc, 0, sc->edid); 424296064Sjmcneill if (error == 0) { 425296064Sjmcneill *edid = sc->edid; 426296064Sjmcneill *edid_len = sizeof(sc->edid); 427296064Sjmcneill break; 428296064Sjmcneill } 429296064Sjmcneill } 430296064Sjmcneill 431296064Sjmcneill if (error == 0) 432296789Sjmcneill a10hdmi_detect_hdmi(sc, &sc->has_hdmi, &sc->has_audio); 433296064Sjmcneill else 434296789Sjmcneill sc->has_hdmi = sc->has_audio = 0; 435296064Sjmcneill 436296064Sjmcneill return (error); 437296064Sjmcneill} 438296064Sjmcneill 439296064Sjmcneillstatic void 440296064Sjmcneilla10hdmi_set_audiomode(device_t dev, const struct videomode *mode) 441296064Sjmcneill{ 442296064Sjmcneill struct a10hdmi_softc *sc; 443296064Sjmcneill uint32_t val; 444296064Sjmcneill int retry; 445296064Sjmcneill 446296064Sjmcneill sc = device_get_softc(dev); 447296064Sjmcneill 448296064Sjmcneill /* Disable and reset audio module and wait for reset bit to clear */ 449296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_CTRL, AUD_CTRL_RST); 450296064Sjmcneill for (retry = HDMI_AUDIO_RESET_RETRY; retry > 0; retry--) { 451296064Sjmcneill val = HDMI_READ(sc, HDMI_AUD_CTRL); 452296064Sjmcneill if ((val & AUD_CTRL_RST) == 0) 453296064Sjmcneill break; 454296064Sjmcneill } 455296064Sjmcneill if (retry == 0) { 456296064Sjmcneill device_printf(dev, "timeout waiting for audio module\n"); 457296064Sjmcneill return; 458296064Sjmcneill } 459296064Sjmcneill 460296064Sjmcneill if (!sc->has_audio) 461296064Sjmcneill return; 462296064Sjmcneill 463296064Sjmcneill /* DMA and FIFO control */ 464296064Sjmcneill HDMI_WRITE(sc, HDMI_ADMA_CTRL, HDMI_ADMA_MODE_DDMA); 465296064Sjmcneill 466296064Sjmcneill /* Audio format control (LPCM, S16LE, stereo) */ 467296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_FMT, AUD_FMT_CH(HDMI_AUDIO_CHANNELS)); 468296064Sjmcneill 469296064Sjmcneill /* Channel mappings */ 470296064Sjmcneill HDMI_WRITE(sc, HDMI_PCM_CTRL, HDMI_AUDIO_CHANNELMAP); 471296064Sjmcneill 472296064Sjmcneill /* Clocks */ 473296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_CTS, 474296064Sjmcneill HDMI_AUDIO_CTS(mode->dot_clock, HDMI_AUDIO_N)); 475296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_N, HDMI_AUDIO_N); 476296064Sjmcneill 477296064Sjmcneill /* Set sampling frequency to 48 kHz, word length to 16-bit */ 478296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_CH_STATUS0, CH_STATUS0_FS_FREQ_48); 479296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_CH_STATUS1, CH_STATUS1_WORD_LEN_16); 480296064Sjmcneill 481296064Sjmcneill /* Enable */ 482296064Sjmcneill HDMI_WRITE(sc, HDMI_AUD_CTRL, AUD_CTRL_EN); 483296064Sjmcneill} 484296064Sjmcneill 485296064Sjmcneillstatic int 486296064Sjmcneilla10hdmi_set_videomode(device_t dev, const struct videomode *mode) 487296064Sjmcneill{ 488296064Sjmcneill struct a10hdmi_softc *sc; 489296064Sjmcneill int error, clk_div, clk_dbl; 490296064Sjmcneill int dblscan, hfp, hspw, hbp, vfp, vspw, vbp; 491296064Sjmcneill uint32_t val; 492296064Sjmcneill 493296064Sjmcneill sc = device_get_softc(dev); 494296064Sjmcneill dblscan = !!(mode->flags & VID_DBLSCAN); 495296064Sjmcneill hfp = mode->hsync_start - mode->hdisplay; 496296064Sjmcneill hspw = mode->hsync_end - mode->hsync_start; 497296064Sjmcneill hbp = mode->htotal - mode->hsync_start; 498296064Sjmcneill vfp = mode->vsync_start - mode->vdisplay; 499296064Sjmcneill vspw = mode->vsync_end - mode->vsync_start; 500296064Sjmcneill vbp = mode->vtotal - mode->vsync_start; 501296064Sjmcneill 502296064Sjmcneill error = a10_clk_tcon_get_config(&clk_div, &clk_dbl); 503296064Sjmcneill if (error != 0) 504296064Sjmcneill return (error); 505296064Sjmcneill 506296064Sjmcneill /* Clear interrupt status */ 507296064Sjmcneill HDMI_WRITE(sc, HDMI_INT_STATUS, HDMI_READ(sc, HDMI_INT_STATUS)); 508296064Sjmcneill 509296064Sjmcneill /* Clock setup */ 510296064Sjmcneill val = HDMI_READ(sc, HDMI_PADCTRL1); 511296064Sjmcneill val &= ~PADCTRL1_REG_CKSS; 512296064Sjmcneill val |= (clk_dbl ? PADCTRL1_REG_CKSS_2X : PADCTRL1_REG_CKSS_1X); 513296064Sjmcneill HDMI_WRITE(sc, HDMI_PADCTRL1, val); 514296064Sjmcneill HDMI_WRITE(sc, HDMI_PLLCTRL0, PLLCTRL0_PLL_EN | PLLCTRL0_BWS | 515296064Sjmcneill PLLCTRL0_HV_IS_33 | PLLCTRL0_LDO1_EN | PLLCTRL0_LDO2_EN | 516296064Sjmcneill PLLCTRL0_SDIV2 | PLLCTRL0_VCO_GAIN | PLLCTRL0_S | 517296064Sjmcneill PLLCTRL0_CP_S | PLLCTRL0_CS | PLLCTRL0_PREDIV(clk_div) | 518296064Sjmcneill PLLCTRL0_VCO_S); 519296064Sjmcneill 520296064Sjmcneill /* Setup display settings */ 521296789Sjmcneill val = 0; 522296789Sjmcneill if (sc->has_hdmi) 523296789Sjmcneill val |= VID_CTRL_HDMI_MODE; 524296064Sjmcneill if (mode->flags & VID_INTERLACE) 525296064Sjmcneill val |= VID_CTRL_INTERLACE; 526296064Sjmcneill if (mode->flags & VID_DBLSCAN) 527296064Sjmcneill val |= VID_CTRL_REPEATER_2X; 528296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_CTRL, val); 529296064Sjmcneill 530296064Sjmcneill /* Setup display timings */ 531296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_TIMING0, 532296064Sjmcneill VID_ACT_V(mode->vdisplay) | VID_ACT_H(mode->hdisplay << dblscan)); 533296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_TIMING1, 534296064Sjmcneill VID_VBP(vbp) | VID_HBP(hbp << dblscan)); 535296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_TIMING2, 536296064Sjmcneill VID_VFP(vfp) | VID_HFP(hfp << dblscan)); 537296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_TIMING3, 538296064Sjmcneill VID_VSPW(vspw) | VID_HSPW(hspw << dblscan)); 539296064Sjmcneill val = TX_CLOCK_NORMAL; 540296064Sjmcneill if (mode->flags & VID_PVSYNC) 541296064Sjmcneill val |= VID_VSYNC_ACTSEL; 542296064Sjmcneill if (mode->flags & VID_PHSYNC) 543296064Sjmcneill val |= VID_HSYNC_ACTSEL; 544296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_TIMING4, val); 545296064Sjmcneill 546296064Sjmcneill /* This is an ordered list of infoframe packets that the HDMI 547296064Sjmcneill * transmitter will send. Transmit packets in the following order: 548296064Sjmcneill * 1. General control packet 549296064Sjmcneill * 2. AVI infoframe 550296064Sjmcneill * 3. Audio infoframe 551296064Sjmcneill * There are 2 registers with 4 slots each. The list is terminated 552296064Sjmcneill * with the special PKT_END marker. 553296064Sjmcneill */ 554296064Sjmcneill HDMI_WRITE(sc, HDMI_PKTCTRL0, 555296064Sjmcneill PKTCTRL_PACKET(0, PKT_GC) | PKTCTRL_PACKET(1, PKT_AVI) | 556296064Sjmcneill PKTCTRL_PACKET(2, PKT_AI) | PKTCTRL_PACKET(3, PKT_END)); 557296064Sjmcneill HDMI_WRITE(sc, HDMI_PKTCTRL1, 0); 558296064Sjmcneill 559296064Sjmcneill /* Setup audio */ 560296064Sjmcneill a10hdmi_set_audiomode(dev, mode); 561296064Sjmcneill 562296064Sjmcneill return (0); 563296064Sjmcneill} 564296064Sjmcneill 565296064Sjmcneillstatic int 566296064Sjmcneilla10hdmi_enable(device_t dev, int onoff) 567296064Sjmcneill{ 568296064Sjmcneill struct a10hdmi_softc *sc; 569296064Sjmcneill uint32_t val; 570296064Sjmcneill 571296064Sjmcneill sc = device_get_softc(dev); 572296064Sjmcneill 573296064Sjmcneill /* Enable or disable video output */ 574296064Sjmcneill val = HDMI_READ(sc, HDMI_VID_CTRL); 575296064Sjmcneill if (onoff) 576296064Sjmcneill val |= VID_CTRL_VIDEO_EN; 577296064Sjmcneill else 578296064Sjmcneill val &= ~VID_CTRL_VIDEO_EN; 579296064Sjmcneill HDMI_WRITE(sc, HDMI_VID_CTRL, val); 580296064Sjmcneill 581296064Sjmcneill return (0); 582296064Sjmcneill} 583296064Sjmcneill 584296064Sjmcneillstatic device_method_t a10hdmi_methods[] = { 585296064Sjmcneill /* Device interface */ 586296064Sjmcneill DEVMETHOD(device_probe, a10hdmi_probe), 587296064Sjmcneill DEVMETHOD(device_attach, a10hdmi_attach), 588296064Sjmcneill 589296064Sjmcneill /* HDMI interface */ 590296064Sjmcneill DEVMETHOD(hdmi_get_edid, a10hdmi_get_edid), 591296064Sjmcneill DEVMETHOD(hdmi_set_videomode, a10hdmi_set_videomode), 592296064Sjmcneill DEVMETHOD(hdmi_enable, a10hdmi_enable), 593296064Sjmcneill 594296064Sjmcneill DEVMETHOD_END 595296064Sjmcneill}; 596296064Sjmcneill 597296064Sjmcneillstatic driver_t a10hdmi_driver = { 598296064Sjmcneill "a10hdmi", 599296064Sjmcneill a10hdmi_methods, 600296064Sjmcneill sizeof(struct a10hdmi_softc), 601296064Sjmcneill}; 602296064Sjmcneill 603296064Sjmcneillstatic devclass_t a10hdmi_devclass; 604296064Sjmcneill 605296064SjmcneillDRIVER_MODULE(a10hdmi, simplebus, a10hdmi_driver, a10hdmi_devclass, 0, 0); 606296064SjmcneillMODULE_VERSION(a10hdmi, 1); 607