1259863Sneel/*- 2259863Sneel * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 3259863Sneel * All rights reserved. 4259863Sneel * 5259863Sneel * Redistribution and use in source and binary forms, with or without 6259863Sneel * modification, are permitted provided that the following conditions 7259863Sneel * are met: 8259863Sneel * 1. Redistributions of source code must retain the above copyright 9259863Sneel * notice, this list of conditions and the following disclaimer. 10259863Sneel * 2. Redistributions in binary form must reproduce the above copyright 11259863Sneel * notice, this list of conditions and the following disclaimer in the 12259863Sneel * documentation and/or other materials provided with the distribution. 13259863Sneel * 14259863Sneel * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15259863Sneel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16259863Sneel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17259863Sneel * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18259863Sneel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19259863Sneel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20259863Sneel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21259863Sneel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22259863Sneel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23259863Sneel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24259863Sneel * SUCH DAMAGE. 25259863Sneel * 26259863Sneel * $FreeBSD$ 27259863Sneel */ 28259863Sneel 29259863Sneel#ifndef _VLAPIC_PRIV_H_ 30259863Sneel#define _VLAPIC_PRIV_H_ 31259863Sneel 32259978Sneel#include <x86/apicreg.h> 33259978Sneel 34259863Sneel/* 35259863Sneel * APIC Register: Offset Description 36259863Sneel */ 37259863Sneel#define APIC_OFFSET_ID 0x20 /* Local APIC ID */ 38259863Sneel#define APIC_OFFSET_VER 0x30 /* Local APIC Version */ 39259863Sneel#define APIC_OFFSET_TPR 0x80 /* Task Priority Register */ 40259863Sneel#define APIC_OFFSET_APR 0x90 /* Arbitration Priority */ 41259863Sneel#define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */ 42259863Sneel#define APIC_OFFSET_EOI 0xB0 /* EOI Register */ 43259863Sneel#define APIC_OFFSET_RRR 0xC0 /* Remote read */ 44259863Sneel#define APIC_OFFSET_LDR 0xD0 /* Logical Destination */ 45259863Sneel#define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */ 46259863Sneel#define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */ 47259863Sneel#define APIC_OFFSET_ISR0 0x100 /* In Service Register */ 48259863Sneel#define APIC_OFFSET_ISR1 0x110 49259863Sneel#define APIC_OFFSET_ISR2 0x120 50259863Sneel#define APIC_OFFSET_ISR3 0x130 51259863Sneel#define APIC_OFFSET_ISR4 0x140 52259863Sneel#define APIC_OFFSET_ISR5 0x150 53259863Sneel#define APIC_OFFSET_ISR6 0x160 54259863Sneel#define APIC_OFFSET_ISR7 0x170 55259863Sneel#define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */ 56259863Sneel#define APIC_OFFSET_TMR1 0x190 57259863Sneel#define APIC_OFFSET_TMR2 0x1A0 58259863Sneel#define APIC_OFFSET_TMR3 0x1B0 59259863Sneel#define APIC_OFFSET_TMR4 0x1C0 60259863Sneel#define APIC_OFFSET_TMR5 0x1D0 61259863Sneel#define APIC_OFFSET_TMR6 0x1E0 62259863Sneel#define APIC_OFFSET_TMR7 0x1F0 63259863Sneel#define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */ 64259863Sneel#define APIC_OFFSET_IRR1 0x210 65259863Sneel#define APIC_OFFSET_IRR2 0x220 66259863Sneel#define APIC_OFFSET_IRR3 0x230 67259863Sneel#define APIC_OFFSET_IRR4 0x240 68259863Sneel#define APIC_OFFSET_IRR5 0x250 69259863Sneel#define APIC_OFFSET_IRR6 0x260 70259863Sneel#define APIC_OFFSET_IRR7 0x270 71259863Sneel#define APIC_OFFSET_ESR 0x280 /* Error Status Register */ 72259863Sneel#define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */ 73259863Sneel#define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */ 74259863Sneel#define APIC_OFFSET_ICR_HI 0x310 75259863Sneel#define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */ 76259863Sneel#define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */ 77259863Sneel#define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */ 78259863Sneel#define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */ 79259863Sneel#define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */ 80259863Sneel#define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */ 81259863Sneel#define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */ 82259863Sneel#define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */ 83259863Sneel#define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */ 84262140Sneel#define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */ 85259863Sneel 86260410Sneel#define VLAPIC_CTR0(vlapic, format) \ 87260410Sneel VCPU_CTR0((vlapic)->vm, (vlapic)->vcpuid, format) 88260410Sneel 89260410Sneel#define VLAPIC_CTR1(vlapic, format, p1) \ 90260410Sneel VCPU_CTR1((vlapic)->vm, (vlapic)->vcpuid, format, p1) 91260410Sneel 92260410Sneel#define VLAPIC_CTR2(vlapic, format, p1, p2) \ 93260410Sneel VCPU_CTR2((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2) 94260410Sneel 95262140Sneel#define VLAPIC_CTR3(vlapic, format, p1, p2, p3) \ 96262140Sneel VCPU_CTR3((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2, p3) 97262140Sneel 98260410Sneel#define VLAPIC_CTR_IRR(vlapic, msg) \ 99260410Sneeldo { \ 100260410Sneel uint32_t *irrptr = &(vlapic)->apic_page->irr0; \ 101260410Sneel irrptr[0] = irrptr[0]; /* silence compiler */ \ 102260410Sneel VLAPIC_CTR1((vlapic), msg " irr0 0x%08x", irrptr[0 << 2]); \ 103260410Sneel VLAPIC_CTR1((vlapic), msg " irr1 0x%08x", irrptr[1 << 2]); \ 104260410Sneel VLAPIC_CTR1((vlapic), msg " irr2 0x%08x", irrptr[2 << 2]); \ 105260410Sneel VLAPIC_CTR1((vlapic), msg " irr3 0x%08x", irrptr[3 << 2]); \ 106260410Sneel VLAPIC_CTR1((vlapic), msg " irr4 0x%08x", irrptr[4 << 2]); \ 107260410Sneel VLAPIC_CTR1((vlapic), msg " irr5 0x%08x", irrptr[5 << 2]); \ 108260410Sneel VLAPIC_CTR1((vlapic), msg " irr6 0x%08x", irrptr[6 << 2]); \ 109260410Sneel VLAPIC_CTR1((vlapic), msg " irr7 0x%08x", irrptr[7 << 2]); \ 110260410Sneel} while (0) 111260410Sneel 112260410Sneel#define VLAPIC_CTR_ISR(vlapic, msg) \ 113260410Sneeldo { \ 114260410Sneel uint32_t *isrptr = &(vlapic)->apic_page->isr0; \ 115260410Sneel isrptr[0] = isrptr[0]; /* silence compiler */ \ 116260410Sneel VLAPIC_CTR1((vlapic), msg " isr0 0x%08x", isrptr[0 << 2]); \ 117260410Sneel VLAPIC_CTR1((vlapic), msg " isr1 0x%08x", isrptr[1 << 2]); \ 118260410Sneel VLAPIC_CTR1((vlapic), msg " isr2 0x%08x", isrptr[2 << 2]); \ 119260410Sneel VLAPIC_CTR1((vlapic), msg " isr3 0x%08x", isrptr[3 << 2]); \ 120260410Sneel VLAPIC_CTR1((vlapic), msg " isr4 0x%08x", isrptr[4 << 2]); \ 121260410Sneel VLAPIC_CTR1((vlapic), msg " isr5 0x%08x", isrptr[5 << 2]); \ 122260410Sneel VLAPIC_CTR1((vlapic), msg " isr6 0x%08x", isrptr[6 << 2]); \ 123260410Sneel VLAPIC_CTR1((vlapic), msg " isr7 0x%08x", isrptr[7 << 2]); \ 124260410Sneel} while (0) 125260410Sneel 126259863Sneelenum boot_state { 127259863Sneel BS_INIT, 128259863Sneel BS_SIPI, 129259863Sneel BS_RUNNING 130259863Sneel}; 131259863Sneel 132259863Sneel/* 133259863Sneel * 16 priority levels with at most one vector injected per level. 134259863Sneel */ 135259863Sneel#define ISRVEC_STK_SIZE (16 + 1) 136259863Sneel 137259978Sneel#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI 138259978Sneel 139260410Sneelstruct vlapic; 140260410Sneel 141260410Sneelstruct vlapic_ops { 142260410Sneel int (*set_intr_ready)(struct vlapic *vlapic, int vector, bool level); 143260410Sneel int (*pending_intr)(struct vlapic *vlapic, int *vecptr); 144260410Sneel void (*intr_accepted)(struct vlapic *vlapic, int vector); 145260410Sneel void (*post_intr)(struct vlapic *vlapic, int hostcpu); 146261170Sneel void (*set_tmr)(struct vlapic *vlapic, int vector, bool level); 147262281Sneel void (*enable_x2apic_mode)(struct vlapic *vlapic); 148260410Sneel}; 149260410Sneel 150259863Sneelstruct vlapic { 151259863Sneel struct vm *vm; 152259863Sneel int vcpuid; 153259863Sneel struct LAPIC *apic_page; 154260410Sneel struct vlapic_ops ops; 155259863Sneel 156259863Sneel uint32_t esr_pending; 157259863Sneel int esr_firing; 158259863Sneel 159259863Sneel struct callout callout; /* vlapic timer */ 160259863Sneel struct bintime timer_fire_bt; /* callout expiry time */ 161259863Sneel struct bintime timer_freq_bt; /* timer frequency */ 162259863Sneel struct bintime timer_period_bt; /* timer period */ 163259863Sneel struct mtx timer_mtx; 164259863Sneel 165259863Sneel /* 166259863Sneel * The 'isrvec_stk' is a stack of vectors injected by the local apic. 167259863Sneel * A vector is popped from the stack when the processor does an EOI. 168259863Sneel * The vector on the top of the stack is used to compute the 169259863Sneel * Processor Priority in conjunction with the TPR. 170259863Sneel */ 171259978Sneel uint8_t isrvec_stk[ISRVEC_STK_SIZE]; 172259978Sneel int isrvec_stk_top; 173259863Sneel 174259978Sneel uint64_t msr_apicbase; 175259978Sneel enum boot_state boot_state; 176259978Sneel 177259978Sneel /* 178259978Sneel * Copies of some registers in the virtual APIC page. We do this for 179259978Sneel * a couple of different reasons: 180259978Sneel * - to be able to detect what changed (e.g. svr_last) 181259978Sneel * - to maintain a coherent snapshot of the register (e.g. lvt_last) 182259978Sneel */ 183259978Sneel uint32_t svr_last; 184259978Sneel uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1]; 185259863Sneel}; 186259863Sneel 187259863Sneelvoid vlapic_init(struct vlapic *vlapic); 188259863Sneelvoid vlapic_cleanup(struct vlapic *vlapic); 189259863Sneel 190259863Sneel#endif /* _VLAPIC_PRIV_H_ */ 191