1221828Sgrehan/*-
2221828Sgrehan * Copyright (c) 2011 NetApp, Inc.
3221828Sgrehan * All rights reserved.
4221828Sgrehan *
5221828Sgrehan * Redistribution and use in source and binary forms, with or without
6221828Sgrehan * modification, are permitted provided that the following conditions
7221828Sgrehan * are met:
8221828Sgrehan * 1. Redistributions of source code must retain the above copyright
9221828Sgrehan *    notice, this list of conditions and the following disclaimer.
10221828Sgrehan * 2. Redistributions in binary form must reproduce the above copyright
11221828Sgrehan *    notice, this list of conditions and the following disclaimer in the
12221828Sgrehan *    documentation and/or other materials provided with the distribution.
13221828Sgrehan *
14221828Sgrehan * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15221828Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16221828Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17221828Sgrehan * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18221828Sgrehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19221828Sgrehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20221828Sgrehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21221828Sgrehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22221828Sgrehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23221828Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24221828Sgrehan * SUCH DAMAGE.
25221828Sgrehan *
26221828Sgrehan * $FreeBSD: stable/11/sys/amd64/vmm/io/vlapic.h 360432 2020-04-28 08:28:13Z grehan $
27221828Sgrehan */
28221828Sgrehan
29221828Sgrehan#ifndef _VLAPIC_H_
30221828Sgrehan#define	_VLAPIC_H_
31221828Sgrehan
32221828Sgrehanstruct vm;
33240943Sneelenum x2apic_state;
34240943Sneel
35262236Sneelint vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
36262236Sneel    uint64_t data, bool *retu);
37262236Sneelint vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
38262236Sneel    uint64_t *data, bool *retu);
39259863Sneel
40259863Sneel/*
41260383Sneel * Returns 0 if there is no eligible vector that can be delivered to the
42260383Sneel * guest at this time and non-zero otherwise.
43259863Sneel *
44260383Sneel * If an eligible vector number is found and 'vecptr' is not NULL then it will
45260383Sneel * be stored in the location pointed to by 'vecptr'.
46260383Sneel *
47259863Sneel * Note that the vector does not automatically transition to the ISR as a
48259863Sneel * result of calling this function.
49259863Sneel */
50260383Sneelint vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
51259863Sneel
52259863Sneel/*
53259863Sneel * Transition 'vector' from IRR to ISR. This function is called with the
54259863Sneel * vector returned by 'vlapic_pending_intr()' when the guest is able to
55259863Sneel * accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
56259863Sneel * block interrupt delivery).
57259863Sneel */
58221828Sgrehanvoid vlapic_intr_accepted(struct vlapic *vlapic, int vector);
59259863Sneel
60260383Sneel/*
61260383Sneel * Returns 1 if the vcpu needs to be notified of the interrupt and 0 otherwise.
62260383Sneel */
63260383Sneelint vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level);
64260383Sneel
65260383Sneel/*
66260383Sneel * Post an interrupt to the vcpu running on 'hostcpu'. This will use a
67260383Sneel * hardware assist if available (e.g. Posted Interrupt) or fall back to
68260466Sneel * sending an 'ipinum' to interrupt the 'hostcpu'.
69260383Sneel */
70260466Sneelvoid vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum);
71260383Sneel
72259779Sjhbvoid vlapic_set_error(struct vlapic *vlapic, uint32_t mask);
73259779Sjhbvoid vlapic_fire_cmci(struct vlapic *vlapic);
74259779Sjhbint vlapic_trigger_lvt(struct vlapic *vlapic, int vector);
75221828Sgrehan
76360432Sgrehanvoid vlapic_sync_tpr(struct vlapic *vlapic);
77360432Sgrehan
78240772Sneeluint64_t vlapic_get_apicbase(struct vlapic *vlapic);
79262236Sneelint vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val);
80240943Sneelvoid vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state s);
81259081Sneelbool vlapic_enabled(struct vlapic *vlapic);
82240772Sneel
83259482Sneelvoid vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
84259482Sneel    int delmode, int vec);
85259924Sneel
86260619Sneel/* Reset the trigger-mode bits for all vectors to be edge-triggered */
87260619Sneelvoid vlapic_reset_tmr(struct vlapic *vlapic);
88260619Sneel
89260619Sneel/*
90260619Sneel * Set the trigger-mode bit associated with 'vector' to level-triggered if
91260619Sneel * the (dest,phys,delmode) tuple resolves to an interrupt being delivered to
92260619Sneel * this 'vlapic'.
93260619Sneel */
94260619Sneelvoid vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,
95260619Sneel    int delmode, int vector);
96260619Sneel
97267300Sneelvoid vlapic_set_cr8(struct vlapic *vlapic, uint64_t val);
98267300Sneeluint64_t vlapic_get_cr8(struct vlapic *vlapic);
99267178Stychon
100259924Sneel/* APIC write handlers */
101259924Sneelvoid vlapic_id_write_handler(struct vlapic *vlapic);
102259924Sneelvoid vlapic_ldr_write_handler(struct vlapic *vlapic);
103259924Sneelvoid vlapic_dfr_write_handler(struct vlapic *vlapic);
104259937Sneelvoid vlapic_svr_write_handler(struct vlapic *vlapic);
105259961Sneelvoid vlapic_esr_write_handler(struct vlapic *vlapic);
106259961Sneelint vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu);
107259961Sneelvoid vlapic_icrtmr_write_handler(struct vlapic *vlapic);
108259961Sneelvoid vlapic_dcr_write_handler(struct vlapic *vlapic);
109259978Sneelvoid vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset);
110262281Sneelvoid vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val);
111221828Sgrehan#endif	/* _VLAPIC_H_ */
112