vmm_dev.h revision 284539 
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/amd64/include/vmm_dev.h 284539 2015-06-18 06:00:17Z neel $
27 */
28
29#ifndef	_VMM_DEV_H_
30#define	_VMM_DEV_H_
31
32#ifdef _KERNEL
33void	vmmdev_init(void);
34int	vmmdev_cleanup(void);
35#endif
36
37struct vm_memmap {
38	vm_paddr_t	gpa;
39	int		segid;		/* memory segment */
40	vm_ooffset_t	segoff;		/* offset into memory segment */
41	size_t		len;		/* mmap length */
42	int		prot;		/* RWX */
43	int		flags;
44};
45#define	VM_MEMMAP_F_WIRED	0x01
46#define	VM_MEMMAP_F_IOMMU	0x02
47
48#define	VM_MEMSEG_NAME(m)	((m)->name[0] != '\0' ? (m)->name : NULL)
49struct vm_memseg {
50	int		segid;
51	size_t		len;
52	char		name[SPECNAMELEN + 1];
53};
54
55struct vm_register {
56	int		cpuid;
57	int		regnum;		/* enum vm_reg_name */
58	uint64_t	regval;
59};
60
61struct vm_seg_desc {			/* data or code segment */
62	int		cpuid;
63	int		regnum;		/* enum vm_reg_name */
64	struct seg_desc desc;
65};
66
67struct vm_run {
68	int		cpuid;
69	struct vm_exit	vm_exit;
70};
71
72struct vm_exception {
73	int		cpuid;
74	int		vector;
75	uint32_t	error_code;
76	int		error_code_valid;
77	int		restart_instruction;
78};
79
80struct vm_lapic_msi {
81	uint64_t	msg;
82	uint64_t	addr;
83};
84
85struct vm_lapic_irq {
86	int		cpuid;
87	int		vector;
88};
89
90struct vm_ioapic_irq {
91	int		irq;
92};
93
94struct vm_isa_irq {
95	int		atpic_irq;
96	int		ioapic_irq;
97};
98
99struct vm_isa_irq_trigger {
100	int		atpic_irq;
101	enum vm_intr_trigger trigger;
102};
103
104struct vm_capability {
105	int		cpuid;
106	enum vm_cap_type captype;
107	int		capval;
108	int		allcpus;
109};
110
111struct vm_pptdev {
112	int		bus;
113	int		slot;
114	int		func;
115};
116
117struct vm_pptdev_mmio {
118	int		bus;
119	int		slot;
120	int		func;
121	vm_paddr_t	gpa;
122	vm_paddr_t	hpa;
123	size_t		len;
124};
125
126struct vm_pptdev_msi {
127	int		vcpu;
128	int		bus;
129	int		slot;
130	int		func;
131	int		numvec;		/* 0 means disabled */
132	uint64_t	msg;
133	uint64_t	addr;
134};
135
136struct vm_pptdev_msix {
137	int		vcpu;
138	int		bus;
139	int		slot;
140	int		func;
141	int		idx;
142	uint64_t	msg;
143	uint32_t	vector_control;
144	uint64_t	addr;
145};
146
147struct vm_nmi {
148	int		cpuid;
149};
150
151#define	MAX_VM_STATS	64
152struct vm_stats {
153	int		cpuid;				/* in */
154	int		num_entries;			/* out */
155	struct timeval	tv;
156	uint64_t	statbuf[MAX_VM_STATS];
157};
158
159struct vm_stat_desc {
160	int		index;				/* in */
161	char		desc[128];			/* out */
162};
163
164struct vm_x2apic {
165	int			cpuid;
166	enum x2apic_state	state;
167};
168
169struct vm_gpa_pte {
170	uint64_t	gpa;				/* in */
171	uint64_t	pte[4];				/* out */
172	int		ptenum;
173};
174
175struct vm_hpet_cap {
176	uint32_t	capabilities;	/* lower 32 bits of HPET capabilities */
177};
178
179struct vm_suspend {
180	enum vm_suspend_how how;
181};
182
183struct vm_gla2gpa {
184	int		vcpuid;		/* inputs */
185	int 		prot;		/* PROT_READ or PROT_WRITE */
186	uint64_t	gla;
187	struct vm_guest_paging paging;
188	int		fault;		/* outputs */
189	uint64_t	gpa;
190};
191
192struct vm_activate_cpu {
193	int		vcpuid;
194};
195
196struct vm_cpuset {
197	int		which;
198	int		cpusetsize;
199	cpuset_t	*cpus;
200};
201#define	VM_ACTIVE_CPUS		0
202#define	VM_SUSPENDED_CPUS	1
203
204struct vm_intinfo {
205	int		vcpuid;
206	uint64_t	info1;
207	uint64_t	info2;
208};
209
210struct vm_rtc_time {
211	time_t		secs;
212};
213
214struct vm_rtc_data {
215	int		offset;
216	uint8_t		value;
217};
218
219enum {
220	/* general routines */
221	IOCNUM_ABIVERS = 0,
222	IOCNUM_RUN = 1,
223	IOCNUM_SET_CAPABILITY = 2,
224	IOCNUM_GET_CAPABILITY = 3,
225	IOCNUM_SUSPEND = 4,
226	IOCNUM_REINIT = 5,
227
228	/* memory apis */
229	IOCNUM_MAP_MEMORY = 10,			/* deprecated */
230	IOCNUM_GET_MEMORY_SEG = 11,		/* deprecated */
231	IOCNUM_GET_GPA_PMAP = 12,
232	IOCNUM_GLA2GPA = 13,
233	IOCNUM_ALLOC_MEMSEG = 14,
234	IOCNUM_GET_MEMSEG = 15,
235	IOCNUM_MMAP_MEMSEG = 16,
236	IOCNUM_MMAP_GETNEXT = 17,
237
238	/* register/state accessors */
239	IOCNUM_SET_REGISTER = 20,
240	IOCNUM_GET_REGISTER = 21,
241	IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
242	IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
243
244	/* interrupt injection */
245	IOCNUM_GET_INTINFO = 28,
246	IOCNUM_SET_INTINFO = 29,
247	IOCNUM_INJECT_EXCEPTION = 30,
248	IOCNUM_LAPIC_IRQ = 31,
249	IOCNUM_INJECT_NMI = 32,
250	IOCNUM_IOAPIC_ASSERT_IRQ = 33,
251	IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
252	IOCNUM_IOAPIC_PULSE_IRQ = 35,
253	IOCNUM_LAPIC_MSI = 36,
254	IOCNUM_LAPIC_LOCAL_IRQ = 37,
255	IOCNUM_IOAPIC_PINCOUNT = 38,
256	IOCNUM_RESTART_INSTRUCTION = 39,
257
258	/* PCI pass-thru */
259	IOCNUM_BIND_PPTDEV = 40,
260	IOCNUM_UNBIND_PPTDEV = 41,
261	IOCNUM_MAP_PPTDEV_MMIO = 42,
262	IOCNUM_PPTDEV_MSI = 43,
263	IOCNUM_PPTDEV_MSIX = 44,
264
265	/* statistics */
266	IOCNUM_VM_STATS = 50,
267	IOCNUM_VM_STAT_DESC = 51,
268
269	/* kernel device state */
270	IOCNUM_SET_X2APIC_STATE = 60,
271	IOCNUM_GET_X2APIC_STATE = 61,
272	IOCNUM_GET_HPET_CAPABILITIES = 62,
273
274	/* legacy interrupt injection */
275	IOCNUM_ISA_ASSERT_IRQ = 80,
276	IOCNUM_ISA_DEASSERT_IRQ = 81,
277	IOCNUM_ISA_PULSE_IRQ = 82,
278	IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
279
280	/* vm_cpuset */
281	IOCNUM_ACTIVATE_CPU = 90,
282	IOCNUM_GET_CPUSET = 91,
283
284	/* RTC */
285	IOCNUM_RTC_READ = 100,
286	IOCNUM_RTC_WRITE = 101,
287	IOCNUM_RTC_SETTIME = 102,
288	IOCNUM_RTC_GETTIME = 103,
289};
290
291#define	VM_RUN		\
292	_IOWR('v', IOCNUM_RUN, struct vm_run)
293#define	VM_SUSPEND	\
294	_IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
295#define	VM_REINIT	\
296	_IO('v', IOCNUM_REINIT)
297#define	VM_ALLOC_MEMSEG	\
298	_IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg)
299#define	VM_GET_MEMSEG	\
300	_IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg)
301#define	VM_MMAP_MEMSEG	\
302	_IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap)
303#define	VM_MMAP_GETNEXT	\
304	_IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap)
305#define	VM_SET_REGISTER \
306	_IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
307#define	VM_GET_REGISTER \
308	_IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
309#define	VM_SET_SEGMENT_DESCRIPTOR \
310	_IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
311#define	VM_GET_SEGMENT_DESCRIPTOR \
312	_IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
313#define	VM_INJECT_EXCEPTION	\
314	_IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
315#define	VM_LAPIC_IRQ 		\
316	_IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
317#define	VM_LAPIC_LOCAL_IRQ 	\
318	_IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
319#define	VM_LAPIC_MSI		\
320	_IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
321#define	VM_IOAPIC_ASSERT_IRQ	\
322	_IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
323#define	VM_IOAPIC_DEASSERT_IRQ	\
324	_IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
325#define	VM_IOAPIC_PULSE_IRQ	\
326	_IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
327#define	VM_IOAPIC_PINCOUNT	\
328	_IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
329#define	VM_ISA_ASSERT_IRQ	\
330	_IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
331#define	VM_ISA_DEASSERT_IRQ	\
332	_IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
333#define	VM_ISA_PULSE_IRQ	\
334	_IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
335#define	VM_ISA_SET_IRQ_TRIGGER	\
336	_IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
337#define	VM_SET_CAPABILITY \
338	_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
339#define	VM_GET_CAPABILITY \
340	_IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
341#define	VM_BIND_PPTDEV \
342	_IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
343#define	VM_UNBIND_PPTDEV \
344	_IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
345#define	VM_MAP_PPTDEV_MMIO \
346	_IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
347#define	VM_PPTDEV_MSI \
348	_IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
349#define	VM_PPTDEV_MSIX \
350	_IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
351#define VM_INJECT_NMI \
352	_IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
353#define	VM_STATS \
354	_IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
355#define	VM_STAT_DESC \
356	_IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
357#define	VM_SET_X2APIC_STATE \
358	_IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
359#define	VM_GET_X2APIC_STATE \
360	_IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
361#define	VM_GET_HPET_CAPABILITIES \
362	_IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
363#define	VM_GET_GPA_PMAP \
364	_IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
365#define	VM_GLA2GPA	\
366	_IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
367#define	VM_ACTIVATE_CPU	\
368	_IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu)
369#define	VM_GET_CPUS	\
370	_IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset)
371#define	VM_SET_INTINFO	\
372	_IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo)
373#define	VM_GET_INTINFO	\
374	_IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo)
375#define VM_RTC_WRITE \
376	_IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data)
377#define VM_RTC_READ \
378	_IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data)
379#define VM_RTC_SETTIME	\
380	_IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time)
381#define VM_RTC_GETTIME	\
382	_IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time)
383#define	VM_RESTART_INSTRUCTION \
384	_IOW('v', IOCNUM_RESTART_INSTRUCTION, int)
385#endif
386