vmm_dev.h revision 266633 
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/amd64/include/vmm_dev.h 266633 2014-05-24 23:12:30Z neel $
27 */
28
29#ifndef	_VMM_DEV_H_
30#define	_VMM_DEV_H_
31
32#ifdef _KERNEL
33void	vmmdev_init(void);
34int	vmmdev_cleanup(void);
35#endif
36
37struct vm_memory_segment {
38	vm_paddr_t	gpa;	/* in */
39	size_t		len;
40	int		wired;
41};
42
43struct vm_register {
44	int		cpuid;
45	int		regnum;		/* enum vm_reg_name */
46	uint64_t	regval;
47};
48
49struct vm_seg_desc {			/* data or code segment */
50	int		cpuid;
51	int		regnum;		/* enum vm_reg_name */
52	struct seg_desc desc;
53};
54
55struct vm_run {
56	int		cpuid;
57	uint64_t	rip;		/* start running here */
58	struct vm_exit	vm_exit;
59};
60
61struct vm_exception {
62	int		cpuid;
63	int		vector;
64	uint32_t	error_code;
65	int		error_code_valid;
66};
67
68struct vm_lapic_msi {
69	uint64_t	msg;
70	uint64_t	addr;
71};
72
73struct vm_lapic_irq {
74	int		cpuid;
75	int		vector;
76};
77
78struct vm_ioapic_irq {
79	int		irq;
80};
81
82struct vm_isa_irq {
83	int		atpic_irq;
84	int		ioapic_irq;
85};
86
87struct vm_isa_irq_trigger {
88	int		atpic_irq;
89	enum vm_intr_trigger trigger;
90};
91
92struct vm_capability {
93	int		cpuid;
94	enum vm_cap_type captype;
95	int		capval;
96	int		allcpus;
97};
98
99struct vm_pptdev {
100	int		bus;
101	int		slot;
102	int		func;
103};
104
105struct vm_pptdev_mmio {
106	int		bus;
107	int		slot;
108	int		func;
109	vm_paddr_t	gpa;
110	vm_paddr_t	hpa;
111	size_t		len;
112};
113
114struct vm_pptdev_msi {
115	int		vcpu;
116	int		bus;
117	int		slot;
118	int		func;
119	int		numvec;		/* 0 means disabled */
120	uint64_t	msg;
121	uint64_t	addr;
122};
123
124struct vm_pptdev_msix {
125	int		vcpu;
126	int		bus;
127	int		slot;
128	int		func;
129	int		idx;
130	uint64_t	msg;
131	uint32_t	vector_control;
132	uint64_t	addr;
133};
134
135struct vm_nmi {
136	int		cpuid;
137};
138
139#define	MAX_VM_STATS	64
140struct vm_stats {
141	int		cpuid;				/* in */
142	int		num_entries;			/* out */
143	struct timeval	tv;
144	uint64_t	statbuf[MAX_VM_STATS];
145};
146
147struct vm_stat_desc {
148	int		index;				/* in */
149	char		desc[128];			/* out */
150};
151
152struct vm_x2apic {
153	int			cpuid;
154	enum x2apic_state	state;
155};
156
157struct vm_gpa_pte {
158	uint64_t	gpa;				/* in */
159	uint64_t	pte[4];				/* out */
160	int		ptenum;
161};
162
163struct vm_hpet_cap {
164	uint32_t	capabilities;	/* lower 32 bits of HPET capabilities */
165};
166
167struct vm_suspend {
168	enum vm_suspend_how how;
169};
170
171struct vm_gla2gpa {
172	int		vcpuid;		/* inputs */
173	int 		prot;		/* PROT_READ or PROT_WRITE */
174	uint64_t	gla;
175	struct vm_guest_paging paging;
176	int		fault;		/* outputs */
177	uint64_t	gpa;
178};
179
180enum {
181	/* general routines */
182	IOCNUM_ABIVERS = 0,
183	IOCNUM_RUN = 1,
184	IOCNUM_SET_CAPABILITY = 2,
185	IOCNUM_GET_CAPABILITY = 3,
186	IOCNUM_SUSPEND = 4,
187
188	/* memory apis */
189	IOCNUM_MAP_MEMORY = 10,
190	IOCNUM_GET_MEMORY_SEG = 11,
191	IOCNUM_GET_GPA_PMAP = 12,
192	IOCNUM_GLA2GPA = 13,
193
194	/* register/state accessors */
195	IOCNUM_SET_REGISTER = 20,
196	IOCNUM_GET_REGISTER = 21,
197	IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
198	IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
199
200	/* interrupt injection */
201	IOCNUM_INJECT_EXCEPTION = 30,
202	IOCNUM_LAPIC_IRQ = 31,
203	IOCNUM_INJECT_NMI = 32,
204	IOCNUM_IOAPIC_ASSERT_IRQ = 33,
205	IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
206	IOCNUM_IOAPIC_PULSE_IRQ = 35,
207	IOCNUM_LAPIC_MSI = 36,
208	IOCNUM_LAPIC_LOCAL_IRQ = 37,
209	IOCNUM_IOAPIC_PINCOUNT = 38,
210
211	/* PCI pass-thru */
212	IOCNUM_BIND_PPTDEV = 40,
213	IOCNUM_UNBIND_PPTDEV = 41,
214	IOCNUM_MAP_PPTDEV_MMIO = 42,
215	IOCNUM_PPTDEV_MSI = 43,
216	IOCNUM_PPTDEV_MSIX = 44,
217
218	/* statistics */
219	IOCNUM_VM_STATS = 50,
220	IOCNUM_VM_STAT_DESC = 51,
221
222	/* kernel device state */
223	IOCNUM_SET_X2APIC_STATE = 60,
224	IOCNUM_GET_X2APIC_STATE = 61,
225	IOCNUM_GET_HPET_CAPABILITIES = 62,
226
227	/* legacy interrupt injection */
228	IOCNUM_ISA_ASSERT_IRQ = 80,
229	IOCNUM_ISA_DEASSERT_IRQ = 81,
230	IOCNUM_ISA_PULSE_IRQ = 82,
231	IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
232};
233
234#define	VM_RUN		\
235	_IOWR('v', IOCNUM_RUN, struct vm_run)
236#define	VM_SUSPEND	\
237	_IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
238#define	VM_MAP_MEMORY	\
239	_IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment)
240#define	VM_GET_MEMORY_SEG \
241	_IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment)
242#define	VM_SET_REGISTER \
243	_IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
244#define	VM_GET_REGISTER \
245	_IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
246#define	VM_SET_SEGMENT_DESCRIPTOR \
247	_IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
248#define	VM_GET_SEGMENT_DESCRIPTOR \
249	_IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
250#define	VM_INJECT_EXCEPTION	\
251	_IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
252#define	VM_LAPIC_IRQ 		\
253	_IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
254#define	VM_LAPIC_LOCAL_IRQ 	\
255	_IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
256#define	VM_LAPIC_MSI		\
257	_IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
258#define	VM_IOAPIC_ASSERT_IRQ	\
259	_IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
260#define	VM_IOAPIC_DEASSERT_IRQ	\
261	_IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
262#define	VM_IOAPIC_PULSE_IRQ	\
263	_IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
264#define	VM_IOAPIC_PINCOUNT	\
265	_IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
266#define	VM_ISA_ASSERT_IRQ	\
267	_IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
268#define	VM_ISA_DEASSERT_IRQ	\
269	_IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
270#define	VM_ISA_PULSE_IRQ	\
271	_IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
272#define	VM_ISA_SET_IRQ_TRIGGER	\
273	_IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
274#define	VM_SET_CAPABILITY \
275	_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
276#define	VM_GET_CAPABILITY \
277	_IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
278#define	VM_BIND_PPTDEV \
279	_IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
280#define	VM_UNBIND_PPTDEV \
281	_IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
282#define	VM_MAP_PPTDEV_MMIO \
283	_IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
284#define	VM_PPTDEV_MSI \
285	_IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
286#define	VM_PPTDEV_MSIX \
287	_IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
288#define VM_INJECT_NMI \
289	_IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
290#define	VM_STATS \
291	_IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
292#define	VM_STAT_DESC \
293	_IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
294#define	VM_SET_X2APIC_STATE \
295	_IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
296#define	VM_GET_X2APIC_STATE \
297	_IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
298#define	VM_GET_HPET_CAPABILITIES \
299	_IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
300#define	VM_GET_GPA_PMAP \
301	_IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
302#define	VM_GLA2GPA	\
303	_IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
304#endif
305