vmm_dev.h revision 266125
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/amd64/include/vmm_dev.h 266125 2014-05-15 14:16:55Z jhb $ 27 */ 28 29#ifndef _VMM_DEV_H_ 30#define _VMM_DEV_H_ 31 32#ifdef _KERNEL 33void vmmdev_init(void); 34int vmmdev_cleanup(void); 35#endif 36 37struct vm_memory_segment { 38 vm_paddr_t gpa; /* in */ 39 size_t len; 40 int wired; 41}; 42 43struct vm_register { 44 int cpuid; 45 int regnum; /* enum vm_reg_name */ 46 uint64_t regval; 47}; 48 49struct vm_seg_desc { /* data or code segment */ 50 int cpuid; 51 int regnum; /* enum vm_reg_name */ 52 struct seg_desc desc; 53}; 54 55struct vm_run { 56 int cpuid; 57 uint64_t rip; /* start running here */ 58 struct vm_exit vm_exit; 59}; 60 61struct vm_exception { 62 int cpuid; 63 int vector; 64 uint32_t error_code; 65 int error_code_valid; 66}; 67 68struct vm_lapic_msi { 69 uint64_t msg; 70 uint64_t addr; 71}; 72 73struct vm_lapic_irq { 74 int cpuid; 75 int vector; 76}; 77 78struct vm_ioapic_irq { 79 int irq; 80}; 81 82struct vm_isa_irq { 83 int atpic_irq; 84 int ioapic_irq; 85}; 86 87struct vm_isa_irq_trigger { 88 int atpic_irq; 89 enum vm_intr_trigger trigger; 90}; 91 92struct vm_capability { 93 int cpuid; 94 enum vm_cap_type captype; 95 int capval; 96 int allcpus; 97}; 98 99struct vm_pptdev { 100 int bus; 101 int slot; 102 int func; 103}; 104 105struct vm_pptdev_mmio { 106 int bus; 107 int slot; 108 int func; 109 vm_paddr_t gpa; 110 vm_paddr_t hpa; 111 size_t len; 112}; 113 114struct vm_pptdev_msi { 115 int vcpu; 116 int bus; 117 int slot; 118 int func; 119 int numvec; /* 0 means disabled */ 120 uint64_t msg; 121 uint64_t addr; 122}; 123 124struct vm_pptdev_msix { 125 int vcpu; 126 int bus; 127 int slot; 128 int func; 129 int idx; 130 uint64_t msg; 131 uint32_t vector_control; 132 uint64_t addr; 133}; 134 135struct vm_nmi { 136 int cpuid; 137}; 138 139#define MAX_VM_STATS 64 140struct vm_stats { 141 int cpuid; /* in */ 142 int num_entries; /* out */ 143 struct timeval tv; 144 uint64_t statbuf[MAX_VM_STATS]; 145}; 146 147struct vm_stat_desc { 148 int index; /* in */ 149 char desc[128]; /* out */ 150}; 151 152struct vm_x2apic { 153 int cpuid; 154 enum x2apic_state state; 155}; 156 157struct vm_gpa_pte { 158 uint64_t gpa; /* in */ 159 uint64_t pte[4]; /* out */ 160 int ptenum; 161}; 162 163struct vm_hpet_cap { 164 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 165}; 166 167struct vm_suspend { 168 enum vm_suspend_how how; 169}; 170 171enum { 172 /* general routines */ 173 IOCNUM_ABIVERS = 0, 174 IOCNUM_RUN = 1, 175 IOCNUM_SET_CAPABILITY = 2, 176 IOCNUM_GET_CAPABILITY = 3, 177 IOCNUM_SUSPEND = 4, 178 179 /* memory apis */ 180 IOCNUM_MAP_MEMORY = 10, 181 IOCNUM_GET_MEMORY_SEG = 11, 182 IOCNUM_GET_GPA_PMAP = 12, 183 184 /* register/state accessors */ 185 IOCNUM_SET_REGISTER = 20, 186 IOCNUM_GET_REGISTER = 21, 187 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 188 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 189 190 /* interrupt injection */ 191 IOCNUM_INJECT_EXCEPTION = 30, 192 IOCNUM_LAPIC_IRQ = 31, 193 IOCNUM_INJECT_NMI = 32, 194 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 195 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 196 IOCNUM_IOAPIC_PULSE_IRQ = 35, 197 IOCNUM_LAPIC_MSI = 36, 198 IOCNUM_LAPIC_LOCAL_IRQ = 37, 199 IOCNUM_IOAPIC_PINCOUNT = 38, 200 201 /* PCI pass-thru */ 202 IOCNUM_BIND_PPTDEV = 40, 203 IOCNUM_UNBIND_PPTDEV = 41, 204 IOCNUM_MAP_PPTDEV_MMIO = 42, 205 IOCNUM_PPTDEV_MSI = 43, 206 IOCNUM_PPTDEV_MSIX = 44, 207 208 /* statistics */ 209 IOCNUM_VM_STATS = 50, 210 IOCNUM_VM_STAT_DESC = 51, 211 212 /* kernel device state */ 213 IOCNUM_SET_X2APIC_STATE = 60, 214 IOCNUM_GET_X2APIC_STATE = 61, 215 IOCNUM_GET_HPET_CAPABILITIES = 62, 216 217 /* legacy interrupt injection */ 218 IOCNUM_ISA_ASSERT_IRQ = 80, 219 IOCNUM_ISA_DEASSERT_IRQ = 81, 220 IOCNUM_ISA_PULSE_IRQ = 82, 221 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 222}; 223 224#define VM_RUN \ 225 _IOWR('v', IOCNUM_RUN, struct vm_run) 226#define VM_SUSPEND \ 227 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 228#define VM_MAP_MEMORY \ 229 _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment) 230#define VM_GET_MEMORY_SEG \ 231 _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment) 232#define VM_SET_REGISTER \ 233 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 234#define VM_GET_REGISTER \ 235 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 236#define VM_SET_SEGMENT_DESCRIPTOR \ 237 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 238#define VM_GET_SEGMENT_DESCRIPTOR \ 239 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 240#define VM_INJECT_EXCEPTION \ 241 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 242#define VM_LAPIC_IRQ \ 243 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 244#define VM_LAPIC_LOCAL_IRQ \ 245 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 246#define VM_LAPIC_MSI \ 247 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 248#define VM_IOAPIC_ASSERT_IRQ \ 249 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 250#define VM_IOAPIC_DEASSERT_IRQ \ 251 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 252#define VM_IOAPIC_PULSE_IRQ \ 253 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 254#define VM_IOAPIC_PINCOUNT \ 255 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 256#define VM_ISA_ASSERT_IRQ \ 257 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 258#define VM_ISA_DEASSERT_IRQ \ 259 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 260#define VM_ISA_PULSE_IRQ \ 261 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 262#define VM_ISA_SET_IRQ_TRIGGER \ 263 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 264#define VM_SET_CAPABILITY \ 265 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 266#define VM_GET_CAPABILITY \ 267 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 268#define VM_BIND_PPTDEV \ 269 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 270#define VM_UNBIND_PPTDEV \ 271 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 272#define VM_MAP_PPTDEV_MMIO \ 273 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 274#define VM_PPTDEV_MSI \ 275 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 276#define VM_PPTDEV_MSIX \ 277 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 278#define VM_INJECT_NMI \ 279 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 280#define VM_STATS \ 281 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 282#define VM_STAT_DESC \ 283 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 284#define VM_SET_X2APIC_STATE \ 285 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 286#define VM_GET_X2APIC_STATE \ 287 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 288#define VM_GET_HPET_CAPABILITIES \ 289 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 290#define VM_GET_GPA_PMAP \ 291 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 292#endif 293