vmm_dev.h revision 263780
1345153Sdim/*- 2345153Sdim * Copyright (c) 2011 NetApp, Inc. 3345153Sdim * All rights reserved. 4345153Sdim * 5345153Sdim * Redistribution and use in source and binary forms, with or without 6345153Sdim * modification, are permitted provided that the following conditions 7345153Sdim * are met: 8353358Sdim * 1. Redistributions of source code must retain the above copyright 9353358Sdim * notice, this list of conditions and the following disclaimer. 10353358Sdim * 2. Redistributions in binary form must reproduce the above copyright 11345153Sdim * notice, this list of conditions and the following disclaimer in the 12345153Sdim * documentation and/or other materials provided with the distribution. 13345153Sdim * 14345153Sdim * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15345153Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16345153Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17345153Sdim * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18345153Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19345153Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20345153Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21345153Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22345153Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23345153Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24345153Sdim * SUCH DAMAGE. 25345153Sdim * 26345153Sdim * $FreeBSD: head/sys/amd64/include/vmm_dev.h 263780 2014-03-26 23:34:27Z neel $ 27345153Sdim */ 28345153Sdim 29345153Sdim#ifndef _VMM_DEV_H_ 30345153Sdim#define _VMM_DEV_H_ 31345153Sdim 32345153Sdim#ifdef _KERNEL 33345153Sdimvoid vmmdev_init(void); 34345153Sdimint vmmdev_cleanup(void); 35345153Sdim#endif 36345153Sdim 37345153Sdimstruct vm_memory_segment { 38345153Sdim vm_paddr_t gpa; /* in */ 39345153Sdim size_t len; 40345153Sdim int wired; 41345153Sdim}; 42345153Sdim 43345153Sdimstruct vm_register { 44345153Sdim int cpuid; 45345153Sdim int regnum; /* enum vm_reg_name */ 46345153Sdim uint64_t regval; 47345153Sdim}; 48345153Sdim 49345153Sdimstruct vm_seg_desc { /* data or code segment */ 50345153Sdim int cpuid; 51345153Sdim int regnum; /* enum vm_reg_name */ 52345153Sdim struct seg_desc desc; 53345153Sdim}; 54345153Sdim 55345153Sdimstruct vm_run { 56345153Sdim int cpuid; 57345153Sdim uint64_t rip; /* start running here */ 58345153Sdim struct vm_exit vm_exit; 59345153Sdim}; 60345153Sdim 61345153Sdimstruct vm_exception { 62345153Sdim int cpuid; 63345153Sdim int vector; 64345153Sdim uint32_t error_code; 65345153Sdim int error_code_valid; 66345153Sdim}; 67345153Sdim 68345153Sdimstruct vm_lapic_msi { 69345153Sdim uint64_t msg; 70345153Sdim uint64_t addr; 71345153Sdim}; 72345153Sdim 73345153Sdimstruct vm_lapic_irq { 74345153Sdim int cpuid; 75345153Sdim int vector; 76345153Sdim}; 77345153Sdim 78345153Sdimstruct vm_ioapic_irq { 79345153Sdim int irq; 80345153Sdim}; 81345153Sdim 82345153Sdimstruct vm_isa_irq { 83345153Sdim int atpic_irq; 84345153Sdim int ioapic_irq; 85345153Sdim}; 86345153Sdim 87345153Sdimstruct vm_capability { 88345153Sdim int cpuid; 89345153Sdim enum vm_cap_type captype; 90345153Sdim int capval; 91345153Sdim int allcpus; 92345153Sdim}; 93345153Sdim 94345153Sdimstruct vm_pptdev { 95345153Sdim int bus; 96345153Sdim int slot; 97345153Sdim int func; 98345153Sdim}; 99345153Sdim 100345153Sdimstruct vm_pptdev_mmio { 101345153Sdim int bus; 102345153Sdim int slot; 103345153Sdim int func; 104345153Sdim vm_paddr_t gpa; 105345153Sdim vm_paddr_t hpa; 106345153Sdim size_t len; 107345153Sdim}; 108345153Sdim 109345153Sdimstruct vm_pptdev_msi { 110345153Sdim int vcpu; 111345153Sdim int bus; 112345153Sdim int slot; 113345153Sdim int func; 114345153Sdim int numvec; /* 0 means disabled */ 115345153Sdim uint64_t msg; 116345153Sdim uint64_t addr; 117345153Sdim}; 118345153Sdim 119345153Sdimstruct vm_pptdev_msix { 120345153Sdim int vcpu; 121345153Sdim int bus; 122345153Sdim int slot; 123345153Sdim int func; 124345153Sdim int idx; 125345153Sdim uint64_t msg; 126345153Sdim uint32_t vector_control; 127345153Sdim uint64_t addr; 128345153Sdim}; 129345153Sdim 130345153Sdimstruct vm_nmi { 131345153Sdim int cpuid; 132345153Sdim}; 133345153Sdim 134345153Sdim#define MAX_VM_STATS 64 135345153Sdimstruct vm_stats { 136345153Sdim int cpuid; /* in */ 137345153Sdim int num_entries; /* out */ 138345153Sdim struct timeval tv; 139345153Sdim uint64_t statbuf[MAX_VM_STATS]; 140345153Sdim}; 141345153Sdim 142345153Sdimstruct vm_stat_desc { 143345153Sdim int index; /* in */ 144345153Sdim char desc[128]; /* out */ 145345153Sdim}; 146345153Sdim 147345153Sdimstruct vm_x2apic { 148345153Sdim int cpuid; 149345153Sdim enum x2apic_state state; 150345153Sdim}; 151345153Sdim 152345153Sdimstruct vm_gpa_pte { 153345153Sdim uint64_t gpa; /* in */ 154345153Sdim uint64_t pte[4]; /* out */ 155345153Sdim int ptenum; 156345153Sdim}; 157345153Sdim 158345153Sdimstruct vm_hpet_cap { 159345153Sdim uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 160345153Sdim}; 161345153Sdim 162345153Sdimenum { 163345153Sdim /* general routines */ 164345153Sdim IOCNUM_ABIVERS = 0, 165345153Sdim IOCNUM_RUN = 1, 166345153Sdim IOCNUM_SET_CAPABILITY = 2, 167345153Sdim IOCNUM_GET_CAPABILITY = 3, 168345153Sdim IOCNUM_SUSPEND = 4, 169345153Sdim 170345153Sdim /* memory apis */ 171345153Sdim IOCNUM_MAP_MEMORY = 10, 172345153Sdim IOCNUM_GET_MEMORY_SEG = 11, 173345153Sdim IOCNUM_GET_GPA_PMAP = 12, 174345153Sdim 175345153Sdim /* register/state accessors */ 176345153Sdim IOCNUM_SET_REGISTER = 20, 177345153Sdim IOCNUM_GET_REGISTER = 21, 178345153Sdim IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 179345153Sdim IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 180345153Sdim 181345153Sdim /* interrupt injection */ 182345153Sdim IOCNUM_INJECT_EXCEPTION = 30, 183345153Sdim IOCNUM_LAPIC_IRQ = 31, 184345153Sdim IOCNUM_INJECT_NMI = 32, 185345153Sdim IOCNUM_IOAPIC_ASSERT_IRQ = 33, 186345153Sdim IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 187345153Sdim IOCNUM_IOAPIC_PULSE_IRQ = 35, 188345153Sdim IOCNUM_LAPIC_MSI = 36, 189345153Sdim IOCNUM_LAPIC_LOCAL_IRQ = 37, 190345153Sdim IOCNUM_IOAPIC_PINCOUNT = 38, 191345153Sdim 192345153Sdim /* PCI pass-thru */ 193345153Sdim IOCNUM_BIND_PPTDEV = 40, 194345153Sdim IOCNUM_UNBIND_PPTDEV = 41, 195345153Sdim IOCNUM_MAP_PPTDEV_MMIO = 42, 196345153Sdim IOCNUM_PPTDEV_MSI = 43, 197345153Sdim IOCNUM_PPTDEV_MSIX = 44, 198345153Sdim 199345153Sdim /* statistics */ 200345153Sdim IOCNUM_VM_STATS = 50, 201345153Sdim IOCNUM_VM_STAT_DESC = 51, 202345153Sdim 203345153Sdim /* kernel device state */ 204345153Sdim IOCNUM_SET_X2APIC_STATE = 60, 205345153Sdim IOCNUM_GET_X2APIC_STATE = 61, 206345153Sdim IOCNUM_GET_HPET_CAPABILITIES = 62, 207345153Sdim 208345153Sdim /* legacy interrupt injection */ 209345153Sdim IOCNUM_ISA_ASSERT_IRQ = 80, 210345153Sdim IOCNUM_ISA_DEASSERT_IRQ = 81, 211345153Sdim IOCNUM_ISA_PULSE_IRQ = 82, 212345153Sdim}; 213345153Sdim 214345153Sdim#define VM_RUN \ 215345153Sdim _IOWR('v', IOCNUM_RUN, struct vm_run) 216345153Sdim#define VM_SUSPEND \ 217345153Sdim _IO('v', IOCNUM_SUSPEND) 218345153Sdim#define VM_MAP_MEMORY \ 219345153Sdim _IOWR('v', IOCNUM_MAP_MEMORY, struct vm_memory_segment) 220345153Sdim#define VM_GET_MEMORY_SEG \ 221345153Sdim _IOWR('v', IOCNUM_GET_MEMORY_SEG, struct vm_memory_segment) 222353358Sdim#define VM_SET_REGISTER \ 223345153Sdim _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 224345153Sdim#define VM_GET_REGISTER \ 225345153Sdim _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 226345153Sdim#define VM_SET_SEGMENT_DESCRIPTOR \ 227345153Sdim _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 228345153Sdim#define VM_GET_SEGMENT_DESCRIPTOR \ 229345153Sdim _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 230345153Sdim#define VM_INJECT_EXCEPTION \ 231345153Sdim _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 232345153Sdim#define VM_LAPIC_IRQ \ 233345153Sdim _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 234345153Sdim#define VM_LAPIC_LOCAL_IRQ \ 235345153Sdim _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 236345153Sdim#define VM_LAPIC_MSI \ 237345153Sdim _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 238345153Sdim#define VM_IOAPIC_ASSERT_IRQ \ 239345153Sdim _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 240345153Sdim#define VM_IOAPIC_DEASSERT_IRQ \ 241345153Sdim _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 242345153Sdim#define VM_IOAPIC_PULSE_IRQ \ 243345153Sdim _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 244345153Sdim#define VM_IOAPIC_PINCOUNT \ 245345153Sdim _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 246345153Sdim#define VM_ISA_ASSERT_IRQ \ 247345153Sdim _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 248345153Sdim#define VM_ISA_DEASSERT_IRQ \ 249345153Sdim _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 250345153Sdim#define VM_ISA_PULSE_IRQ \ 251345153Sdim _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 252345153Sdim#define VM_SET_CAPABILITY \ 253345153Sdim _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 254345153Sdim#define VM_GET_CAPABILITY \ 255345153Sdim _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 256345153Sdim#define VM_BIND_PPTDEV \ 257345153Sdim _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 258345153Sdim#define VM_UNBIND_PPTDEV \ 259345153Sdim _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 260345153Sdim#define VM_MAP_PPTDEV_MMIO \ 261345153Sdim _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 262345153Sdim#define VM_PPTDEV_MSI \ 263345153Sdim _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 264345153Sdim#define VM_PPTDEV_MSIX \ 265345153Sdim _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 266345153Sdim#define VM_INJECT_NMI \ 267345153Sdim _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 268345153Sdim#define VM_STATS \ 269345153Sdim _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 270345153Sdim#define VM_STAT_DESC \ 271345153Sdim _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 272345153Sdim#define VM_SET_X2APIC_STATE \ 273345153Sdim _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 274345153Sdim#define VM_GET_X2APIC_STATE \ 275345153Sdim _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 276345153Sdim#define VM_GET_HPET_CAPABILITIES \ 277345153Sdim _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 278345153Sdim#define VM_GET_GPA_PMAP \ 279345153Sdim _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 280345153Sdim#endif 281345153Sdim