fpu.h revision 5 
1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *	This product includes software developed by the University of
19 *	California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 *    may be used to endorse or promote products derived from this software
22 *    without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 *	@(#)npx.h	5.3 (Berkeley) 1/18/91
37 *
38 * PATCHES MAGIC                LEVEL   PATCH THAT GOT US HERE
39 * --------------------         -----   ----------------------
40 * CURRENT PATCH LEVEL:         1       00154
41 * --------------------         -----   ----------------------
42 *
43 * 20 Apr 93	Bruce Evans		New npx-0.5 code
44 *
45 */
46
47/*
48 * 287/387 NPX Coprocessor Data Structures and Constants
49 * W. Jolitz 1/90
50 */
51
52#ifndef	___NPX87___
53#define	___NPX87___
54
55/* Environment information of floating point unit */
56struct	env87 {
57	long	en_cw;		/* control word (16bits) */
58	long	en_sw;		/* status word (16bits) */
59	long	en_tw;		/* tag word (16bits) */
60	long	en_fip;		/* floating point instruction pointer */
61	u_short	en_fcs;		/* floating code segment selector */
62	u_short	en_opcode;	/* opcode last executed (11 bits ) */
63	long	en_foo;		/* floating operand offset */
64	long	en_fos;		/* floating operand segment selector */
65};
66
67/* Contents of each floating point accumulator */
68struct	fpacc87 {
69#ifdef dontdef /* too unportable */
70	u_long	fp_mantlo;	/* mantissa low (31:0) */
71	u_long	fp_manthi;	/* mantissa high (63:32) */
72	int	fp_exp:15;	/* exponent */
73	int	fp_sgn:1;	/* mantissa sign */
74#else
75	u_char	fp_bytes[10];
76#endif
77};
78
79/* Floating point context */
80struct	save87 {
81	struct	env87 sv_env;		/* floating point control/status */
82	struct	fpacc87	sv_ac[8];	/* accumulator contents, 0-7 */
83#ifndef dontdef
84	u_long	sv_ex_sw;	/* status word for last exception (was pad) */
85	u_long	sv_ex_tw;	/* tag word for last exception (was pad) */
86	u_char	sv_pad[8 * 2 - 2 * 4];	/* bogus historical padding */
87#endif
88};
89
90/* Cyrix EMC memory - mapped coprocessor context switch information */
91struct	emcsts {
92	long	em_msw;		/* memory mapped status register when swtched */
93	long	em_tar;		/* memory mapped temp A register when swtched */
94	long	em_dl;		/* memory mapped D low register when swtched */
95};
96
97/* Intel prefers long real (53 bit) precision */
98#define	__iBCS_NPXCW__		0x262
99/* wfj prefers temporary real (64 bit) precision */
100#define	__386BSD_NPXCW__	0x362
101/*
102 * bde prefers 53 bit precision and all exceptions masked.
103 *
104 * The standard control word from finit is 0x37F, giving:
105 *
106 *	round to nearest
107 *	64-bit precision
108 *	all exceptions masked.
109 *
110 * Now I want:
111 *
112 *	affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
113 *	53-bit precision (2 in bitfield 3<<8)
114 *	overflow exception unmasked (0 in bitfield 1<<3)
115 *	zero divide exception unmasked (0 in bitfield 1<<2)
116 *	invalid-operand exception unmasked (0 in bitfield 1<<0).
117 *
118 * 64-bit precision often gives bad results with high level languages
119 * because it makes the results of calculations depend on whether
120 * intermediate values are stored in memory or in FPU registers.
121 *
122 * The "Intel" and wfj control words have:
123 *
124 *	underflow exception unmasked (0 in bitfield 1<<4)
125 *
126 * but that causes an unexpected exception in the test program 'paranoia'
127 * and makes denormals useless (DBL_MIN / 2 underflows).  It doesn't make
128 * a lot of sense to trap underflow without trapping denormals.
129 *
130 * Later I will want the IEEE default of all exceptions masked.  See the
131 * 0.0 math manpage for why this is better.  The 0.1 math manpage is empty.
132 */
133#define	__BDE_NPXCW__		0x1272
134#define	__BETTER_BDE_NPXCW__	0x127f
135
136#ifdef __BROKEN_NPXCW__
137#ifdef __386BSD__
138#define	__INITIAL_NPXCW__	__386BSD_NPXCW__
139#else
140#define	__INITIAL_NPXCW__	__iBCS_NPXCW__
141#endif
142#else
143#define	__INITIAL_NPXCW__	__BDE_NPXCW__
144#endif
145
146#endif	___NPX87___
147