fpu.h revision 1432
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)npx.h 5.3 (Berkeley) 1/18/91 37 * $Id: npx.h,v 1.2 1993/10/16 14:39:22 rgrimes Exp $ 38 */ 39 40/* 41 * 287/387 NPX Coprocessor Data Structures and Constants 42 * W. Jolitz 1/90 43 */ 44 45#ifndef ___NPX87___ 46#define ___NPX87___ 47 48/* Environment information of floating point unit */ 49struct env87 { 50 long en_cw; /* control word (16bits) */ 51 long en_sw; /* status word (16bits) */ 52 long en_tw; /* tag word (16bits) */ 53 long en_fip; /* floating point instruction pointer */ 54 u_short en_fcs; /* floating code segment selector */ 55 u_short en_opcode; /* opcode last executed (11 bits ) */ 56 long en_foo; /* floating operand offset */ 57 long en_fos; /* floating operand segment selector */ 58}; 59 60/* Contents of each floating point accumulator */ 61struct fpacc87 { 62#ifdef dontdef /* too unportable */ 63 u_long fp_mantlo; /* mantissa low (31:0) */ 64 u_long fp_manthi; /* mantissa high (63:32) */ 65 int fp_exp:15; /* exponent */ 66 int fp_sgn:1; /* mantissa sign */ 67#else 68 u_char fp_bytes[10]; 69#endif 70}; 71 72/* Floating point context */ 73struct save87 { 74 struct env87 sv_env; /* floating point control/status */ 75 struct fpacc87 sv_ac[8]; /* accumulator contents, 0-7 */ 76 u_long sv_ex_sw; /* status word for last exception (was pad) */ 77 u_long sv_ex_tw; /* tag word for last exception (was pad) */ 78#ifdef GPL_MATH_EMULATE 79 u_char sv_pad[60]; 80#else 81 u_char sv_pad[8 * 2 - 2 * 4]; /* bogus historical padding */ 82#endif /* GPL_MATH_EMULATE */ 83}; 84 85/* Cyrix EMC memory - mapped coprocessor context switch information */ 86struct emcsts { 87 long em_msw; /* memory mapped status register when swtched */ 88 long em_tar; /* memory mapped temp A register when swtched */ 89 long em_dl; /* memory mapped D low register when swtched */ 90}; 91 92/* Intel prefers long real (53 bit) precision */ 93#define __iBCS_NPXCW__ 0x262 94/* wfj prefers temporary real (64 bit) precision */ 95#define __386BSD_NPXCW__ 0x362 96/* 97 * bde prefers 53 bit precision and all exceptions masked. 98 * 99 * The standard control word from finit is 0x37F, giving: 100 * 101 * round to nearest 102 * 64-bit precision 103 * all exceptions masked. 104 * 105 * Now I want: 106 * 107 * affine mode for 287's (if they work at all) (1 in bitfield 1<<12) 108 * 53-bit precision (2 in bitfield 3<<8) 109 * overflow exception unmasked (0 in bitfield 1<<3) 110 * zero divide exception unmasked (0 in bitfield 1<<2) 111 * invalid-operand exception unmasked (0 in bitfield 1<<0). 112 * 113 * 64-bit precision often gives bad results with high level languages 114 * because it makes the results of calculations depend on whether 115 * intermediate values are stored in memory or in FPU registers. 116 * 117 * The "Intel" and wfj control words have: 118 * 119 * underflow exception unmasked (0 in bitfield 1<<4) 120 * 121 * but that causes an unexpected exception in the test program 'paranoia' 122 * and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make 123 * a lot of sense to trap underflow without trapping denormals. 124 * 125 * Later I will want the IEEE default of all exceptions masked. See the 126 * 0.0 math manpage for why this is better. The 0.1 math manpage is empty. 127 */ 128#define __BDE_NPXCW__ 0x1272 129#define __BETTER_BDE_NPXCW__ 0x127f 130 131#ifdef __BROKEN_NPXCW__ 132#ifdef __386BSD__ 133#define __INITIAL_NPXCW__ __386BSD_NPXCW__ 134#else 135#define __INITIAL_NPXCW__ __iBCS_NPXCW__ 136#endif 137#else 138#define __INITIAL_NPXCW__ __BDE_NPXCW__ 139#endif 140 141#endif ___NPX87___ 142