mp_machdep.c revision 38422
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.77 1998/08/16 00:41:40 bde Exp $ 26 */ 27 28#include "opt_smp.h" 29#include "opt_vm86.h" 30#include "opt_cpu.h" 31#include "opt_user_ldt.h" 32 33#ifdef SMP 34#include <machine/smptests.h> 35#else 36#error 37#endif 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/kernel.h> 42#include <sys/proc.h> 43#include <sys/sysctl.h> 44#ifdef BETTER_CLOCK 45#include <sys/dkstat.h> 46#endif 47 48#include <vm/vm.h> 49#include <vm/vm_param.h> 50#include <vm/pmap.h> 51#include <vm/vm_kern.h> 52#include <vm/vm_extern.h> 53#ifdef BETTER_CLOCK 54#include <sys/lock.h> 55#include <vm/vm_map.h> 56#include <sys/user.h> 57#ifdef GPROF 58#include <sys/gmon.h> 59#endif 60#endif 61 62#include <machine/smp.h> 63#include <machine/apic.h> 64#include <machine/mpapic.h> 65#include <machine/segments.h> 66#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 67#include <machine/tss.h> 68#include <machine/specialreg.h> 69#include <machine/cputypes.h> 70#include <machine/globaldata.h> 71 72#include <i386/i386/cons.h> /* cngetc() */ 73 74#if defined(APIC_IO) 75#include <machine/md_var.h> /* setidt() */ 76#include <i386/isa/icu.h> /* IPIs */ 77#include <i386/isa/intr_machdep.h> /* IPIs */ 78#endif /* APIC_IO */ 79 80#if defined(TEST_DEFAULT_CONFIG) 81#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 82#else 83#define MPFPS_MPFB1 mpfps->mpfb1 84#endif /* TEST_DEFAULT_CONFIG */ 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#define BIOS_BASE (0xf0000) 91#define BIOS_SIZE (0x10000) 92#define BIOS_COUNT (BIOS_SIZE/4) 93 94#define CMOS_REG (0x70) 95#define CMOS_DATA (0x71) 96#define BIOS_RESET (0x0f) 97#define BIOS_WARM (0x0a) 98 99#define PROCENTRY_FLAG_EN 0x01 100#define PROCENTRY_FLAG_BP 0x02 101#define IOAPICENTRY_FLAG_EN 0x01 102 103 104/* MP Floating Pointer Structure */ 105typedef struct MPFPS { 106 char signature[4]; 107 void *pap; 108 u_char length; 109 u_char spec_rev; 110 u_char checksum; 111 u_char mpfb1; 112 u_char mpfb2; 113 u_char mpfb3; 114 u_char mpfb4; 115 u_char mpfb5; 116} *mpfps_t; 117 118/* MP Configuration Table Header */ 119typedef struct MPCTH { 120 char signature[4]; 121 u_short base_table_length; 122 u_char spec_rev; 123 u_char checksum; 124 u_char oem_id[8]; 125 u_char product_id[12]; 126 void *oem_table_pointer; 127 u_short oem_table_size; 128 u_short entry_count; 129 void *apic_address; 130 u_short extended_table_length; 131 u_char extended_table_checksum; 132 u_char reserved; 133} *mpcth_t; 134 135 136typedef struct PROCENTRY { 137 u_char type; 138 u_char apic_id; 139 u_char apic_version; 140 u_char cpu_flags; 141 u_long cpu_signature; 142 u_long feature_flags; 143 u_long reserved1; 144 u_long reserved2; 145} *proc_entry_ptr; 146 147typedef struct BUSENTRY { 148 u_char type; 149 u_char bus_id; 150 char bus_type[6]; 151} *bus_entry_ptr; 152 153typedef struct IOAPICENTRY { 154 u_char type; 155 u_char apic_id; 156 u_char apic_version; 157 u_char apic_flags; 158 void *apic_address; 159} *io_apic_entry_ptr; 160 161typedef struct INTENTRY { 162 u_char type; 163 u_char int_type; 164 u_short int_flags; 165 u_char src_bus_id; 166 u_char src_bus_irq; 167 u_char dst_apic_id; 168 u_char dst_apic_int; 169} *int_entry_ptr; 170 171/* descriptions of MP basetable entries */ 172typedef struct BASETABLE_ENTRY { 173 u_char type; 174 u_char length; 175 char name[16]; 176} basetable_entry; 177 178/* 179 * this code MUST be enabled here and in mpboot.s. 180 * it follows the very early stages of AP boot by placing values in CMOS ram. 181 * it NORMALLY will never be needed and thus the primitive method for enabling. 182 * 183#define CHECK_POINTS 184 */ 185 186#if defined(CHECK_POINTS) 187#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 188#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 189 190#define CHECK_INIT(D); \ 191 CHECK_WRITE(0x34, (D)); \ 192 CHECK_WRITE(0x35, (D)); \ 193 CHECK_WRITE(0x36, (D)); \ 194 CHECK_WRITE(0x37, (D)); \ 195 CHECK_WRITE(0x38, (D)); \ 196 CHECK_WRITE(0x39, (D)); 197 198#define CHECK_PRINT(S); \ 199 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 200 (S), \ 201 CHECK_READ(0x34), \ 202 CHECK_READ(0x35), \ 203 CHECK_READ(0x36), \ 204 CHECK_READ(0x37), \ 205 CHECK_READ(0x38), \ 206 CHECK_READ(0x39)); 207 208#else /* CHECK_POINTS */ 209 210#define CHECK_INIT(D) 211#define CHECK_PRINT(S) 212 213#endif /* CHECK_POINTS */ 214 215/* 216 * Values to send to the POST hardware. 217 */ 218#define MP_BOOTADDRESS_POST 0x10 219#define MP_PROBE_POST 0x11 220#define MPTABLE_PASS1_POST 0x12 221 222#define MP_START_POST 0x13 223#define MP_ENABLE_POST 0x14 224#define MPTABLE_PASS2_POST 0x15 225 226#define START_ALL_APS_POST 0x16 227#define INSTALL_AP_TRAMP_POST 0x17 228#define START_AP_POST 0x18 229 230#define MP_ANNOUNCE_POST 0x19 231 232 233/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 234int current_postcode; 235 236/** XXX FIXME: what system files declare these??? */ 237extern struct region_descriptor r_gdt, r_idt; 238 239int bsp_apic_ready = 0; /* flags useability of BSP apic */ 240int mp_ncpus; /* # of CPUs, including BSP */ 241int mp_naps; /* # of Applications processors */ 242int mp_nbusses; /* # of busses */ 243int mp_napics; /* # of IO APICs */ 244int boot_cpu_id; /* designated BSP */ 245vm_offset_t cpu_apic_address; 246vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 247extern int nkpt; 248 249u_int32_t cpu_apic_versions[NCPU]; 250u_int32_t io_apic_versions[NAPIC]; 251 252#ifdef APIC_INTR_DIAGNOSTIC 253int apic_itrace_enter[32]; 254int apic_itrace_tryisrlock[32]; 255int apic_itrace_gotisrlock[32]; 256int apic_itrace_active[32]; 257int apic_itrace_masked[32]; 258int apic_itrace_noisrlock[32]; 259int apic_itrace_masked2[32]; 260int apic_itrace_unmask[32]; 261int apic_itrace_noforward[32]; 262int apic_itrace_leave[32]; 263int apic_itrace_enter2[32]; 264int apic_itrace_doreti[32]; 265int apic_itrace_splz[32]; 266int apic_itrace_eoi[32]; 267#ifdef APIC_INTR_DIAGNOSTIC_IRQ 268unsigned short apic_itrace_debugbuffer[32768]; 269int apic_itrace_debugbuffer_idx; 270struct simplelock apic_itrace_debuglock; 271#endif 272#endif 273 274#ifdef APIC_INTR_REORDER 275struct { 276 volatile int *location; 277 int bit; 278} apic_isrbit_location[32]; 279#endif 280 281/* 282 * APIC ID logical/physical mapping structures. 283 * We oversize these to simplify boot-time config. 284 */ 285int cpu_num_to_apic_id[NAPICID]; 286int io_num_to_apic_id[NAPICID]; 287int apic_id_to_logical[NAPICID]; 288 289 290/* Bitmap of all available CPUs */ 291u_int all_cpus; 292 293/* AP uses this PTD during bootstrap. Do not staticize. */ 294pd_entry_t *bootPTD; 295 296/* Hotwire a 0->4MB V==P mapping */ 297extern pt_entry_t *KPTphys; 298 299/* Virtual address of per-cpu common_tss */ 300extern struct i386tss common_tss; 301#ifdef VM86 302extern struct segment_descriptor common_tssd; 303extern u_int private_tss; /* flag indicating private tss */ 304extern u_int my_tr; 305#endif /* VM86 */ 306 307/* IdlePTD per cpu */ 308pd_entry_t *IdlePTDS[NCPU]; 309 310/* "my" private page table page, for BSP init */ 311extern pt_entry_t SMP_prvpt[]; 312 313/* Private page pointer to curcpu's PTD, used during BSP init */ 314extern pd_entry_t *my_idlePTD; 315 316struct pcb stoppcbs[NCPU]; 317 318static int smp_started; /* has the system started? */ 319 320/* 321 * Local data and functions. 322 */ 323 324static int mp_capable; 325static u_int boot_address; 326static u_int base_memory; 327 328static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 329static mpfps_t mpfps; 330static int search_for_sig(u_int32_t target, int count); 331static void mp_enable(u_int boot_addr); 332 333static int mptable_pass1(void); 334static int mptable_pass2(void); 335static void default_mp_table(int type); 336static void fix_mp_table(void); 337static void init_locks(void); 338static int start_all_aps(u_int boot_addr); 339static void install_ap_tramp(u_int boot_addr); 340static int start_ap(int logicalCpu, u_int boot_addr); 341 342/* 343 * Calculate usable address in base memory for AP trampoline code. 344 */ 345u_int 346mp_bootaddress(u_int basemem) 347{ 348 POSTCODE(MP_BOOTADDRESS_POST); 349 350 base_memory = basemem * 1024; /* convert to bytes */ 351 352 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 353 if ((base_memory - boot_address) < bootMP_size) 354 boot_address -= 4096; /* not enough, lower by 4k */ 355 356 return boot_address; 357} 358 359 360/* 361 * Look for an Intel MP spec table (ie, SMP capable hardware). 362 */ 363int 364mp_probe(void) 365{ 366 int x; 367 u_long segment; 368 u_int32_t target; 369 370 POSTCODE(MP_PROBE_POST); 371 372 /* see if EBDA exists */ 373 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 374 /* search first 1K of EBDA */ 375 target = (u_int32_t) (segment << 4); 376 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 377 goto found; 378 } else { 379 /* last 1K of base memory, effective 'top of base' passed in */ 380 target = (u_int32_t) (base_memory - 0x400); 381 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 382 goto found; 383 } 384 385 /* search the BIOS */ 386 target = (u_int32_t) BIOS_BASE; 387 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 388 goto found; 389 390 /* nothing found */ 391 mpfps = (mpfps_t)0; 392 mp_capable = 0; 393 return 0; 394 395found: 396 /* calculate needed resources */ 397 mpfps = (mpfps_t)x; 398 if (mptable_pass1()) 399 panic("you must reconfigure your kernel"); 400 401 /* flag fact that we are running multiple processors */ 402 mp_capable = 1; 403 return 1; 404} 405 406 407/* 408 * Startup the SMP processors. 409 */ 410void 411mp_start(void) 412{ 413 POSTCODE(MP_START_POST); 414 415 /* look for MP capable motherboard */ 416 if (mp_capable) 417 mp_enable(boot_address); 418 else 419 panic("MP hardware not found!"); 420} 421 422 423/* 424 * Print various information about the SMP system hardware and setup. 425 */ 426void 427mp_announce(void) 428{ 429 int x; 430 431 POSTCODE(MP_ANNOUNCE_POST); 432 433 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 434 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 435 printf(", version: 0x%08x", cpu_apic_versions[0]); 436 printf(", at 0x%08x\n", cpu_apic_address); 437 for (x = 1; x <= mp_naps; ++x) { 438 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 439 printf(", version: 0x%08x", cpu_apic_versions[x]); 440 printf(", at 0x%08x\n", cpu_apic_address); 441 } 442 443#if defined(APIC_IO) 444 for (x = 0; x < mp_napics; ++x) { 445 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 446 printf(", version: 0x%08x", io_apic_versions[x]); 447 printf(", at 0x%08x\n", io_apic_address[x]); 448 } 449#else 450 printf(" Warning: APIC I/O disabled\n"); 451#endif /* APIC_IO */ 452} 453 454/* 455 * AP cpu's call this to sync up protected mode. 456 */ 457void 458init_secondary(void) 459{ 460 int gsel_tss; 461#ifndef VM86 462 u_int my_tr; 463#endif 464 465 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 466 r_gdt.rd_base = (int) gdt; 467 lgdt(&r_gdt); /* does magic intra-segment return */ 468 lidt(&r_idt); 469 lldt(_default_ldt); 470#ifdef USER_LDT 471 currentldt = _default_ldt; 472#endif 473 474 my_tr = NGDT + cpuid; 475 gsel_tss = GSEL(my_tr, SEL_KPL); 476 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 477 common_tss.tss_esp0 = 0; /* not used until after switch */ 478 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 479 common_tss.tss_ioopt = (sizeof common_tss) << 16; 480#ifdef VM86 481 common_tssd = gdt[my_tr].sd; 482 private_tss = 0; 483#endif /* VM86 */ 484 ltr(gsel_tss); 485 486 load_cr0(0x8005003b); /* XXX! */ 487 488 PTD[0] = 0; 489 pmap_set_opt((unsigned *)PTD); 490 491 putmtrr(); 492 pmap_setvidram(); 493 494 invltlb(); 495} 496 497 498#if defined(APIC_IO) 499/* 500 * Final configuration of the BSP's local APIC: 501 * - disable 'pic mode'. 502 * - disable 'virtual wire mode'. 503 * - enable NMI. 504 */ 505void 506bsp_apic_configure(void) 507{ 508 u_char byte; 509 u_int32_t temp; 510 511 /* leave 'pic mode' if necessary */ 512 if (picmode) { 513 outb(0x22, 0x70); /* select IMCR */ 514 byte = inb(0x23); /* current contents */ 515 byte |= 0x01; /* mask external INTR */ 516 outb(0x23, byte); /* disconnect 8259s/NMI */ 517 } 518 519 /* mask lint0 (the 8259 'virtual wire' connection) */ 520 temp = lapic.lvt_lint0; 521 temp |= APIC_LVT_M; /* set the mask */ 522 lapic.lvt_lint0 = temp; 523 524 /* setup lint1 to handle NMI */ 525 temp = lapic.lvt_lint1; 526 temp &= ~APIC_LVT_M; /* clear the mask */ 527 lapic.lvt_lint1 = temp; 528 529 if (bootverbose) 530 apic_dump("bsp_apic_configure()"); 531} 532#endif /* APIC_IO */ 533 534 535/******************************************************************* 536 * local functions and data 537 */ 538 539/* 540 * start the SMP system 541 */ 542static void 543mp_enable(u_int boot_addr) 544{ 545 int x; 546#if defined(APIC_IO) 547 int apic; 548 u_int ux; 549#endif /* APIC_IO */ 550 551 getmtrr(); 552 pmap_setvidram(); 553 554 POSTCODE(MP_ENABLE_POST); 555 556 /* turn on 4MB of V == P addressing so we can get to MP table */ 557 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 558 invltlb(); 559 560 /* examine the MP table for needed info, uses physical addresses */ 561 x = mptable_pass2(); 562 563 *(int *)PTD = 0; 564 invltlb(); 565 566 /* can't process default configs till the CPU APIC is pmapped */ 567 if (x) 568 default_mp_table(x); 569 570 /* post scan cleanup */ 571 fix_mp_table(); 572 573#if defined(APIC_IO) 574 575 /* fill the LOGICAL io_apic_versions table */ 576 for (apic = 0; apic < mp_napics; ++apic) { 577 ux = io_apic_read(apic, IOAPIC_VER); 578 io_apic_versions[apic] = ux; 579 } 580 581 /* program each IO APIC in the system */ 582 for (apic = 0; apic < mp_napics; ++apic) 583 if (io_apic_setup(apic) < 0) 584 panic("IO APIC setup failure"); 585 586 /* install a 'Spurious INTerrupt' vector */ 587 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 588 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 589 590 /* install an inter-CPU IPI for TLB invalidation */ 591 setidt(XINVLTLB_OFFSET, Xinvltlb, 592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 593 594#ifdef BETTER_CLOCK 595 /* install an inter-CPU IPI for reading processor state */ 596 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate, 597 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 598#endif 599 600 /* install an inter-CPU IPI for forcing an additional software trap */ 601 setidt(XCPUAST_OFFSET, Xcpuast, 602 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 603 604 /* install an inter-CPU IPI for interrupt forwarding */ 605 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq, 606 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 607 608 /* install an inter-CPU IPI for CPU stop/restart */ 609 setidt(XCPUSTOP_OFFSET, Xcpustop, 610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 611 612#if defined(TEST_TEST1) 613 /* install a "fake hardware INTerrupt" vector */ 614 setidt(XTEST1_OFFSET, Xtest1, 615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 616#endif /** TEST_TEST1 */ 617 618#endif /* APIC_IO */ 619 620 /* initialize all SMP locks */ 621 init_locks(); 622 623 /* start each Application Processor */ 624 start_all_aps(boot_addr); 625 626 /* 627 * The init process might be started on a different CPU now, 628 * and the boot CPU might not call prepare_usermode to get 629 * cr0 correctly configured. Thus we initialize cr0 here. 630 */ 631 load_cr0(rcr0() | CR0_WP | CR0_AM); 632} 633 634 635/* 636 * look for the MP spec signature 637 */ 638 639/* string defined by the Intel MP Spec as identifying the MP table */ 640#define MP_SIG 0x5f504d5f /* _MP_ */ 641#define NEXT(X) ((X) += 4) 642static int 643search_for_sig(u_int32_t target, int count) 644{ 645 int x; 646 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 647 648 for (x = 0; x < count; NEXT(x)) 649 if (addr[x] == MP_SIG) 650 /* make array index a byte index */ 651 return (target + (x * sizeof(u_int32_t))); 652 653 return -1; 654} 655 656 657static basetable_entry basetable_entry_types[] = 658{ 659 {0, 20, "Processor"}, 660 {1, 8, "Bus"}, 661 {2, 8, "I/O APIC"}, 662 {3, 8, "I/O INT"}, 663 {4, 8, "Local INT"} 664}; 665 666typedef struct BUSDATA { 667 u_char bus_id; 668 enum busTypes bus_type; 669} bus_datum; 670 671typedef struct INTDATA { 672 u_char int_type; 673 u_short int_flags; 674 u_char src_bus_id; 675 u_char src_bus_irq; 676 u_char dst_apic_id; 677 u_char dst_apic_int; 678} io_int, local_int; 679 680typedef struct BUSTYPENAME { 681 u_char type; 682 char name[7]; 683} bus_type_name; 684 685static bus_type_name bus_type_table[] = 686{ 687 {CBUS, "CBUS"}, 688 {CBUSII, "CBUSII"}, 689 {EISA, "EISA"}, 690 {UNKNOWN_BUSTYPE, "---"}, 691 {UNKNOWN_BUSTYPE, "---"}, 692 {ISA, "ISA"}, 693 {UNKNOWN_BUSTYPE, "---"}, 694 {UNKNOWN_BUSTYPE, "---"}, 695 {UNKNOWN_BUSTYPE, "---"}, 696 {UNKNOWN_BUSTYPE, "---"}, 697 {UNKNOWN_BUSTYPE, "---"}, 698 {UNKNOWN_BUSTYPE, "---"}, 699 {PCI, "PCI"}, 700 {UNKNOWN_BUSTYPE, "---"}, 701 {UNKNOWN_BUSTYPE, "---"}, 702 {UNKNOWN_BUSTYPE, "---"}, 703 {UNKNOWN_BUSTYPE, "---"}, 704 {XPRESS, "XPRESS"}, 705 {UNKNOWN_BUSTYPE, "---"} 706}; 707/* from MP spec v1.4, table 5-1 */ 708static int default_data[7][5] = 709{ 710/* nbus, id0, type0, id1, type1 */ 711 {1, 0, ISA, 255, 255}, 712 {1, 0, EISA, 255, 255}, 713 {1, 0, EISA, 255, 255}, 714 {0, 255, 255, 255, 255},/* MCA not supported */ 715 {2, 0, ISA, 1, PCI}, 716 {2, 0, EISA, 1, PCI}, 717 {0, 255, 255, 255, 255} /* MCA not supported */ 718}; 719 720 721/* the bus data */ 722static bus_datum bus_data[NBUS]; 723 724/* the IO INT data, one entry per possible APIC INTerrupt */ 725static io_int io_apic_ints[NINTR]; 726 727static int nintrs; 728 729static int processor_entry __P((proc_entry_ptr entry, int cpu)); 730static int bus_entry __P((bus_entry_ptr entry, int bus)); 731static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 732static int int_entry __P((int_entry_ptr entry, int intr)); 733static int lookup_bus_type __P((char *name)); 734 735 736/* 737 * 1st pass on motherboard's Intel MP specification table. 738 * 739 * initializes: 740 * mp_ncpus = 1 741 * 742 * determines: 743 * cpu_apic_address (common to all CPUs) 744 * io_apic_address[N] 745 * mp_naps 746 * mp_nbusses 747 * mp_napics 748 * nintrs 749 */ 750static int 751mptable_pass1(void) 752{ 753 int x; 754 mpcth_t cth; 755 int totalSize; 756 void* position; 757 int count; 758 int type; 759 int mustpanic; 760 761 POSTCODE(MPTABLE_PASS1_POST); 762 763 mustpanic = 0; 764 765 /* clear various tables */ 766 for (x = 0; x < NAPICID; ++x) { 767 io_apic_address[x] = ~0; /* IO APIC address table */ 768 } 769 770 /* init everything to empty */ 771 mp_naps = 0; 772 mp_nbusses = 0; 773 mp_napics = 0; 774 nintrs = 0; 775 776 /* check for use of 'default' configuration */ 777 if (MPFPS_MPFB1 != 0) { 778 /* use default addresses */ 779 cpu_apic_address = DEFAULT_APIC_BASE; 780 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 781 782 /* fill in with defaults */ 783 mp_naps = 2; /* includes BSP */ 784 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 785#if defined(APIC_IO) 786 mp_napics = 1; 787 nintrs = 16; 788#endif /* APIC_IO */ 789 } 790 else { 791 if ((cth = mpfps->pap) == 0) 792 panic("MP Configuration Table Header MISSING!"); 793 794 cpu_apic_address = (vm_offset_t) cth->apic_address; 795 796 /* walk the table, recording info of interest */ 797 totalSize = cth->base_table_length - sizeof(struct MPCTH); 798 position = (u_char *) cth + sizeof(struct MPCTH); 799 count = cth->entry_count; 800 801 while (count--) { 802 switch (type = *(u_char *) position) { 803 case 0: /* processor_entry */ 804 if (((proc_entry_ptr)position)->cpu_flags 805 & PROCENTRY_FLAG_EN) 806 ++mp_naps; 807 break; 808 case 1: /* bus_entry */ 809 ++mp_nbusses; 810 break; 811 case 2: /* io_apic_entry */ 812 if (((io_apic_entry_ptr)position)->apic_flags 813 & IOAPICENTRY_FLAG_EN) 814 io_apic_address[mp_napics++] = 815 (vm_offset_t)((io_apic_entry_ptr) 816 position)->apic_address; 817 break; 818 case 3: /* int_entry */ 819 ++nintrs; 820 break; 821 case 4: /* int_entry */ 822 break; 823 default: 824 panic("mpfps Base Table HOSED!"); 825 /* NOTREACHED */ 826 } 827 828 totalSize -= basetable_entry_types[type].length; 829 (u_char*)position += basetable_entry_types[type].length; 830 } 831 } 832 833 /* qualify the numbers */ 834 if (mp_naps > NCPU) 835#if 0 /* XXX FIXME: kern/4255 */ 836 printf("Warning: only using %d of %d available CPUs!\n", 837 NCPU, mp_naps); 838#else 839 { 840 printf("NCPU cannot be different than actual CPU count.\n"); 841 printf(" add 'options NCPU=%d' to your kernel config file,\n", 842 mp_naps); 843 printf(" then rerun config & rebuild your SMP kernel\n"); 844 mustpanic = 1; 845 } 846#endif /* XXX FIXME: kern/4255 */ 847 if (mp_nbusses > NBUS) { 848 printf("found %d busses, increase NBUS\n", mp_nbusses); 849 mustpanic = 1; 850 } 851 if (mp_napics > NAPIC) { 852 printf("found %d apics, increase NAPIC\n", mp_napics); 853 mustpanic = 1; 854 } 855 if (nintrs > NINTR) { 856 printf("found %d intrs, increase NINTR\n", nintrs); 857 mustpanic = 1; 858 } 859 860 /* 861 * Count the BSP. 862 * This is also used as a counter while starting the APs. 863 */ 864 mp_ncpus = 1; 865 866 --mp_naps; /* subtract the BSP */ 867 868 return mustpanic; 869} 870 871 872/* 873 * 2nd pass on motherboard's Intel MP specification table. 874 * 875 * sets: 876 * boot_cpu_id 877 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 878 * CPU_TO_ID(N), logical CPU to APIC ID table 879 * IO_TO_ID(N), logical IO to APIC ID table 880 * bus_data[N] 881 * io_apic_ints[N] 882 */ 883static int 884mptable_pass2(void) 885{ 886 int x; 887 mpcth_t cth; 888 int totalSize; 889 void* position; 890 int count; 891 int type; 892 int apic, bus, cpu, intr; 893 894 POSTCODE(MPTABLE_PASS2_POST); 895 896 /* clear various tables */ 897 for (x = 0; x < NAPICID; ++x) { 898 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 899 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 900 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 901 } 902 903 /* clear bus data table */ 904 for (x = 0; x < NBUS; ++x) 905 bus_data[x].bus_id = 0xff; 906 907 /* clear IO APIC INT table */ 908 for (x = 0; x < NINTR; ++x) 909 io_apic_ints[x].int_type = 0xff; 910 911 /* setup the cpu/apic mapping arrays */ 912 boot_cpu_id = -1; 913 914 /* record whether PIC or virtual-wire mode */ 915 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 916 917 /* check for use of 'default' configuration */ 918 if (MPFPS_MPFB1 != 0) 919 return MPFPS_MPFB1; /* return default configuration type */ 920 921 if ((cth = mpfps->pap) == 0) 922 panic("MP Configuration Table Header MISSING!"); 923 924 /* walk the table, recording info of interest */ 925 totalSize = cth->base_table_length - sizeof(struct MPCTH); 926 position = (u_char *) cth + sizeof(struct MPCTH); 927 count = cth->entry_count; 928 apic = bus = intr = 0; 929 cpu = 1; /* pre-count the BSP */ 930 931 while (count--) { 932 switch (type = *(u_char *) position) { 933 case 0: 934 if (processor_entry(position, cpu)) 935 ++cpu; 936 break; 937 case 1: 938 if (bus_entry(position, bus)) 939 ++bus; 940 break; 941 case 2: 942 if (io_apic_entry(position, apic)) 943 ++apic; 944 break; 945 case 3: 946 if (int_entry(position, intr)) 947 ++intr; 948 break; 949 case 4: 950 /* int_entry(position); */ 951 break; 952 default: 953 panic("mpfps Base Table HOSED!"); 954 /* NOTREACHED */ 955 } 956 957 totalSize -= basetable_entry_types[type].length; 958 (u_char *) position += basetable_entry_types[type].length; 959 } 960 961 if (boot_cpu_id == -1) 962 panic("NO BSP found!"); 963 964 /* report fact that its NOT a default configuration */ 965 return 0; 966} 967 968 969/* 970 * parse an Intel MP specification table 971 */ 972static void 973fix_mp_table(void) 974{ 975 int x; 976 int id; 977 int bus_0; 978 int bus_pci; 979 int num_pci_bus; 980 981 /* 982 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 983 * did it wrong. The MP spec says that when more than 1 PCI bus 984 * exists the BIOS must begin with bus entries for the PCI bus and use 985 * actual PCI bus numbering. This implies that when only 1 PCI bus 986 * exists the BIOS can choose to ignore this ordering, and indeed many 987 * MP motherboards do ignore it. This causes a problem when the PCI 988 * sub-system makes requests of the MP sub-system based on PCI bus 989 * numbers. So here we look for the situation and renumber the 990 * busses and associated INTs in an effort to "make it right". 991 */ 992 993 /* find bus 0, PCI bus, count the number of PCI busses */ 994 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 995 if (bus_data[x].bus_id == 0) { 996 bus_0 = x; 997 } 998 if (bus_data[x].bus_type == PCI) { 999 ++num_pci_bus; 1000 bus_pci = x; 1001 } 1002 } 1003 /* 1004 * bus_0 == slot of bus with ID of 0 1005 * bus_pci == slot of last PCI bus encountered 1006 */ 1007 1008 /* check the 1 PCI bus case for sanity */ 1009 if (num_pci_bus == 1) { 1010 1011 /* if it is number 0 all is well */ 1012 if (bus_data[bus_pci].bus_id == 0) 1013 return; 1014 1015 /* mis-numbered, swap with whichever bus uses slot 0 */ 1016 1017 /* swap the bus entry types */ 1018 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1019 bus_data[bus_0].bus_type = PCI; 1020 1021 /* swap each relavant INTerrupt entry */ 1022 id = bus_data[bus_pci].bus_id; 1023 for (x = 0; x < nintrs; ++x) { 1024 if (io_apic_ints[x].src_bus_id == id) { 1025 io_apic_ints[x].src_bus_id = 0; 1026 } 1027 else if (io_apic_ints[x].src_bus_id == 0) { 1028 io_apic_ints[x].src_bus_id = id; 1029 } 1030 } 1031 } 1032 /* sanity check if more than 1 PCI bus */ 1033 else if (num_pci_bus > 1) { 1034 for (x = 0; x < mp_nbusses; ++x) { 1035 if (bus_data[x].bus_type != PCI) 1036 continue; 1037 if (bus_data[x].bus_id >= num_pci_bus) 1038 panic("bad PCI bus numbering"); 1039 } 1040 } 1041} 1042 1043 1044static int 1045processor_entry(proc_entry_ptr entry, int cpu) 1046{ 1047 /* check for usability */ 1048 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1049 return 0; 1050 1051 /* check for BSP flag */ 1052 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1053 boot_cpu_id = entry->apic_id; 1054 CPU_TO_ID(0) = entry->apic_id; 1055 ID_TO_CPU(entry->apic_id) = 0; 1056 return 0; /* its already been counted */ 1057 } 1058 1059 /* add another AP to list, if less than max number of CPUs */ 1060 else { 1061 CPU_TO_ID(cpu) = entry->apic_id; 1062 ID_TO_CPU(entry->apic_id) = cpu; 1063 return 1; 1064 } 1065} 1066 1067 1068static int 1069bus_entry(bus_entry_ptr entry, int bus) 1070{ 1071 int x; 1072 char c, name[8]; 1073 1074 /* encode the name into an index */ 1075 for (x = 0; x < 6; ++x) { 1076 if ((c = entry->bus_type[x]) == ' ') 1077 break; 1078 name[x] = c; 1079 } 1080 name[x] = '\0'; 1081 1082 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1083 panic("unknown bus type: '%s'", name); 1084 1085 bus_data[bus].bus_id = entry->bus_id; 1086 bus_data[bus].bus_type = x; 1087 1088 return 1; 1089} 1090 1091 1092static int 1093io_apic_entry(io_apic_entry_ptr entry, int apic) 1094{ 1095 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1096 return 0; 1097 1098 IO_TO_ID(apic) = entry->apic_id; 1099 ID_TO_IO(entry->apic_id) = apic; 1100 1101 return 1; 1102} 1103 1104 1105static int 1106lookup_bus_type(char *name) 1107{ 1108 int x; 1109 1110 for (x = 0; x < MAX_BUSTYPE; ++x) 1111 if (strcmp(bus_type_table[x].name, name) == 0) 1112 return bus_type_table[x].type; 1113 1114 return UNKNOWN_BUSTYPE; 1115} 1116 1117 1118static int 1119int_entry(int_entry_ptr entry, int intr) 1120{ 1121 io_apic_ints[intr].int_type = entry->int_type; 1122 io_apic_ints[intr].int_flags = entry->int_flags; 1123 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1124 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1125 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1126 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1127 1128 return 1; 1129} 1130 1131 1132static int 1133apic_int_is_bus_type(int intr, int bus_type) 1134{ 1135 int bus; 1136 1137 for (bus = 0; bus < mp_nbusses; ++bus) 1138 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1139 && ((int) bus_data[bus].bus_type == bus_type)) 1140 return 1; 1141 1142 return 0; 1143} 1144 1145 1146/* 1147 * Given a traditional ISA INT mask, return an APIC mask. 1148 */ 1149u_int 1150isa_apic_mask(u_int isa_mask) 1151{ 1152 int isa_irq; 1153 int apic_pin; 1154 1155#if defined(SKIP_IRQ15_REDIRECT) 1156 if (isa_mask == (1 << 15)) { 1157 printf("skipping ISA IRQ15 redirect\n"); 1158 return isa_mask; 1159 } 1160#endif /* SKIP_IRQ15_REDIRECT */ 1161 1162 isa_irq = ffs(isa_mask); /* find its bit position */ 1163 if (isa_irq == 0) /* doesn't exist */ 1164 return 0; 1165 --isa_irq; /* make it zero based */ 1166 1167 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1168 if (apic_pin == -1) 1169 return 0; 1170 1171 return (1 << apic_pin); /* convert pin# to a mask */ 1172} 1173 1174 1175/* 1176 * Determine which APIC pin an ISA/EISA INT is attached to. 1177 */ 1178#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1179#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1180 1181#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1182int 1183isa_apic_pin(int isa_irq) 1184{ 1185 int intr; 1186 1187 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1188 if (INTTYPE(intr) == 0) { /* standard INT */ 1189 if (SRCBUSIRQ(intr) == isa_irq) { 1190 if (apic_int_is_bus_type(intr, ISA) || 1191 apic_int_is_bus_type(intr, EISA)) 1192 return INTPIN(intr); /* found */ 1193 } 1194 } 1195 } 1196 return -1; /* NOT found */ 1197} 1198 1199 1200/* 1201 * Determine which APIC pin a PCI INT is attached to. 1202 */ 1203#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1204#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1205#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1206int 1207pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1208{ 1209 int intr; 1210 1211 --pciInt; /* zero based */ 1212 1213 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1214 if ((INTTYPE(intr) == 0) /* standard INT */ 1215 && (SRCBUSID(intr) == pciBus) 1216 && (SRCBUSDEVICE(intr) == pciDevice) 1217 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1218 if (apic_int_is_bus_type(intr, PCI)) 1219 return INTPIN(intr); /* exact match */ 1220 1221 return -1; /* NOT found */ 1222} 1223 1224int 1225next_apic_pin(int pin) 1226{ 1227 int intr, ointr; 1228 int bus, bustype; 1229 1230 bus = 0; 1231 bustype = 0; 1232 for (intr = 0; intr < nintrs; intr++) { 1233 if (INTPIN(intr) != pin || INTTYPE(intr) != 0) 1234 continue; 1235 bus = SRCBUSID(intr); 1236 bustype = apic_bus_type(bus); 1237 if (bustype != ISA && 1238 bustype != EISA && 1239 bustype != PCI) 1240 continue; 1241 break; 1242 } 1243 if (intr >= nintrs) { 1244 return -1; 1245 } 1246 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1247 if (INTTYPE(ointr) != 0) 1248 continue; 1249 if (bus != SRCBUSID(ointr)) 1250 continue; 1251 if (bustype == PCI) { 1252 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1253 continue; 1254 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1255 continue; 1256 } 1257 if (bustype == ISA || bustype == EISA) { 1258 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1259 continue; 1260 } 1261 if (INTPIN(intr) == INTPIN(ointr)) 1262 continue; 1263 break; 1264 } 1265 if (ointr >= nintrs) { 1266 return -1; 1267 } 1268 return INTPIN(ointr); 1269} 1270#undef SRCBUSLINE 1271#undef SRCBUSDEVICE 1272#undef SRCBUSID 1273#undef SRCBUSIRQ 1274 1275#undef INTPIN 1276#undef INTTYPE 1277 1278 1279/* 1280 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1281 * 1282 * XXX FIXME: 1283 * Exactly what this means is unclear at this point. It is a solution 1284 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1285 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1286 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1287 * option. 1288 */ 1289int 1290undirect_isa_irq(int rirq) 1291{ 1292#if defined(READY) 1293 printf("Freeing redirected ISA irq %d.\n", rirq); 1294 /** FIXME: tickle the MB redirector chip */ 1295 return ???; 1296#else 1297 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1298 return 0; 1299#endif /* READY */ 1300} 1301 1302 1303/* 1304 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1305 */ 1306int 1307undirect_pci_irq(int rirq) 1308{ 1309#if defined(READY) 1310 if (bootverbose) 1311 printf("Freeing redirected PCI irq %d.\n", rirq); 1312 1313 /** FIXME: tickle the MB redirector chip */ 1314 return ???; 1315#else 1316 if (bootverbose) 1317 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1318 rirq); 1319 return 0; 1320#endif /* READY */ 1321} 1322 1323 1324/* 1325 * given a bus ID, return: 1326 * the bus type if found 1327 * -1 if NOT found 1328 */ 1329int 1330apic_bus_type(int id) 1331{ 1332 int x; 1333 1334 for (x = 0; x < mp_nbusses; ++x) 1335 if (bus_data[x].bus_id == id) 1336 return bus_data[x].bus_type; 1337 1338 return -1; 1339} 1340 1341 1342/* 1343 * given a LOGICAL APIC# and pin#, return: 1344 * the associated src bus ID if found 1345 * -1 if NOT found 1346 */ 1347int 1348apic_src_bus_id(int apic, int pin) 1349{ 1350 int x; 1351 1352 /* search each of the possible INTerrupt sources */ 1353 for (x = 0; x < nintrs; ++x) 1354 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1355 (pin == io_apic_ints[x].dst_apic_int)) 1356 return (io_apic_ints[x].src_bus_id); 1357 1358 return -1; /* NOT found */ 1359} 1360 1361 1362/* 1363 * given a LOGICAL APIC# and pin#, return: 1364 * the associated src bus IRQ if found 1365 * -1 if NOT found 1366 */ 1367int 1368apic_src_bus_irq(int apic, int pin) 1369{ 1370 int x; 1371 1372 for (x = 0; x < nintrs; x++) 1373 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1374 (pin == io_apic_ints[x].dst_apic_int)) 1375 return (io_apic_ints[x].src_bus_irq); 1376 1377 return -1; /* NOT found */ 1378} 1379 1380 1381/* 1382 * given a LOGICAL APIC# and pin#, return: 1383 * the associated INTerrupt type if found 1384 * -1 if NOT found 1385 */ 1386int 1387apic_int_type(int apic, int pin) 1388{ 1389 int x; 1390 1391 /* search each of the possible INTerrupt sources */ 1392 for (x = 0; x < nintrs; ++x) 1393 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1394 (pin == io_apic_ints[x].dst_apic_int)) 1395 return (io_apic_ints[x].int_type); 1396 1397 return -1; /* NOT found */ 1398} 1399 1400 1401/* 1402 * given a LOGICAL APIC# and pin#, return: 1403 * the associated trigger mode if found 1404 * -1 if NOT found 1405 */ 1406int 1407apic_trigger(int apic, int pin) 1408{ 1409 int x; 1410 1411 /* search each of the possible INTerrupt sources */ 1412 for (x = 0; x < nintrs; ++x) 1413 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1414 (pin == io_apic_ints[x].dst_apic_int)) 1415 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1416 1417 return -1; /* NOT found */ 1418} 1419 1420 1421/* 1422 * given a LOGICAL APIC# and pin#, return: 1423 * the associated 'active' level if found 1424 * -1 if NOT found 1425 */ 1426int 1427apic_polarity(int apic, int pin) 1428{ 1429 int x; 1430 1431 /* search each of the possible INTerrupt sources */ 1432 for (x = 0; x < nintrs; ++x) 1433 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1434 (pin == io_apic_ints[x].dst_apic_int)) 1435 return (io_apic_ints[x].int_flags & 0x03); 1436 1437 return -1; /* NOT found */ 1438} 1439 1440 1441/* 1442 * set data according to MP defaults 1443 * FIXME: probably not complete yet... 1444 */ 1445static void 1446default_mp_table(int type) 1447{ 1448 int ap_cpu_id; 1449#if defined(APIC_IO) 1450 u_int32_t ux; 1451 int io_apic_id; 1452 int pin; 1453#endif /* APIC_IO */ 1454 1455#if 0 1456 printf(" MP default config type: %d\n", type); 1457 switch (type) { 1458 case 1: 1459 printf(" bus: ISA, APIC: 82489DX\n"); 1460 break; 1461 case 2: 1462 printf(" bus: EISA, APIC: 82489DX\n"); 1463 break; 1464 case 3: 1465 printf(" bus: EISA, APIC: 82489DX\n"); 1466 break; 1467 case 4: 1468 printf(" bus: MCA, APIC: 82489DX\n"); 1469 break; 1470 case 5: 1471 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1472 break; 1473 case 6: 1474 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1475 break; 1476 case 7: 1477 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1478 break; 1479 default: 1480 printf(" future type\n"); 1481 break; 1482 /* NOTREACHED */ 1483 } 1484#endif /* 0 */ 1485 1486 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1487 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1488 1489 /* BSP */ 1490 CPU_TO_ID(0) = boot_cpu_id; 1491 ID_TO_CPU(boot_cpu_id) = 0; 1492 1493 /* one and only AP */ 1494 CPU_TO_ID(1) = ap_cpu_id; 1495 ID_TO_CPU(ap_cpu_id) = 1; 1496 1497#if defined(APIC_IO) 1498 /* one and only IO APIC */ 1499 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1500 1501 /* 1502 * sanity check, refer to MP spec section 3.6.6, last paragraph 1503 * necessary as some hardware isn't properly setting up the IO APIC 1504 */ 1505#if defined(REALLY_ANAL_IOAPICID_VALUE) 1506 if (io_apic_id != 2) { 1507#else 1508 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1509#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1510 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1511 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1512 ux |= 0x02000000; /* set it to '2' */ 1513 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1514 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1515 if ((ux & APIC_ID_MASK) != 0x02000000) 1516 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1517 io_apic_id = 2; 1518 } 1519 IO_TO_ID(0) = io_apic_id; 1520 ID_TO_IO(io_apic_id) = 0; 1521#endif /* APIC_IO */ 1522 1523 /* fill out bus entries */ 1524 switch (type) { 1525 case 1: 1526 case 2: 1527 case 3: 1528 case 5: 1529 case 6: 1530 bus_data[0].bus_id = default_data[type - 1][1]; 1531 bus_data[0].bus_type = default_data[type - 1][2]; 1532 bus_data[1].bus_id = default_data[type - 1][3]; 1533 bus_data[1].bus_type = default_data[type - 1][4]; 1534 break; 1535 1536 /* case 4: case 7: MCA NOT supported */ 1537 default: /* illegal/reserved */ 1538 panic("BAD default MP config: %d", type); 1539 /* NOTREACHED */ 1540 } 1541 1542#if defined(APIC_IO) 1543 /* general cases from MP v1.4, table 5-2 */ 1544 for (pin = 0; pin < 16; ++pin) { 1545 io_apic_ints[pin].int_type = 0; 1546 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1547 io_apic_ints[pin].src_bus_id = 0; 1548 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1549 io_apic_ints[pin].dst_apic_id = io_apic_id; 1550 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1551 } 1552 1553 /* special cases from MP v1.4, table 5-2 */ 1554 if (type == 2) { 1555 io_apic_ints[2].int_type = 0xff; /* N/C */ 1556 io_apic_ints[13].int_type = 0xff; /* N/C */ 1557#if !defined(APIC_MIXED_MODE) 1558 /** FIXME: ??? */ 1559 panic("sorry, can't support type 2 default yet"); 1560#endif /* APIC_MIXED_MODE */ 1561 } 1562 else 1563 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1564 1565 if (type == 7) 1566 io_apic_ints[0].int_type = 0xff; /* N/C */ 1567 else 1568 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1569#endif /* APIC_IO */ 1570} 1571 1572 1573/* 1574 * initialize all the SMP locks 1575 */ 1576 1577/* critical region around IO APIC, apic_imen */ 1578struct simplelock imen_lock; 1579 1580/* critical region around splxx(), cpl, cml, cil, ipending */ 1581struct simplelock cpl_lock; 1582 1583/* Make FAST_INTR() routines sequential */ 1584struct simplelock fast_intr_lock; 1585 1586/* critical region around INTR() routines */ 1587struct simplelock intr_lock; 1588 1589/* lock regions protected in UP kernel via cli/sti */ 1590struct simplelock mpintr_lock; 1591 1592/* lock region used by kernel profiling */ 1593struct simplelock mcount_lock; 1594 1595#ifdef USE_COMLOCK 1596/* locks com (tty) data/hardware accesses: a FASTINTR() */ 1597struct simplelock com_lock; 1598#endif /* USE_COMLOCK */ 1599 1600#ifdef USE_CLOCKLOCK 1601/* lock regions around the clock hardware */ 1602struct simplelock clock_lock; 1603#endif /* USE_CLOCKLOCK */ 1604 1605static void 1606init_locks(void) 1607{ 1608 /* 1609 * Get the initial mp_lock with a count of 1 for the BSP. 1610 * This uses a LOGICAL cpu ID, ie BSP == 0. 1611 */ 1612 mp_lock = 0x00000001; 1613 1614 /* ISR uses its own "giant lock" */ 1615 isr_lock = FREE_LOCK; 1616 1617#if defined(APIC_INTR_DIAGNOSTIC) && defined(APIC_INTR_DIAGNOSTIC_IRQ) 1618 s_lock_init((struct simplelock*)&apic_itrace_debuglock); 1619#endif 1620 1621 s_lock_init((struct simplelock*)&mpintr_lock); 1622 1623 s_lock_init((struct simplelock*)&mcount_lock); 1624 1625 s_lock_init((struct simplelock*)&fast_intr_lock); 1626 s_lock_init((struct simplelock*)&intr_lock); 1627 s_lock_init((struct simplelock*)&imen_lock); 1628 s_lock_init((struct simplelock*)&cpl_lock); 1629 1630#ifdef USE_COMLOCK 1631 s_lock_init((struct simplelock*)&com_lock); 1632#endif /* USE_COMLOCK */ 1633#ifdef USE_CLOCKLOCK 1634 s_lock_init((struct simplelock*)&clock_lock); 1635#endif /* USE_CLOCKLOCK */ 1636} 1637 1638 1639/* 1640 * start each AP in our list 1641 */ 1642static int 1643start_all_aps(u_int boot_addr) 1644{ 1645 int x, i; 1646 u_char mpbiosreason; 1647 u_long mpbioswarmvec; 1648 pd_entry_t *newptd; 1649 pt_entry_t *newpt; 1650 struct globaldata *gd; 1651 char *stack; 1652 pd_entry_t *myPTD; 1653 1654 POSTCODE(START_ALL_APS_POST); 1655 1656 /* initialize BSP's local APIC */ 1657 apic_initialize(); 1658 bsp_apic_ready = 1; 1659 1660 /* install the AP 1st level boot code */ 1661 install_ap_tramp(boot_addr); 1662 1663 1664 /* save the current value of the warm-start vector */ 1665 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1666 outb(CMOS_REG, BIOS_RESET); 1667 mpbiosreason = inb(CMOS_DATA); 1668 1669 /* record BSP in CPU map */ 1670 all_cpus = 1; 1671 1672 /* start each AP */ 1673 for (x = 1; x <= mp_naps; ++x) { 1674 1675 /* This is a bit verbose, it will go away soon. */ 1676 1677 /* alloc new page table directory */ 1678 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1679 1680 /* Store the virtual PTD address for this CPU */ 1681 IdlePTDS[x] = newptd; 1682 1683 /* clone currently active one (ie: IdlePTD) */ 1684 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1685 1686 /* set up 0 -> 4MB P==V mapping for AP boot */ 1687 newptd[0] = (void *)(uintptr_t)(PG_V | PG_RW | 1688 ((uintptr_t)(void *)KPTphys & PG_FRAME)); 1689 1690 /* store PTD for this AP's boot sequence */ 1691 myPTD = (pd_entry_t *)vtophys(newptd); 1692 1693 /* alloc new page table page */ 1694 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1695 1696 /* set the new PTD's private page to point there */ 1697 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1698 1699 /* install self referential entry */ 1700 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1701 1702 /* allocate a new private data page */ 1703 gd = (struct globaldata *)kmem_alloc(kernel_map, PAGE_SIZE); 1704 1705 /* wire it into the private page table page */ 1706 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(gd)); 1707 1708 /* wire the ptp into itself for access */ 1709 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1710 1711 /* copy in the pointer to the local apic */ 1712 newpt[2] = SMP_prvpt[2]; 1713 1714 /* and the IO apic mapping[s] */ 1715 for (i = 16; i < 32; i++) 1716 newpt[i] = SMP_prvpt[i]; 1717 1718 /* allocate and set up an idle stack data page */ 1719 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1720 for (i = 0; i < UPAGES; i++) 1721 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1722 1723 newpt[3 + UPAGES] = 0; /* *prv_CMAP1 */ 1724 newpt[4 + UPAGES] = 0; /* *prv_CMAP2 */ 1725 newpt[5 + UPAGES] = 0; /* *prv_CMAP3 */ 1726 newpt[6 + UPAGES] = 0; /* *prv_PMAP1 */ 1727 1728 /* prime data page for it to use */ 1729 gd->cpuid = x; 1730 gd->cpu_lockid = x << 24; 1731 gd->my_idlePTD = myPTD; 1732 gd->prv_CMAP1 = &newpt[3 + UPAGES]; 1733 gd->prv_CMAP2 = &newpt[4 + UPAGES]; 1734 gd->prv_CMAP3 = &newpt[5 + UPAGES]; 1735 gd->prv_PMAP1 = &newpt[6 + UPAGES]; 1736 1737 /* setup a vector to our boot code */ 1738 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1739 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1740 outb(CMOS_REG, BIOS_RESET); 1741 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1742 1743 bootPTD = myPTD; 1744 /* attempt to start the Application Processor */ 1745 CHECK_INIT(99); /* setup checkpoints */ 1746 if (!start_ap(x, boot_addr)) { 1747 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1748 CHECK_PRINT("trace"); /* show checkpoints */ 1749 /* better panic as the AP may be running loose */ 1750 printf("panic y/n? [y] "); 1751 if (cngetc() != 'n') 1752 panic("bye-bye"); 1753 } 1754 CHECK_PRINT("trace"); /* show checkpoints */ 1755 1756 /* record its version info */ 1757 cpu_apic_versions[x] = cpu_apic_versions[0]; 1758 1759 all_cpus |= (1 << x); /* record AP in CPU map */ 1760 } 1761 1762 /* build our map of 'other' CPUs */ 1763 other_cpus = all_cpus & ~(1 << cpuid); 1764 1765 /* fill in our (BSP) APIC version */ 1766 cpu_apic_versions[0] = lapic.version; 1767 1768 /* restore the warmstart vector */ 1769 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1770 outb(CMOS_REG, BIOS_RESET); 1771 outb(CMOS_DATA, mpbiosreason); 1772 1773 /* 1774 * Set up the idle context for the BSP. Similar to above except 1775 * that some was done by locore, some by pmap.c and some is implicit 1776 * because the BSP is cpu#0 and the page is initially zero, and also 1777 * because we can refer to variables by name on the BSP.. 1778 */ 1779 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1780 1781 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1782 IdlePTDS[0] = newptd; 1783 1784 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1785 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1786 1787 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1788 1789 /* Allocate and setup BSP idle stack */ 1790 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1791 for (i = 0; i < UPAGES; i++) 1792 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1793 1794 pmap_set_opt_bsp(); 1795 1796 for (i = 0; i < mp_ncpus; i++) { 1797 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1798 } 1799 1800 /* number of APs actually started */ 1801 return mp_ncpus - 1; 1802} 1803 1804 1805/* 1806 * load the 1st level AP boot code into base memory. 1807 */ 1808 1809/* targets for relocation */ 1810extern void bigJump(void); 1811extern void bootCodeSeg(void); 1812extern void bootDataSeg(void); 1813extern void MPentry(void); 1814extern u_int MP_GDT; 1815extern u_int mp_gdtbase; 1816 1817static void 1818install_ap_tramp(u_int boot_addr) 1819{ 1820 int x; 1821 int size = *(int *) ((u_long) & bootMP_size); 1822 u_char *src = (u_char *) ((u_long) bootMP); 1823 u_char *dst = (u_char *) boot_addr + KERNBASE; 1824 u_int boot_base = (u_int) bootMP; 1825 u_int8_t *dst8; 1826 u_int16_t *dst16; 1827 u_int32_t *dst32; 1828 1829 POSTCODE(INSTALL_AP_TRAMP_POST); 1830 1831 for (x = 0; x < size; ++x) 1832 *dst++ = *src++; 1833 1834 /* 1835 * modify addresses in code we just moved to basemem. unfortunately we 1836 * need fairly detailed info about mpboot.s for this to work. changes 1837 * to mpboot.s might require changes here. 1838 */ 1839 1840 /* boot code is located in KERNEL space */ 1841 dst = (u_char *) boot_addr + KERNBASE; 1842 1843 /* modify the lgdt arg */ 1844 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1845 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1846 1847 /* modify the ljmp target for MPentry() */ 1848 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1849 *dst32 = ((u_int) MPentry - KERNBASE); 1850 1851 /* modify the target for boot code segment */ 1852 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1853 dst8 = (u_int8_t *) (dst16 + 1); 1854 *dst16 = (u_int) boot_addr & 0xffff; 1855 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1856 1857 /* modify the target for boot data segment */ 1858 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1859 dst8 = (u_int8_t *) (dst16 + 1); 1860 *dst16 = (u_int) boot_addr & 0xffff; 1861 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1862} 1863 1864 1865/* 1866 * this function starts the AP (application processor) identified 1867 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1868 * to accomplish this. This is necessary because of the nuances 1869 * of the different hardware we might encounter. It ain't pretty, 1870 * but it seems to work. 1871 */ 1872static int 1873start_ap(int logical_cpu, u_int boot_addr) 1874{ 1875 int physical_cpu; 1876 int vector; 1877 int cpus; 1878 u_long icr_lo, icr_hi; 1879 1880 POSTCODE(START_AP_POST); 1881 1882 /* get the PHYSICAL APIC ID# */ 1883 physical_cpu = CPU_TO_ID(logical_cpu); 1884 1885 /* calculate the vector */ 1886 vector = (boot_addr >> 12) & 0xff; 1887 1888 /* used as a watchpoint to signal AP startup */ 1889 cpus = mp_ncpus; 1890 1891 /* 1892 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1893 * and running the target CPU. OR this INIT IPI might be latched (P5 1894 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1895 * ignored. 1896 */ 1897 1898 /* setup the address for the target AP */ 1899 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1900 icr_hi |= (physical_cpu << 24); 1901 lapic.icr_hi = icr_hi; 1902 1903 /* do an INIT IPI: assert RESET */ 1904 icr_lo = lapic.icr_lo & 0xfff00000; 1905 lapic.icr_lo = icr_lo | 0x0000c500; 1906 1907 /* wait for pending status end */ 1908 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1909 /* spin */ ; 1910 1911 /* do an INIT IPI: deassert RESET */ 1912 lapic.icr_lo = icr_lo | 0x00008500; 1913 1914 /* wait for pending status end */ 1915 u_sleep(10000); /* wait ~10mS */ 1916 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1917 /* spin */ ; 1918 1919 /* 1920 * next we do a STARTUP IPI: the previous INIT IPI might still be 1921 * latched, (P5 bug) this 1st STARTUP would then terminate 1922 * immediately, and the previously started INIT IPI would continue. OR 1923 * the previous INIT IPI has already run. and this STARTUP IPI will 1924 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1925 * will run. 1926 */ 1927 1928 /* do a STARTUP IPI */ 1929 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1930 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1931 /* spin */ ; 1932 u_sleep(200); /* wait ~200uS */ 1933 1934 /* 1935 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1936 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1937 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1938 * recognized after hardware RESET or INIT IPI. 1939 */ 1940 1941 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1942 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1943 /* spin */ ; 1944 u_sleep(200); /* wait ~200uS */ 1945 1946 /* wait for it to start */ 1947 set_apic_timer(5000000);/* == 5 seconds */ 1948 while (read_apic_timer()) 1949 if (mp_ncpus > cpus) 1950 return 1; /* return SUCCESS */ 1951 1952 return 0; /* return FAILURE */ 1953} 1954 1955 1956/* 1957 * Flush the TLB on all other CPU's 1958 * 1959 * XXX: Needs to handshake and wait for completion before proceding. 1960 */ 1961void 1962smp_invltlb(void) 1963{ 1964#if defined(APIC_IO) 1965 if (smp_started && invltlb_ok) 1966 all_but_self_ipi(XINVLTLB_OFFSET); 1967#endif /* APIC_IO */ 1968} 1969 1970void 1971invlpg(u_int addr) 1972{ 1973 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1974 1975 /* send a message to the other CPUs */ 1976 smp_invltlb(); 1977} 1978 1979void 1980invltlb(void) 1981{ 1982 u_long temp; 1983 1984 /* 1985 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1986 * inlined. 1987 */ 1988 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1989 1990 /* send a message to the other CPUs */ 1991 smp_invltlb(); 1992} 1993 1994 1995/* 1996 * When called the executing CPU will send an IPI to all other CPUs 1997 * requesting that they halt execution. 1998 * 1999 * Usually (but not necessarily) called with 'other_cpus' as its arg. 2000 * 2001 * - Signals all CPUs in map to stop. 2002 * - Waits for each to stop. 2003 * 2004 * Returns: 2005 * -1: error 2006 * 0: NA 2007 * 1: ok 2008 * 2009 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 2010 * from executing at same time. 2011 */ 2012int 2013stop_cpus(u_int map) 2014{ 2015 if (!smp_started) 2016 return 0; 2017 2018 /* send the Xcpustop IPI to all CPUs in map */ 2019 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 2020 2021 while ((stopped_cpus & map) != map) 2022 /* spin */ ; 2023 2024 return 1; 2025} 2026 2027 2028/* 2029 * Called by a CPU to restart stopped CPUs. 2030 * 2031 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 2032 * 2033 * - Signals all CPUs in map to restart. 2034 * - Waits for each to restart. 2035 * 2036 * Returns: 2037 * -1: error 2038 * 0: NA 2039 * 1: ok 2040 */ 2041int 2042restart_cpus(u_int map) 2043{ 2044 if (!smp_started) 2045 return 0; 2046 2047 started_cpus = map; /* signal other cpus to restart */ 2048 2049 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 2050 /* spin */ ; 2051 2052 return 1; 2053} 2054 2055int smp_active = 0; /* are the APs allowed to run? */ 2056SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 2057 2058/* XXX maybe should be hw.ncpu */ 2059static int smp_cpus = 1; /* how many cpu's running */ 2060SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 2061 2062int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 2063SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 2064 2065/* Warning: Do not staticize. Used from swtch.s */ 2066int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */ 2067SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 2068 &do_page_zero_idle, 0, ""); 2069 2070/* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */ 2071int forward_irq_enabled = 1; 2072SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW, 2073 &forward_irq_enabled, 0, ""); 2074 2075/* Enable forwarding of a signal to a process running on a different CPU */ 2076int forward_signal_enabled = 1; 2077SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW, 2078 &forward_signal_enabled, 0, ""); 2079 2080/* Enable forwarding of roundrobin to all other cpus */ 2081int forward_roundrobin_enabled = 1; 2082SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW, 2083 &forward_roundrobin_enabled, 0, ""); 2084 2085/* 2086 * This is called once the rest of the system is up and running and we're 2087 * ready to let the AP's out of the pen. 2088 */ 2089void ap_init(void); 2090 2091void 2092ap_init() 2093{ 2094 u_int temp; 2095 u_int apic_id; 2096 2097 smp_cpus++; 2098 2099#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2100 lidt(&r_idt); 2101#endif 2102 2103 /* Build our map of 'other' CPUs. */ 2104 other_cpus = all_cpus & ~(1 << cpuid); 2105 2106 printf("SMP: AP CPU #%d Launched!\n", cpuid); 2107 2108 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 2109 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 2110 2111 /* A quick check from sanity claus */ 2112 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2113 if (cpuid != apic_id) { 2114 printf("SMP: cpuid = %d\n", cpuid); 2115 printf("SMP: apic_id = %d\n", apic_id); 2116 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 2117 panic("cpuid mismatch! boom!!"); 2118 } 2119 2120 getmtrr(); 2121 2122 /* Init local apic for irq's */ 2123 apic_initialize(); 2124 2125 /* 2126 * Activate smp_invltlb, although strictly speaking, this isn't 2127 * quite correct yet. We should have a bitfield for cpus willing 2128 * to accept TLB flush IPI's or something and sync them. 2129 */ 2130 invltlb_ok = 1; 2131 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2132 smp_active = 1; /* historic */ 2133 2134 curproc = NULL; /* make sure */ 2135} 2136 2137#ifdef BETTER_CLOCK 2138 2139#define CHECKSTATE_USER 0 2140#define CHECKSTATE_SYS 1 2141#define CHECKSTATE_INTR 2 2142 2143/* Do not staticize. Used from apic_vector.s */ 2144struct proc* checkstate_curproc[NCPU]; 2145int checkstate_cpustate[NCPU]; 2146u_long checkstate_pc[NCPU]; 2147 2148extern long cp_time[CPUSTATES]; 2149 2150#define PC_TO_INDEX(pc, prof) \ 2151 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \ 2152 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1) 2153 2154static void 2155addupc_intr_forwarded(struct proc *p, int id, int *astmap) 2156{ 2157 int i; 2158 struct uprof *prof; 2159 u_long pc; 2160 2161 pc = checkstate_pc[id]; 2162 prof = &p->p_stats->p_prof; 2163 if (pc >= prof->pr_off && 2164 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) { 2165 if ((p->p_flag & P_OWEUPC) == 0) { 2166 prof->pr_addr = pc; 2167 prof->pr_ticks = 1; 2168 p->p_flag |= P_OWEUPC; 2169 } 2170 *astmap |= (1 << id); 2171 } 2172} 2173 2174static void 2175forwarded_statclock(int id, int pscnt, int *astmap) 2176{ 2177 struct pstats *pstats; 2178 long rss; 2179 struct rusage *ru; 2180 struct vmspace *vm; 2181 int cpustate; 2182 struct proc *p; 2183#ifdef GPROF 2184 register struct gmonparam *g; 2185 int i; 2186#endif 2187 2188 p = checkstate_curproc[id]; 2189 cpustate = checkstate_cpustate[id]; 2190 2191 switch (cpustate) { 2192 case CHECKSTATE_USER: 2193 if (p->p_flag & P_PROFIL) 2194 addupc_intr_forwarded(p, id, astmap); 2195 if (pscnt > 1) 2196 return; 2197 p->p_uticks++; 2198 if (p->p_nice > NZERO) 2199 cp_time[CP_NICE]++; 2200 else 2201 cp_time[CP_USER]++; 2202 break; 2203 case CHECKSTATE_SYS: 2204#ifdef GPROF 2205 /* 2206 * Kernel statistics are just like addupc_intr, only easier. 2207 */ 2208 g = &_gmonparam; 2209 if (g->state == GMON_PROF_ON) { 2210 i = checkstate_pc[id] - g->lowpc; 2211 if (i < g->textsize) { 2212 i /= HISTFRACTION * sizeof(*g->kcount); 2213 g->kcount[i]++; 2214 } 2215 } 2216#endif 2217 if (pscnt > 1) 2218 return; 2219 2220 if (!p) 2221 cp_time[CP_IDLE]++; 2222 else { 2223 p->p_sticks++; 2224 cp_time[CP_SYS]++; 2225 } 2226 break; 2227 case CHECKSTATE_INTR: 2228 default: 2229#ifdef GPROF 2230 /* 2231 * Kernel statistics are just like addupc_intr, only easier. 2232 */ 2233 g = &_gmonparam; 2234 if (g->state == GMON_PROF_ON) { 2235 i = checkstate_pc[id] - g->lowpc; 2236 if (i < g->textsize) { 2237 i /= HISTFRACTION * sizeof(*g->kcount); 2238 g->kcount[i]++; 2239 } 2240 } 2241#endif 2242 if (pscnt > 1) 2243 return; 2244 if (p) 2245 p->p_iticks++; 2246 cp_time[CP_INTR]++; 2247 } 2248 if (p != NULL) { 2249 p->p_cpticks++; 2250 if (++p->p_estcpu == 0) 2251 p->p_estcpu--; 2252 if ((p->p_estcpu & 3) == 0) { 2253 resetpriority(p); 2254 if (p->p_priority >= PUSER) 2255 p->p_priority = p->p_usrpri; 2256 } 2257 2258 /* Update resource usage integrals and maximums. */ 2259 if ((pstats = p->p_stats) != NULL && 2260 (ru = &pstats->p_ru) != NULL && 2261 (vm = p->p_vmspace) != NULL) { 2262 ru->ru_ixrss += vm->vm_tsize * PAGE_SIZE / 1024; 2263 ru->ru_idrss += vm->vm_dsize * PAGE_SIZE / 1024; 2264 ru->ru_isrss += vm->vm_ssize * PAGE_SIZE / 1024; 2265 rss = vm->vm_pmap.pm_stats.resident_count * 2266 PAGE_SIZE / 1024; 2267 if (ru->ru_maxrss < rss) 2268 ru->ru_maxrss = rss; 2269 } 2270 } 2271} 2272 2273void 2274forward_statclock(int pscnt) 2275{ 2276 int map; 2277 int id; 2278 int i; 2279 2280 /* Kludge. We don't yet have separate locks for the interrupts 2281 * and the kernel. This means that we cannot let the other processors 2282 * handle complex interrupts while inhibiting them from entering 2283 * the kernel in a non-interrupt context. 2284 * 2285 * What we can do, without changing the locking mechanisms yet, 2286 * is letting the other processors handle a very simple interrupt 2287 * (wich determines the processor states), and do the main 2288 * work ourself. 2289 */ 2290 2291 if (!smp_started || !invltlb_ok || cold || panicstr) 2292 return; 2293 2294 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */ 2295 2296 map = other_cpus & ~stopped_cpus ; 2297 checkstate_probed_cpus = 0; 2298 if (map != 0) 2299 selected_apic_ipi(map, 2300 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2301 2302 i = 0; 2303 while (checkstate_probed_cpus != map) { 2304 /* spin */ 2305 i++; 2306 if (i == 100000) { 2307#ifdef BETTER_CLOCK_DIAGNOSTIC 2308 printf("forward_statclock: checkstate %x\n", 2309 checkstate_probed_cpus); 2310#endif 2311 break; 2312 } 2313 } 2314 2315 /* 2316 * Step 2: walk through other processors processes, update ticks and 2317 * profiling info. 2318 */ 2319 2320 map = 0; 2321 for (id = 0; id < mp_ncpus; id++) { 2322 if (id == cpuid) 2323 continue; 2324 if (((1 << id) & checkstate_probed_cpus) == 0) 2325 continue; 2326 forwarded_statclock(id, pscnt, &map); 2327 } 2328 if (map != 0) { 2329 checkstate_need_ast |= map; 2330 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2331 i = 0; 2332 while ((checkstate_need_ast & map) != 0) { 2333 /* spin */ 2334 i++; 2335 if (i > 100000) { 2336#ifdef BETTER_CLOCK_DIAGNOSTIC 2337 printf("forward_statclock: dropped ast 0x%x\n", 2338 checkstate_need_ast & map); 2339#endif 2340 break; 2341 } 2342 } 2343 } 2344} 2345 2346void 2347forward_hardclock(int pscnt) 2348{ 2349 int map; 2350 int id; 2351 struct proc *p; 2352 struct pstats *pstats; 2353 int i; 2354 2355 /* Kludge. We don't yet have separate locks for the interrupts 2356 * and the kernel. This means that we cannot let the other processors 2357 * handle complex interrupts while inhibiting them from entering 2358 * the kernel in a non-interrupt context. 2359 * 2360 * What we can do, without changing the locking mechanisms yet, 2361 * is letting the other processors handle a very simple interrupt 2362 * (wich determines the processor states), and do the main 2363 * work ourself. 2364 */ 2365 2366 if (!smp_started || !invltlb_ok || cold || panicstr) 2367 return; 2368 2369 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */ 2370 2371 map = other_cpus & ~stopped_cpus ; 2372 checkstate_probed_cpus = 0; 2373 if (map != 0) 2374 selected_apic_ipi(map, 2375 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED); 2376 2377 i = 0; 2378 while (checkstate_probed_cpus != map) { 2379 /* spin */ 2380 i++; 2381 if (i == 100000) { 2382#ifdef BETTER_CLOCK_DIAGNOSTIC 2383 printf("forward_hardclock: checkstate %x\n", 2384 checkstate_probed_cpus); 2385#endif 2386 break; 2387 } 2388 } 2389 2390 /* 2391 * Step 2: walk through other processors processes, update virtual 2392 * timer and profiling timer. If stathz == 0, also update ticks and 2393 * profiling info. 2394 */ 2395 2396 map = 0; 2397 for (id = 0; id < mp_ncpus; id++) { 2398 if (id == cpuid) 2399 continue; 2400 if (((1 << id) & checkstate_probed_cpus) == 0) 2401 continue; 2402 p = checkstate_curproc[id]; 2403 if (p) { 2404 pstats = p->p_stats; 2405 if (checkstate_cpustate[id] == CHECKSTATE_USER && 2406 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) && 2407 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) { 2408 psignal(p, SIGVTALRM); 2409 map |= (1 << id); 2410 } 2411 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) && 2412 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) { 2413 psignal(p, SIGPROF); 2414 map |= (1 << id); 2415 } 2416 } 2417 if (stathz == 0) { 2418 forwarded_statclock( id, pscnt, &map); 2419 } 2420 } 2421 if (map != 0) { 2422 checkstate_need_ast |= map; 2423 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2424 i = 0; 2425 while ((checkstate_need_ast & map) != 0) { 2426 /* spin */ 2427 i++; 2428 if (i > 100000) { 2429#ifdef BETTER_CLOCK_DIAGNOSTIC 2430 printf("forward_hardclock: dropped ast 0x%x\n", 2431 checkstate_need_ast & map); 2432#endif 2433 break; 2434 } 2435 } 2436 } 2437} 2438 2439#endif /* BETTER_CLOCK */ 2440 2441void 2442forward_signal(struct proc *p) 2443{ 2444 int map; 2445 int id; 2446 int i; 2447 2448 /* Kludge. We don't yet have separate locks for the interrupts 2449 * and the kernel. This means that we cannot let the other processors 2450 * handle complex interrupts while inhibiting them from entering 2451 * the kernel in a non-interrupt context. 2452 * 2453 * What we can do, without changing the locking mechanisms yet, 2454 * is letting the other processors handle a very simple interrupt 2455 * (wich determines the processor states), and do the main 2456 * work ourself. 2457 */ 2458 2459 if (!smp_started || !invltlb_ok || cold || panicstr) 2460 return; 2461 if (!forward_signal_enabled) 2462 return; 2463 while (1) { 2464 if (p->p_stat != SRUN) 2465 return; 2466 id = (u_char) p->p_oncpu; 2467 if (id == 0xff) 2468 return; 2469 map = (1<<id); 2470 checkstate_need_ast |= map; 2471 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2472 i = 0; 2473 while ((checkstate_need_ast & map) != 0) { 2474 /* spin */ 2475 i++; 2476 if (i > 100000) { 2477#if 0 2478 printf("forward_signal: dropped ast 0x%x\n", 2479 checkstate_need_ast & map); 2480#endif 2481 break; 2482 } 2483 } 2484 if (id == (u_char) p->p_oncpu) 2485 return; 2486 } 2487} 2488 2489void 2490forward_roundrobin(void) 2491{ 2492 u_int map; 2493 int i; 2494 2495 if (!smp_started || !invltlb_ok || cold || panicstr) 2496 return; 2497 if (!forward_roundrobin_enabled) 2498 return; 2499 resched_cpus |= other_cpus; 2500 map = other_cpus & ~stopped_cpus ; 2501#if 1 2502 selected_apic_ipi(map, XCPUAST_OFFSET, APIC_DELMODE_FIXED); 2503#else 2504 (void) all_but_self_ipi(XCPUAST_OFFSET); 2505#endif 2506 i = 0; 2507 while ((checkstate_need_ast & map) != 0) { 2508 /* spin */ 2509 i++; 2510 if (i > 100000) { 2511#if 0 2512 printf("forward_roundrobin: dropped ast 0x%x\n", 2513 checkstate_need_ast & map); 2514#endif 2515 break; 2516 } 2517 } 2518} 2519 2520 2521#ifdef APIC_INTR_REORDER 2522/* 2523 * Maintain mapping from softintr vector to isr bit in local apic. 2524 */ 2525void 2526set_lapic_isrloc(int intr, int vector) 2527{ 2528 if (intr < 0 || intr > 32) 2529 panic("set_apic_isrloc: bad intr argument: %d",intr); 2530 if (vector < ICU_OFFSET || vector > 255) 2531 panic("set_apic_isrloc: bad vector argument: %d",vector); 2532 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2533 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2534} 2535#endif 2536