mp_machdep.c revision 27489
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#include <sys/param.h> /* for KERNBASE */ 31#include <sys/types.h> 32#include <sys/sysproto.h> 33#include <sys/time.h> 34#include <sys/systm.h> 35 36#include <vm/vm.h> /* for KERNBASE */ 37#include <vm/vm_param.h> /* for KERNBASE */ 38#include <vm/pmap.h> /* for KERNBASE */ 39#include <machine/pmap.h> /* for KERNBASE */ 40#include <vm/vm_kern.h> 41#include <vm/vm_extern.h> 42 43#include <machine/smp.h> 44#include <machine/apic.h> 45#include <machine/mpapic.h> 46#include <machine/cpufunc.h> 47#include <machine/segments.h> 48#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ 49#include <machine/tss.h> 50#include <machine/specialreg.h> 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <machine/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* IPIs */ 57#include <i386/isa/intr_machdep.h> /* IPIs */ 58#endif /* APIC_IO */ 59 60#define WARMBOOT_TARGET 0 61#define WARMBOOT_OFF (KERNBASE + 0x0467) 62#define WARMBOOT_SEG (KERNBASE + 0x0469) 63 64#define BIOS_BASE (0xf0000) 65#define BIOS_SIZE (0x10000) 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68#define CMOS_REG (0x70) 69#define CMOS_DATA (0x71) 70#define BIOS_RESET (0x0f) 71#define BIOS_WARM (0x0a) 72 73#define PROCENTRY_FLAG_EN 0x01 74#define PROCENTRY_FLAG_BP 0x02 75#define IOAPICENTRY_FLAG_EN 0x01 76 77 78/* MP Floating Pointer Structure */ 79typedef struct MPFPS { 80 char signature[4]; 81 void *pap; 82 u_char length; 83 u_char spec_rev; 84 u_char checksum; 85 u_char mpfb1; 86 u_char mpfb2; 87 u_char mpfb3; 88 u_char mpfb4; 89 u_char mpfb5; 90} *mpfps_t; 91 92/* MP Configuration Table Header */ 93typedef struct MPCTH { 94 char signature[4]; 95 u_short base_table_length; 96 u_char spec_rev; 97 u_char checksum; 98 u_char oem_id[8]; 99 u_char product_id[12]; 100 void *oem_table_pointer; 101 u_short oem_table_size; 102 u_short entry_count; 103 void *apic_address; 104 u_short extended_table_length; 105 u_char extended_table_checksum; 106 u_char reserved; 107} *mpcth_t; 108 109 110typedef struct PROCENTRY { 111 u_char type; 112 u_char apic_id; 113 u_char apic_version; 114 u_char cpu_flags; 115 u_long cpu_signature; 116 u_long feature_flags; 117 u_long reserved1; 118 u_long reserved2; 119} *proc_entry_ptr; 120 121typedef struct BUSENTRY { 122 u_char type; 123 u_char bus_id; 124 char bus_type[6]; 125} *bus_entry_ptr; 126 127typedef struct IOAPICENTRY { 128 u_char type; 129 u_char apic_id; 130 u_char apic_version; 131 u_char apic_flags; 132 void *apic_address; 133} *io_apic_entry_ptr; 134 135typedef struct INTENTRY { 136 u_char type; 137 u_char int_type; 138 u_short int_flags; 139 u_char src_bus_id; 140 u_char src_bus_irq; 141 u_char dst_apic_id; 142 u_char dst_apic_int; 143} *int_entry_ptr; 144 145/* descriptions of MP basetable entries */ 146typedef struct BASETABLE_ENTRY { 147 u_char type; 148 u_char length; 149 char name[16]; 150} basetable_entry; 151 152/* 153 * this code MUST be enabled here and in mpboot.s. 154 * it follows the very early stages of AP boot by placing values in CMOS ram. 155 * it NORMALLY will never be needed and thus the primitive method for enabling. 156 * 157#define CHECK_POINTS 158 */ 159 160#if defined(CHECK_POINTS) 161#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 162#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 163 164#define CHECK_INIT(D); \ 165 CHECK_WRITE(0x34, (D)); \ 166 CHECK_WRITE(0x35, (D)); \ 167 CHECK_WRITE(0x36, (D)); \ 168 CHECK_WRITE(0x37, (D)); \ 169 CHECK_WRITE(0x38, (D)); \ 170 CHECK_WRITE(0x39, (D)); 171 172#define CHECK_PRINT(S); \ 173 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 174 (S), \ 175 CHECK_READ(0x34), \ 176 CHECK_READ(0x35), \ 177 CHECK_READ(0x36), \ 178 CHECK_READ(0x37), \ 179 CHECK_READ(0x38), \ 180 CHECK_READ(0x39)); 181 182#else /* CHECK_POINTS */ 183 184#define CHECK_INIT(D) 185#define CHECK_PRINT(S) 186 187#endif /* CHECK_POINTS */ 188 189/* 190 * Values to send to the POST hardware. 191 */ 192#define MP_BOOTADDRESS_POST 0x10 193#define MP_PROBE_POST 0x11 194#define MP_START_POST 0x12 195#define MP_ANNOUNCE_POST 0x13 196#define MPTABLE_PASS1_POST 0x14 197#define MPTABLE_PASS2_POST 0x15 198#define MP_ENABLE_POST 0x16 199#define START_ALL_APS_POST 0x17 200#define INSTALL_AP_TRAMP_POST 0x18 201#define START_AP_POST 0x19 202 203/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 204int current_postcode; 205 206/** XXX FIXME: what system files declare these??? */ 207extern struct region_descriptor r_gdt, r_idt; 208 209int mp_ncpus; /* # of CPUs, including BSP */ 210int mp_naps; /* # of Applications processors */ 211int mp_nbusses; /* # of busses */ 212int mp_napics; /* # of IO APICs */ 213int boot_cpu_id; /* designated BSP */ 214vm_offset_t cpu_apic_address; 215vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 216 217u_int32_t cpu_apic_versions[NCPU]; 218u_int32_t io_apic_versions[NAPIC]; 219 220/* 221 * APIC ID logical/physical mapping structures. 222 * We oversize these to simplify boot-time config. 223 */ 224int cpu_num_to_apic_id[NAPICID]; 225int io_num_to_apic_id[NAPICID]; 226int apic_id_to_logical[NAPICID]; 227 228/* Bitmap of all available CPUs */ 229u_int all_cpus; 230 231/* Boot of AP uses this PTD */ 232u_int *bootPTD; 233 234/* Hotwire a 0->4MB V==P mapping */ 235extern pt_entry_t KPTphys; 236 237/* Virtual address of per-cpu common_tss */ 238extern struct i386tss common_tss; 239 240/* 241 * Local data and functions. 242 */ 243 244static int mp_capable; 245static u_int boot_address; 246static u_int base_memory; 247 248static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 249static mpfps_t mpfps; 250static int search_for_sig(u_int32_t target, int count); 251static void mp_enable(u_int boot_addr); 252 253static int mptable_pass1(void); 254static int mptable_pass2(void); 255static void default_mp_table(int type); 256static int start_all_aps(u_int boot_addr); 257static void install_ap_tramp(u_int boot_addr); 258static int start_ap(int logicalCpu, u_int boot_addr); 259 260 261/* 262 * Calculate usable address in base memory for AP trampoline code. 263 */ 264u_int 265mp_bootaddress(u_int basemem) 266{ 267 POSTCODE(MP_BOOTADDRESS_POST); 268 269 base_memory = basemem * 1024; /* convert to bytes */ 270 271 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 272 if ((base_memory - boot_address) < bootMP_size) 273 boot_address -= 4096; /* not enough, lower by 4k */ 274 275 return boot_address; 276} 277 278 279/* 280 * Look for an Intel MP spec table (ie, SMP capable hardware). 281 */ 282int 283mp_probe(void) 284{ 285 int x; 286 u_long segment; 287 u_int32_t target; 288 289 POSTCODE(MP_PROBE_POST); 290 291 /* see if EBDA exists */ 292 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 293 /* search first 1K of EBDA */ 294 target = (u_int32_t) (segment << 4); 295 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 296 goto found; 297 } else { 298 /* last 1K of base memory, effective 'top of base' passed in */ 299 target = (u_int32_t) (base_memory - 0x400); 300 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 301 goto found; 302 } 303 304 /* search the BIOS */ 305 target = (u_int32_t) BIOS_BASE; 306 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 307 goto found; 308 309 /* nothing found */ 310 mpfps = (mpfps_t)0; 311 mp_capable = 0; 312 return 0; 313 314found: 315 /* calculate needed resources */ 316 mpfps = (mpfps_t)x; 317 if (mptable_pass1()) 318 panic("you must reconfigure your kernel"); 319 320 /* flag fact that we are running multiple processors */ 321 mp_capable = 1; 322 return 1; 323} 324 325 326/* 327 * Startup the SMP processors. 328 */ 329void 330mp_start(void) 331{ 332 POSTCODE(MP_START_POST); 333 334 /* look for MP capable motherboard */ 335 if (mp_capable) 336 mp_enable(boot_address); 337 else 338 panic("MP hardware not found!"); 339} 340 341 342/* 343 * Print various information about the SMP system hardware and setup. 344 */ 345void 346mp_announce(void) 347{ 348 int x; 349 350 POSTCODE(MP_ANNOUNCE_POST); 351 352 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 353 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 354 printf(", version: 0x%08x", cpu_apic_versions[0]); 355 printf(", at 0x%08x\n", cpu_apic_address); 356 for (x = 1; x <= mp_naps; ++x) { 357 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 358 printf(", version: 0x%08x", cpu_apic_versions[x]); 359 printf(", at 0x%08x\n", cpu_apic_address); 360 } 361 362#if defined(APIC_IO) 363 for (x = 0; x < mp_napics; ++x) { 364 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 365 printf(", version: 0x%08x", io_apic_versions[x]); 366 printf(", at 0x%08x\n", io_apic_address[x]); 367 } 368#else 369 printf(" Warning: APIC I/O disabled\n"); 370#endif /* APIC_IO */ 371} 372 373/* 374 * AP cpu's call this to sync up protected mode. 375 */ 376void 377init_secondary(void) 378{ 379 int gsel_tss, slot; 380 381 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 382 r_gdt.rd_base = (int) gdt; 383 lgdt(&r_gdt); /* does magic intra-segment return */ 384 lidt(&r_idt); 385 lldt(_default_ldt); 386 387 slot = NGDT + cpuid; 388 gsel_tss = GSEL(slot, SEL_KPL); 389 gdt[slot].sd.sd_type = SDT_SYS386TSS; 390 common_tss.tss_esp0 = 0; /* not used until after switch */ 391 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 392 common_tss.tss_ioopt = (sizeof common_tss) << 16; 393 ltr(gsel_tss); 394 395 load_cr0(0x8005003b); /* XXX! */ 396 397 PTD[0] = 0; 398 pmap_set_opt((unsigned *)PTD); 399 400 invltlb(); 401} 402 403 404#if defined(APIC_IO) 405/* 406 * Final configuration of the BSP's local APIC: 407 * - disable 'pic mode'. 408 * - disable 'virtual wire mode'. 409 * - enable NMI. 410 */ 411void 412bsp_apic_configure(void) 413{ 414 u_char byte; 415 u_int32_t temp; 416 417 /* leave 'pic mode' if necessary */ 418 if (picmode) { 419 outb(0x22, 0x70); /* select IMCR */ 420 byte = inb(0x23); /* current contents */ 421 byte |= 0x01; /* mask external INTR */ 422 outb(0x23, byte); /* disconnect 8259s/NMI */ 423 } 424 425 /* mask lint0 (the 8259 'virtual wire' connection) */ 426 temp = lapic.lvt_lint0; 427 temp |= APIC_LVT_M; /* set the mask */ 428 lapic.lvt_lint0 = temp; 429 430 /* setup lint1 to handle NMI */ 431 temp = lapic.lvt_lint1; 432 temp &= ~APIC_LVT_M; /* clear the mask */ 433 lapic.lvt_lint1 = temp; 434 435 if (bootverbose) 436 apic_dump(); 437} 438#endif /* APIC_IO */ 439 440 441/******************************************************************* 442 * local functions and data 443 */ 444 445/* 446 * start the SMP system 447 */ 448static void 449mp_enable(u_int boot_addr) 450{ 451 int x; 452#if defined(APIC_IO) 453 int apic; 454 u_int ux; 455#endif /* APIC_IO */ 456 457 POSTCODE(MP_ENABLE_POST); 458 459 /* turn on 4MB of V == P addressing so we can get to MP table */ 460 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 461 invltlb(); 462 463 /* examine the MP table for needed info, uses physical addresses */ 464 x = mptable_pass2(); 465 466 *(int *)PTD = 0; 467 invltlb(); 468 469 /* can't process default configs till the CPU APIC is pmapped */ 470 if (x) 471 default_mp_table(x); 472 473#if defined(APIC_IO) 474 475 /* fill the LOGICAL io_apic_versions table */ 476 for (apic = 0; apic < mp_napics; ++apic) { 477 ux = io_apic_read(apic, IOAPIC_VER); 478 io_apic_versions[apic] = ux; 479 } 480 481 /* program each IO APIC in the system */ 482 for (apic = 0; apic < mp_napics; ++apic) 483 if (io_apic_setup(apic) < 0) 484 panic("IO APIC setup failure"); 485 486 /* install a 'Spurious INTerrupt' vector */ 487 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 488 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 489 490 /* install an inter-CPU IPI for TLB invalidation */ 491 setidt(XINVLTLB_OFFSET, Xinvltlb, 492 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 493 494#if defined(TEST_CPUSTOP) 495 /* install an inter-CPU IPI for CPU stop/restart */ 496 setidt(XCPUSTOP_OFFSET, Xcpustop, 497 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 498#endif /** TEST_CPUSTOP */ 499 500#if defined(TEST_TEST1) 501 /* install a 'Spurious INTerrupt' vector */ 502 setidt(XTEST1_OFFSET, Xtest1, 503 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 504#endif /** TEST_TEST1 */ 505 506#endif /* APIC_IO */ 507 508 /* start each Application Processor */ 509 start_all_aps(boot_addr); 510 511 /* 512 * The init process might be started on a different CPU now, 513 * and the boot CPU might not call prepare_usermode to get 514 * cr0 correctly configured. Thus we initialize cr0 here. 515 */ 516 load_cr0(rcr0() | CR0_WP | CR0_AM); 517} 518 519 520/* 521 * look for the MP spec signature 522 */ 523 524/* string defined by the Intel MP Spec as identifying the MP table */ 525#define MP_SIG 0x5f504d5f /* _MP_ */ 526#define NEXT(X) ((X) += 4) 527static int 528search_for_sig(u_int32_t target, int count) 529{ 530 int x; 531 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 532 533 for (x = 0; x < count; NEXT(x)) 534 if (addr[x] == MP_SIG) 535 /* make array index a byte index */ 536 return (target + (x * sizeof(u_int32_t))); 537 538 return -1; 539} 540 541 542static basetable_entry basetable_entry_types[] = 543{ 544 {0, 20, "Processor"}, 545 {1, 8, "Bus"}, 546 {2, 8, "I/O APIC"}, 547 {3, 8, "I/O INT"}, 548 {4, 8, "Local INT"} 549}; 550 551typedef struct BUSDATA { 552 u_char bus_id; 553 enum busTypes bus_type; 554} bus_datum; 555 556typedef struct INTDATA { 557 u_char int_type; 558 u_short int_flags; 559 u_char src_bus_id; 560 u_char src_bus_irq; 561 u_char dst_apic_id; 562 u_char dst_apic_int; 563} io_int, local_int; 564 565typedef struct BUSTYPENAME { 566 u_char type; 567 char name[7]; 568} bus_type_name; 569 570static bus_type_name bus_type_table[] = 571{ 572 {CBUS, "CBUS"}, 573 {CBUSII, "CBUSII"}, 574 {EISA, "EISA"}, 575 {UNKNOWN_BUSTYPE, "---"}, 576 {UNKNOWN_BUSTYPE, "---"}, 577 {ISA, "ISA"}, 578 {UNKNOWN_BUSTYPE, "---"}, 579 {UNKNOWN_BUSTYPE, "---"}, 580 {UNKNOWN_BUSTYPE, "---"}, 581 {UNKNOWN_BUSTYPE, "---"}, 582 {UNKNOWN_BUSTYPE, "---"}, 583 {UNKNOWN_BUSTYPE, "---"}, 584 {PCI, "PCI"}, 585 {UNKNOWN_BUSTYPE, "---"}, 586 {UNKNOWN_BUSTYPE, "---"}, 587 {UNKNOWN_BUSTYPE, "---"}, 588 {UNKNOWN_BUSTYPE, "---"}, 589 {XPRESS, "XPRESS"}, 590 {UNKNOWN_BUSTYPE, "---"} 591}; 592/* from MP spec v1.4, table 5-1 */ 593static int default_data[7][5] = 594{ 595/* nbus, id0, type0, id1, type1 */ 596 {1, 0, ISA, 255, 255}, 597 {1, 0, EISA, 255, 255}, 598 {1, 0, EISA, 255, 255}, 599 {0, 255, 255, 255, 255},/* MCA not supported */ 600 {2, 0, ISA, 1, PCI}, 601 {2, 0, EISA, 1, PCI}, 602 {0, 255, 255, 255, 255} /* MCA not supported */ 603}; 604 605 606/* the bus data */ 607bus_datum bus_data[NBUS]; 608 609/* the IO INT data, one entry per possible APIC INTerrupt */ 610io_int io_apic_ints[NINTR]; 611 612static int nintrs; 613 614static void fix_mp_table __P((void)); 615static int processor_entry __P((proc_entry_ptr entry, int cpu)); 616static int bus_entry __P((bus_entry_ptr entry, int bus)); 617static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 618static int int_entry __P((int_entry_ptr entry, int intr)); 619static int lookup_bus_type __P((char *name)); 620 621 622/* 623 * 1st pass on motherboard's Intel MP specification table. 624 * 625 * initializes: 626 * mp_ncpus = 1 627 * 628 * determines: 629 * cpu_apic_address (common to all CPUs) 630 * io_apic_address[N] 631 * mp_naps 632 * mp_nbusses 633 * mp_napics 634 * nintrs 635 */ 636static int 637mptable_pass1(void) 638{ 639 int x; 640 mpcth_t cth; 641 int totalSize; 642 void* position; 643 int count; 644 int type; 645 int mustpanic; 646 647 POSTCODE(MPTABLE_PASS1_POST); 648 649 mustpanic = 0; 650 651 /* clear various tables */ 652 for (x = 0; x < NAPICID; ++x) { 653 io_apic_address[x] = ~0; /* IO APIC address table */ 654 } 655 656 /* init everything to empty */ 657 mp_naps = 0; 658 mp_nbusses = 0; 659 mp_napics = 0; 660 nintrs = 0; 661 662 /* check for use of 'default' configuration */ 663 if (mpfps->mpfb1 != 0) { 664 /* use default addresses */ 665 cpu_apic_address = DEFAULT_APIC_BASE; 666 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 667 668 /* fill in with defaults */ 669 mp_naps = 2; /* includes BSP */ 670 mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; 671#if defined(APIC_IO) 672 mp_napics = 1; 673 nintrs = 16; 674#endif /* APIC_IO */ 675 } 676 else { 677 if ((cth = mpfps->pap) == 0) 678 panic("MP Configuration Table Header MISSING!"); 679 680 cpu_apic_address = (vm_offset_t) cth->apic_address; 681 682 /* walk the table, recording info of interest */ 683 totalSize = cth->base_table_length - sizeof(struct MPCTH); 684 position = (u_char *) cth + sizeof(struct MPCTH); 685 count = cth->entry_count; 686 687 while (count--) { 688 switch (type = *(u_char *) position) { 689 case 0: /* processor_entry */ 690 if (((proc_entry_ptr)position)->cpu_flags 691 & PROCENTRY_FLAG_EN) 692 ++mp_naps; 693 break; 694 case 1: /* bus_entry */ 695 ++mp_nbusses; 696 break; 697 case 2: /* io_apic_entry */ 698 if (((io_apic_entry_ptr)position)->apic_flags 699 & IOAPICENTRY_FLAG_EN) 700 io_apic_address[mp_napics++] = 701 (vm_offset_t)((io_apic_entry_ptr) 702 position)->apic_address; 703 break; 704 case 3: /* int_entry */ 705 ++nintrs; 706 break; 707 case 4: /* int_entry */ 708 break; 709 default: 710 panic("mpfps Base Table HOSED!"); 711 /* NOTREACHED */ 712 } 713 714 totalSize -= basetable_entry_types[type].length; 715 (u_char*)position += basetable_entry_types[type].length; 716 } 717 } 718 719 /* qualify the numbers */ 720 if (mp_naps > NCPU) 721 printf("Warning: only using %d of %d available CPUs!\n", 722 NCPU, mp_naps); 723#if 0 724 /** XXX we consider this legal now (but should we?) */ 725 mustpanic = 1; 726#endif 727 if (mp_nbusses > NBUS) { 728 printf("found %d busses, increase NBUS\n", mp_nbusses); 729 mustpanic = 1; 730 } 731 if (mp_napics > NAPIC) { 732 printf("found %d apics, increase NAPIC\n", mp_napics); 733 mustpanic = 1; 734 } 735 if (nintrs > NINTR) { 736 printf("found %d intrs, increase NINTR\n", nintrs); 737 mustpanic = 1; 738 } 739 740 /* 741 * Count the BSP. 742 * This is also used as a counter while starting the APs. 743 */ 744 mp_ncpus = 1; 745 746 --mp_naps; /* subtract the BSP */ 747 748 return mustpanic; 749} 750 751 752/* 753 * 2nd pass on motherboard's Intel MP specification table. 754 * 755 * sets: 756 * boot_cpu_id 757 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 758 * CPU_TO_ID(N), logical CPU to APIC ID table 759 * IO_TO_ID(N), logical IO to APIC ID table 760 * bus_data[N] 761 * io_apic_ints[N] 762 */ 763static int 764mptable_pass2(void) 765{ 766 int x; 767 mpcth_t cth; 768 int totalSize; 769 void* position; 770 int count; 771 int type; 772 int apic, bus, cpu, intr; 773 774 POSTCODE(MPTABLE_PASS2_POST); 775 776 /* clear various tables */ 777 for (x = 0; x < NAPICID; ++x) { 778 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 779 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 780 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 781 } 782 783 /* clear bus data table */ 784 for (x = 0; x < NBUS; ++x) 785 bus_data[x].bus_id = 0xff; 786 787 /* clear IO APIC INT table */ 788 for (x = 0; x < NINTR; ++x) 789 io_apic_ints[x].int_type = 0xff; 790 791 /* setup the cpu/apic mapping arrays */ 792 boot_cpu_id = -1; 793 794 /* record whether PIC or virtual-wire mode */ 795 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 796 797 /* check for use of 'default' configuration */ 798#if defined(TEST_DEFAULT_CONFIG) 799 return TEST_DEFAULT_CONFIG; 800#else 801 if (mpfps->mpfb1 != 0) 802 return mpfps->mpfb1; /* return default configuration type */ 803#endif /* TEST_DEFAULT_CONFIG */ 804 805 if ((cth = mpfps->pap) == 0) 806 panic("MP Configuration Table Header MISSING!"); 807 808 /* walk the table, recording info of interest */ 809 totalSize = cth->base_table_length - sizeof(struct MPCTH); 810 position = (u_char *) cth + sizeof(struct MPCTH); 811 count = cth->entry_count; 812 apic = bus = intr = 0; 813 cpu = 1; /* pre-count the BSP */ 814 815 while (count--) { 816 switch (type = *(u_char *) position) { 817 case 0: 818 if (processor_entry(position, cpu)) 819 ++cpu; 820 break; 821 case 1: 822 if (bus_entry(position, bus)) 823 ++bus; 824 break; 825 case 2: 826 if (io_apic_entry(position, apic)) 827 ++apic; 828 break; 829 case 3: 830 if (int_entry(position, intr)) 831 ++intr; 832 break; 833 case 4: 834 /* int_entry(position); */ 835 break; 836 default: 837 panic("mpfps Base Table HOSED!"); 838 /* NOTREACHED */ 839 } 840 841 totalSize -= basetable_entry_types[type].length; 842 (u_char *) position += basetable_entry_types[type].length; 843 } 844 845 if (boot_cpu_id == -1) 846 panic("NO BSP found!"); 847 848 /* post scan cleanup */ 849 fix_mp_table(); 850 851 /* report fact that its NOT a default configuration */ 852 return 0; 853} 854 855 856/* 857 * parse an Intel MP specification table 858 */ 859static void 860fix_mp_table(void) 861{ 862 int x; 863 int id; 864 int bus_0; 865 int bus_pci; 866 int num_pci_bus; 867 868 /* 869 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 870 * did it wrong. The MP spec says that when more than 1 PCI bus 871 * exists the BIOS must begin with bus entries for the PCI bus and use 872 * actual PCI bus numbering. This implies that when only 1 PCI bus 873 * exists the BIOS can choose to ignore this ordering, and indeed many 874 * MP motherboards do ignore it. This causes a problem when the PCI 875 * sub-system makes requests of the MP sub-system based on PCI bus 876 * numbers. So here we look for the situation and renumber the 877 * busses and associated INTs in an effort to "make it right". 878 */ 879 880 /* find bus 0, PCI bus, count the number of PCI busses */ 881 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 882 if (bus_data[x].bus_id == 0) { 883 bus_0 = x; 884 } 885 if (bus_data[x].bus_type == PCI) { 886 ++num_pci_bus; 887 bus_pci = x; 888 } 889 } 890 /* 891 * bus_0 == slot of bus with ID of 0 892 * bus_pci == slot of last PCI bus encountered 893 */ 894 895 /* check the 1 PCI bus case for sanity */ 896 if (num_pci_bus == 1) { 897 898 /* if it is number 0 all is well */ 899 if (bus_data[bus_pci].bus_id == 0) 900 return; 901 902 /* mis-numbered, swap with whichever bus uses slot 0 */ 903 904 /* swap the bus entry types */ 905 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 906 bus_data[bus_0].bus_type = PCI; 907 908 /* swap each relavant INTerrupt entry */ 909 id = bus_data[bus_pci].bus_id; 910 for (x = 0; x < nintrs; ++x) { 911 if (io_apic_ints[x].src_bus_id == id) { 912 io_apic_ints[x].src_bus_id = 0; 913 } 914 else if (io_apic_ints[x].src_bus_id == 0) { 915 io_apic_ints[x].src_bus_id = id; 916 } 917 } 918 } 919 /* sanity check if more than 1 PCI bus */ 920 else if (num_pci_bus > 1) { 921 for (x = 0; x < mp_nbusses; ++x) { 922 if (bus_data[x].bus_type != PCI) 923 continue; 924 if (bus_data[x].bus_id >= num_pci_bus) 925 panic("bad PCI bus numbering"); 926 } 927 } 928} 929 930 931static int 932processor_entry(proc_entry_ptr entry, int cpu) 933{ 934 /* check for usability */ 935 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 936 return 0; 937 938 /* check for BSP flag */ 939 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 940 boot_cpu_id = entry->apic_id; 941 CPU_TO_ID(0) = entry->apic_id; 942 ID_TO_CPU(entry->apic_id) = 0; 943 return 0; /* its already been counted */ 944 } 945 946 /* add another AP to list, if less than max number of CPUs */ 947 else { 948 CPU_TO_ID(cpu) = entry->apic_id; 949 ID_TO_CPU(entry->apic_id) = cpu; 950 return 1; 951 } 952} 953 954 955static int 956bus_entry(bus_entry_ptr entry, int bus) 957{ 958 int x; 959 char c, name[8]; 960 961 /* encode the name into an index */ 962 for (x = 0; x < 6; ++x) { 963 if ((c = entry->bus_type[x]) == ' ') 964 break; 965 name[x] = c; 966 } 967 name[x] = '\0'; 968 969 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 970 panic("unknown bus type: '%s'", name); 971 972 bus_data[bus].bus_id = entry->bus_id; 973 bus_data[bus].bus_type = x; 974 975 return 1; 976} 977 978 979static int 980io_apic_entry(io_apic_entry_ptr entry, int apic) 981{ 982 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 983 return 0; 984 985 IO_TO_ID(apic) = entry->apic_id; 986 ID_TO_IO(entry->apic_id) = apic; 987 988 return 1; 989} 990 991 992static int 993lookup_bus_type(char *name) 994{ 995 int x; 996 997 for (x = 0; x < MAX_BUSTYPE; ++x) 998 if (strcmp(bus_type_table[x].name, name) == 0) 999 return bus_type_table[x].type; 1000 1001 return UNKNOWN_BUSTYPE; 1002} 1003 1004 1005static int 1006int_entry(int_entry_ptr entry, int intr) 1007{ 1008 io_apic_ints[intr].int_type = entry->int_type; 1009 io_apic_ints[intr].int_flags = entry->int_flags; 1010 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1011 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1012 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1013 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1014 1015 return 1; 1016} 1017 1018 1019static int 1020apic_int_is_bus_type(int intr, int bus_type) 1021{ 1022 int bus; 1023 1024 for (bus = 0; bus < mp_nbusses; ++bus) 1025 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1026 && ((int) bus_data[bus].bus_type == bus_type)) 1027 return 1; 1028 1029 return 0; 1030} 1031 1032 1033/* 1034 * Given a traditional ISA INT mask, return an APIC mask. 1035 */ 1036u_int 1037isa_apic_mask(u_int isa_mask) 1038{ 1039 int isa_irq; 1040 int apic_pin; 1041 1042#if defined(SKIP_IRQ15_REDIRECT) 1043 if (isa_mask == (1 << 15)) { 1044 printf("skipping ISA IRQ15 redirect\n"); 1045 return isa_mask; 1046 } 1047#endif /* SKIP_IRQ15_REDIRECT */ 1048 1049 isa_irq = ffs(isa_mask); /* find its bit position */ 1050 if (isa_irq == 0) /* doesn't exist */ 1051 return 0; 1052 --isa_irq; /* make it zero based */ 1053 1054 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1055 if (apic_pin == -1) 1056 return 0; 1057 1058 return (1 << apic_pin); /* convert pin# to a mask */ 1059} 1060 1061 1062/* 1063 * Determine which APIC pin an ISA/EISA INT is attached to. 1064 */ 1065#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1066#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1067 1068#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1069int 1070isa_apic_pin(int isa_irq) 1071{ 1072 int intr; 1073 1074#if defined(SMP_TIMER_NC) 1075 if (isa_irq == 0) 1076 return -1; 1077#endif /* SMP_TIMER_NC */ 1078 1079 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1080 if (INTTYPE(intr) == 0) { /* standard INT */ 1081 if (SRCBUSIRQ(intr) == isa_irq) { 1082 if (apic_int_is_bus_type(intr, ISA) || 1083 apic_int_is_bus_type(intr, EISA)) 1084 return INTPIN(intr); /* found */ 1085 } 1086 } 1087 } 1088 return -1; /* NOT found */ 1089} 1090#undef SRCBUSIRQ 1091 1092 1093/* 1094 * Determine which APIC pin a PCI INT is attached to. 1095 */ 1096#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1097#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1098#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1099int 1100pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1101{ 1102 int intr; 1103 1104 --pciInt; /* zero based */ 1105 1106 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1107 if ((INTTYPE(intr) == 0) /* standard INT */ 1108 && (SRCBUSID(intr) == pciBus) 1109 && (SRCBUSDEVICE(intr) == pciDevice) 1110 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1111 if (apic_int_is_bus_type(intr, PCI)) 1112 return INTPIN(intr); /* exact match */ 1113 1114 return -1; /* NOT found */ 1115} 1116#undef SRCBUSLINE 1117#undef SRCBUSDEVICE 1118#undef SRCBUSID 1119 1120#undef INTPIN 1121#undef INTTYPE 1122 1123 1124/* 1125 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1126 * 1127 * XXX FIXME: 1128 * Exactly what this means is unclear at this point. It is a solution 1129 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1130 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1131 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1132 * option. 1133 */ 1134int 1135undirect_isa_irq(int rirq) 1136{ 1137#if defined(READY) 1138 printf("Freeing redirected ISA irq %d.\n", rirq); 1139 /** FIXME: tickle the MB redirector chip */ 1140 return ???; 1141#else 1142 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1143 return 0; 1144#endif /* READY */ 1145} 1146 1147 1148/* 1149 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1150 */ 1151int 1152undirect_pci_irq(int rirq) 1153{ 1154#if defined(READY) 1155 if (bootverbose) 1156 printf("Freeing redirected PCI irq %d.\n", rirq); 1157 1158 /** FIXME: tickle the MB redirector chip */ 1159 return ???; 1160#else 1161 if (bootverbose) 1162 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1163 rirq); 1164 return 0; 1165#endif /* READY */ 1166} 1167 1168 1169/* 1170 * given a bus ID, return: 1171 * the bus type if found 1172 * -1 if NOT found 1173 */ 1174int 1175apic_bus_type(int id) 1176{ 1177 int x; 1178 1179 for (x = 0; x < mp_nbusses; ++x) 1180 if (bus_data[x].bus_id == id) 1181 return bus_data[x].bus_type; 1182 1183 return -1; 1184} 1185 1186 1187/* 1188 * given a LOGICAL APIC# and pin#, return: 1189 * the associated src bus ID if found 1190 * -1 if NOT found 1191 */ 1192int 1193apic_src_bus_id(int apic, int pin) 1194{ 1195 int x; 1196 1197 /* search each of the possible INTerrupt sources */ 1198 for (x = 0; x < nintrs; ++x) 1199 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1200 (pin == io_apic_ints[x].dst_apic_int)) 1201 return (io_apic_ints[x].src_bus_id); 1202 1203 return -1; /* NOT found */ 1204} 1205 1206 1207/* 1208 * given a LOGICAL APIC# and pin#, return: 1209 * the associated src bus IRQ if found 1210 * -1 if NOT found 1211 */ 1212int 1213apic_src_bus_irq(int apic, int pin) 1214{ 1215 int x; 1216 1217 for (x = 0; x < nintrs; x++) 1218 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1219 (pin == io_apic_ints[x].dst_apic_int)) 1220 return (io_apic_ints[x].src_bus_irq); 1221 1222 return -1; /* NOT found */ 1223} 1224 1225 1226/* 1227 * given a LOGICAL APIC# and pin#, return: 1228 * the associated INTerrupt type if found 1229 * -1 if NOT found 1230 */ 1231int 1232apic_int_type(int apic, int pin) 1233{ 1234 int x; 1235 1236 /* search each of the possible INTerrupt sources */ 1237 for (x = 0; x < nintrs; ++x) 1238 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1239 (pin == io_apic_ints[x].dst_apic_int)) 1240 return (io_apic_ints[x].int_type); 1241 1242 return -1; /* NOT found */ 1243} 1244 1245 1246/* 1247 * given a LOGICAL APIC# and pin#, return: 1248 * the associated trigger mode if found 1249 * -1 if NOT found 1250 */ 1251int 1252apic_trigger(int apic, int pin) 1253{ 1254 int x; 1255 1256 /* search each of the possible INTerrupt sources */ 1257 for (x = 0; x < nintrs; ++x) 1258 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1259 (pin == io_apic_ints[x].dst_apic_int)) 1260 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1261 1262 return -1; /* NOT found */ 1263} 1264 1265 1266/* 1267 * given a LOGICAL APIC# and pin#, return: 1268 * the associated 'active' level if found 1269 * -1 if NOT found 1270 */ 1271int 1272apic_polarity(int apic, int pin) 1273{ 1274 int x; 1275 1276 /* search each of the possible INTerrupt sources */ 1277 for (x = 0; x < nintrs; ++x) 1278 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1279 (pin == io_apic_ints[x].dst_apic_int)) 1280 return (io_apic_ints[x].int_flags & 0x03); 1281 1282 return -1; /* NOT found */ 1283} 1284 1285 1286/* 1287 * set data according to MP defaults 1288 * FIXME: probably not complete yet... 1289 */ 1290static void 1291default_mp_table(int type) 1292{ 1293 int ap_cpu_id; 1294#if defined(APIC_IO) 1295 u_int32_t ux; 1296 int io_apic_id; 1297 int pin; 1298#endif /* APIC_IO */ 1299 1300#if 0 1301 printf(" MP default config type: %d\n", type); 1302 switch (type) { 1303 case 1: 1304 printf(" bus: ISA, APIC: 82489DX\n"); 1305 break; 1306 case 2: 1307 printf(" bus: EISA, APIC: 82489DX\n"); 1308 break; 1309 case 3: 1310 printf(" bus: EISA, APIC: 82489DX\n"); 1311 break; 1312 case 4: 1313 printf(" bus: MCA, APIC: 82489DX\n"); 1314 break; 1315 case 5: 1316 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1317 break; 1318 case 6: 1319 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1320 break; 1321 case 7: 1322 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1323 break; 1324 default: 1325 printf(" future type\n"); 1326 break; 1327 /* NOTREACHED */ 1328 } 1329#endif /* 0 */ 1330 1331 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1332 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1333 1334 /* BSP */ 1335 CPU_TO_ID(0) = boot_cpu_id; 1336 ID_TO_CPU(boot_cpu_id) = 0; 1337 1338 /* one and only AP */ 1339 CPU_TO_ID(1) = ap_cpu_id; 1340 ID_TO_CPU(ap_cpu_id) = 1; 1341 1342#if defined(APIC_IO) 1343 /* one and only IO APIC */ 1344 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1345 1346 /* 1347 * sanity check, refer to MP spec section 3.6.6, last paragraph 1348 * necessary as some hardware isn't properly setting up the IO APIC 1349 */ 1350#if defined(REALLY_ANAL_IOAPICID_VALUE) 1351 if (io_apic_id != 2) { 1352#else 1353 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1354#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1355 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1356 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1357 ux |= 0x02000000; /* set it to '2' */ 1358 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1359 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1360 if ((ux & APIC_ID_MASK) != 0x02000000) 1361 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1362 io_apic_id = 2; 1363 } 1364 IO_TO_ID(0) = io_apic_id; 1365 ID_TO_IO(io_apic_id) = 0; 1366#endif /* APIC_IO */ 1367 1368 /* fill out bus entries */ 1369 switch (type) { 1370 case 1: 1371 case 2: 1372 case 3: 1373 case 5: 1374 case 6: 1375 bus_data[0].bus_id = default_data[type - 1][1]; 1376 bus_data[0].bus_type = default_data[type - 1][2]; 1377 bus_data[1].bus_id = default_data[type - 1][3]; 1378 bus_data[1].bus_type = default_data[type - 1][4]; 1379 break; 1380 1381 /* case 4: case 7: MCA NOT supported */ 1382 default: /* illegal/reserved */ 1383 panic("BAD default MP config: %d", type); 1384 /* NOTREACHED */ 1385 } 1386 1387#if defined(APIC_IO) 1388 /* general cases from MP v1.4, table 5-2 */ 1389 for (pin = 0; pin < 16; ++pin) { 1390 io_apic_ints[pin].int_type = 0; 1391 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1392 io_apic_ints[pin].src_bus_id = 0; 1393 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1394 io_apic_ints[pin].dst_apic_id = io_apic_id; 1395 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1396 } 1397 1398 /* special cases from MP v1.4, table 5-2 */ 1399 if (type == 2) { 1400 io_apic_ints[2].int_type = 0xff; /* N/C */ 1401 io_apic_ints[13].int_type = 0xff; /* N/C */ 1402#if !defined(APIC_MIXED_MODE) 1403 /** FIXME: ??? */ 1404 panic("sorry, can't support type 2 default yet"); 1405#endif /* APIC_MIXED_MODE */ 1406 } 1407 else 1408 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1409 1410 if (type == 7) 1411 io_apic_ints[0].int_type = 0xff; /* N/C */ 1412 else 1413 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1414#endif /* APIC_IO */ 1415} 1416 1417 1418/* 1419 * start each AP in our list 1420 */ 1421static int 1422start_all_aps(u_int boot_addr) 1423{ 1424 int x, i; 1425 u_char mpbiosreason; 1426 u_long mpbioswarmvec; 1427 pd_entry_t newptd; 1428 pt_entry_t newpt; 1429 int *newpp; 1430 1431 POSTCODE(START_ALL_APS_POST); 1432 1433 /** 1434 * NOTE: this needs further thought: 1435 * where does it get released? 1436 * should it be set to empy? 1437 * 1438 * get the initial mp_lock with a count of 1 for the BSP 1439 */ 1440 mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ 1441 1442 /* initialize BSP's local APIC */ 1443 apic_initialize(); 1444 1445 /* install the AP 1st level boot code */ 1446 install_ap_tramp(boot_addr); 1447 1448 1449 /* save the current value of the warm-start vector */ 1450 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1451 outb(CMOS_REG, BIOS_RESET); 1452 mpbiosreason = inb(CMOS_DATA); 1453 1454 /* record BSP in CPU map */ 1455 all_cpus = 1; 1456 1457 /* start each AP */ 1458 for (x = 1; x <= mp_naps; ++x) { 1459 1460 /* HACK HACK HACK !!! */ 1461 1462 /* alloc new page table directory */ 1463 newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1464 1465 /* clone currently active one (ie: IdlePTD) */ 1466 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1467 1468 /* set up 0 -> 4MB P==V mapping for AP boot */ 1469 newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 1470 1471 /* store PTD for this AP */ 1472 bootPTD = (pd_entry_t)vtophys(newptd); 1473 1474 /* alloc new page table page */ 1475 newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); 1476 1477 /* set the new PTD's private page to point there */ 1478 newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); 1479 1480 /* install self referential entry */ 1481 newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); 1482 1483 /* get a new private data page */ 1484 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1485 1486 /* wire it into the private page table page */ 1487 newpt[0] = PG_V | PG_RW | vtophys(newpp); 1488 1489 /* wire the ptp into itself for access */ 1490 newpt[1] = PG_V | PG_RW | vtophys(newpt); 1491 1492 /* and the local apic */ 1493 newpt[2] = SMP_prvpt[2]; 1494 1495 /* and the IO apic mapping[s] */ 1496 for (i = 16; i < 32; i++) 1497 newpt[i] = SMP_prvpt[i]; 1498 1499 /* prime data page for it to use */ 1500 newpp[0] = x; /* cpuid */ 1501 newpp[1] = 0; /* curproc */ 1502 newpp[2] = 0; /* curpcb */ 1503 newpp[3] = 0; /* npxproc */ 1504 newpp[4] = 0; /* runtime.tv_sec */ 1505 newpp[5] = 0; /* runtime.tv_usec */ 1506 newpp[6] = x << 24; /* cpu_lockid */ 1507 1508 /* XXX NOTE: ABANDON bootPTD for now!!!! */ 1509 1510 /* END REVOLTING HACKERY */ 1511 1512 /* setup a vector to our boot code */ 1513 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1514 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1515 outb(CMOS_REG, BIOS_RESET); 1516 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1517 1518 /* attempt to start the Application Processor */ 1519 CHECK_INIT(99); /* setup checkpoints */ 1520 if (!start_ap(x, boot_addr)) { 1521 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1522 CHECK_PRINT("trace"); /* show checkpoints */ 1523 /* better panic as the AP may be running loose */ 1524 printf("panic y/n? [y] "); 1525 if (cngetc() != 'n') 1526 panic("bye-bye"); 1527 } 1528 CHECK_PRINT("trace"); /* show checkpoints */ 1529 1530 /* record its version info */ 1531 cpu_apic_versions[x] = cpu_apic_versions[0]; 1532 1533 all_cpus |= (1 << x); /* record AP in CPU map */ 1534 } 1535 1536 /* build our map of 'other' CPUs */ 1537 other_cpus = all_cpus & ~(1 << cpuid); 1538 1539 /* fill in our (BSP) APIC version */ 1540 cpu_apic_versions[0] = lapic.version; 1541 1542 /* restore the warmstart vector */ 1543 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1544 outb(CMOS_REG, BIOS_RESET); 1545 outb(CMOS_DATA, mpbiosreason); 1546 1547 pmap_set_opt_bsp(); 1548 1549 /* number of APs actually started */ 1550 return mp_ncpus - 1; 1551} 1552 1553 1554/* 1555 * load the 1st level AP boot code into base memory. 1556 */ 1557 1558/* targets for relocation */ 1559extern void bigJump(void); 1560extern void bootCodeSeg(void); 1561extern void bootDataSeg(void); 1562extern void MPentry(void); 1563extern u_int MP_GDT; 1564extern u_int mp_gdtbase; 1565 1566static void 1567install_ap_tramp(u_int boot_addr) 1568{ 1569 int x; 1570 int size = *(int *) ((u_long) & bootMP_size); 1571 u_char *src = (u_char *) ((u_long) bootMP); 1572 u_char *dst = (u_char *) boot_addr + KERNBASE; 1573 u_int boot_base = (u_int) bootMP; 1574 u_int8_t *dst8; 1575 u_int16_t *dst16; 1576 u_int32_t *dst32; 1577 1578 POSTCODE(INSTALL_AP_TRAMP_POST); 1579 1580 for (x = 0; x < size; ++x) 1581 *dst++ = *src++; 1582 1583 /* 1584 * modify addresses in code we just moved to basemem. unfortunately we 1585 * need fairly detailed info about mpboot.s for this to work. changes 1586 * to mpboot.s might require changes here. 1587 */ 1588 1589 /* boot code is located in KERNEL space */ 1590 dst = (u_char *) boot_addr + KERNBASE; 1591 1592 /* modify the lgdt arg */ 1593 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1594 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1595 1596 /* modify the ljmp target for MPentry() */ 1597 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1598 *dst32 = ((u_int) MPentry - KERNBASE); 1599 1600 /* modify the target for boot code segment */ 1601 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1602 dst8 = (u_int8_t *) (dst16 + 1); 1603 *dst16 = (u_int) boot_addr & 0xffff; 1604 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1605 1606 /* modify the target for boot data segment */ 1607 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1608 dst8 = (u_int8_t *) (dst16 + 1); 1609 *dst16 = (u_int) boot_addr & 0xffff; 1610 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1611} 1612 1613 1614/* 1615 * this function starts the AP (application processor) identified 1616 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1617 * to accomplish this. This is necessary because of the nuances 1618 * of the different hardware we might encounter. It ain't pretty, 1619 * but it seems to work. 1620 */ 1621static int 1622start_ap(int logical_cpu, u_int boot_addr) 1623{ 1624 int physical_cpu; 1625 int vector; 1626 int cpus; 1627 u_long icr_lo, icr_hi; 1628 1629 POSTCODE(START_AP_POST); 1630 1631 /* get the PHYSICAL APIC ID# */ 1632 physical_cpu = CPU_TO_ID(logical_cpu); 1633 1634 /* calculate the vector */ 1635 vector = (boot_addr >> 12) & 0xff; 1636 1637 /* used as a watchpoint to signal AP startup */ 1638 cpus = mp_ncpus; 1639 1640 /* 1641 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1642 * and running the target CPU. OR this INIT IPI might be latched (P5 1643 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1644 * ignored. 1645 */ 1646 1647 /* setup the address for the target AP */ 1648 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1649 icr_hi |= (physical_cpu << 24); 1650 lapic.icr_hi = icr_hi; 1651 1652 /* do an INIT IPI: assert RESET */ 1653 icr_lo = lapic.icr_lo & 0xfff00000; 1654 lapic.icr_lo = icr_lo | 0x0000c500; 1655 1656 /* wait for pending status end */ 1657 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1658 /* spin */ ; 1659 1660 /* do an INIT IPI: deassert RESET */ 1661 lapic.icr_lo = icr_lo | 0x00008500; 1662 1663 /* wait for pending status end */ 1664 u_sleep(10000); /* wait ~10mS */ 1665 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1666 /* spin */ ; 1667 1668 /* 1669 * next we do a STARTUP IPI: the previous INIT IPI might still be 1670 * latched, (P5 bug) this 1st STARTUP would then terminate 1671 * immediately, and the previously started INIT IPI would continue. OR 1672 * the previous INIT IPI has already run. and this STARTUP IPI will 1673 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1674 * will run. 1675 */ 1676 1677 /* do a STARTUP IPI */ 1678 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1679 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1680 /* spin */ ; 1681 u_sleep(200); /* wait ~200uS */ 1682 1683 /* 1684 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1685 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1686 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1687 * recognized after hardware RESET or INIT IPI. 1688 */ 1689 1690 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1691 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1692 /* spin */ ; 1693 u_sleep(200); /* wait ~200uS */ 1694 1695 /* wait for it to start */ 1696 set_apic_timer(5000000);/* == 5 seconds */ 1697 while (read_apic_timer()) 1698 if (mp_ncpus > cpus) 1699 return 1; /* return SUCCESS */ 1700 1701 return 0; /* return FAILURE */ 1702} 1703 1704 1705/* 1706 * Flush the TLB on all other CPU's 1707 * 1708 * XXX: Needs to handshake and wait for completion before proceding. 1709 */ 1710void 1711smp_invltlb(void) 1712{ 1713#if defined(APIC_IO) 1714 if (smp_active && invltlb_ok) 1715 all_but_self_ipi(XINVLTLB_OFFSET); 1716#endif /* APIC_IO */ 1717} 1718 1719void 1720invlpg(u_int addr) 1721{ 1722 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1723 1724 /* send a message to the other CPUs */ 1725 smp_invltlb(); 1726} 1727 1728void 1729invltlb(void) 1730{ 1731 u_long temp; 1732 1733 /* 1734 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1735 * inlined. 1736 */ 1737 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1738 1739 /* send a message to the other CPUs */ 1740 smp_invltlb(); 1741} 1742 1743 1744#if defined(TEST_CPUSTOP) 1745 1746#if defined(DEBUG_CPUSTOP) 1747void db_printf __P((const char *fmt, ...)); 1748#endif /* DEBUG_CPUSTOP */ 1749 1750/* 1751 * When called the executing CPU will send an IPI to all other CPUs 1752 * requesting that they halt execution. 1753 * 1754 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1755 * 1756 * - Signals all CPUs in map to stop. 1757 * - Waits for each to stop. 1758 * 1759 * Returns: 1760 * -1: error 1761 * 0: NA 1762 * 1: ok 1763 * 1764 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1765 * from executing at same time. 1766 */ 1767int 1768stop_cpus( u_int map ) 1769{ 1770 if (!smp_active) 1771 return 0; 1772 1773 /* send IPI to all CPUs in map */ 1774#if defined(DEBUG_CPUSTOP) 1775 db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); 1776#endif /* DEBUG_CPUSTOP */ 1777 1778 stopped_cpus = 0; 1779 1780 /* send the Xcpustop IPI to all CPUs in map */ 1781 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1782 1783#if defined(DEBUG_CPUSTOP) 1784 db_printf(" spin\n"); 1785#endif /* DEBUG_CPUSTOP */ 1786 1787 while (stopped_cpus != map) 1788 /* spin */ ; 1789 1790#if defined(DEBUG_CPUSTOP) 1791 db_printf(" spun\nstopped\n"); 1792#endif /* DEBUG_CPUSTOP */ 1793 1794 return 1; 1795} 1796 1797 1798/* 1799 * Called by a CPU to restart stopped CPUs. 1800 * 1801 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1802 * 1803 * - Signals all CPUs in map to restart. 1804 * - Waits for each to restart. 1805 * 1806 * Returns: 1807 * -1: error 1808 * 0: NA 1809 * 1: ok 1810 */ 1811int 1812restart_cpus( u_int map ) 1813{ 1814 if (!smp_active) 1815 return 0; 1816 1817#if defined(DEBUG_CPUSTOP) 1818 db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", 1819 cpuid, map, stopped_cpus); 1820#endif /* DEBUG_CPUSTOP */ 1821 1822 started_cpus = map; /* signal other cpus to restart */ 1823 1824 while (started_cpus) /* wait for each to clear its bit */ 1825 /* spin */ ; 1826 1827#if defined(DEBUG_CPUSTOP) 1828 db_printf(" restarted\n"); 1829#endif /* DEBUG_CPUSTOP */ 1830 1831 return 1; 1832} 1833 1834#endif /** TEST_CPUSTOP */ 1835