mp_machdep.c revision 255217
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 255217 2013-09-04 23:31:29Z kib $"); 29 30#include "opt_cpu.h" 31#include "opt_ddb.h" 32#include "opt_kstack_pages.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/cpuset.h> 40#ifdef GPROF 41#include <sys/gmon.h> 42#endif 43#include <sys/kernel.h> 44#include <sys/ktr.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/memrange.h> 48#include <sys/mutex.h> 49#include <sys/pcpu.h> 50#include <sys/proc.h> 51#include <sys/sched.h> 52#include <sys/smp.h> 53#include <sys/sysctl.h> 54 55#include <vm/vm.h> 56#include <vm/vm_param.h> 57#include <vm/pmap.h> 58#include <vm/vm_kern.h> 59#include <vm/vm_extern.h> 60 61#include <x86/apicreg.h> 62#include <machine/clock.h> 63#include <machine/cputypes.h> 64#include <machine/cpufunc.h> 65#include <x86/mca.h> 66#include <machine/md_var.h> 67#include <machine/pcb.h> 68#include <machine/psl.h> 69#include <machine/smp.h> 70#include <machine/specialreg.h> 71#include <machine/tss.h> 72 73#ifdef XENHVM 74#include <xen/hvm.h> 75#endif 76 77#define WARMBOOT_TARGET 0 78#define WARMBOOT_OFF (KERNBASE + 0x0467) 79#define WARMBOOT_SEG (KERNBASE + 0x0469) 80 81#define CMOS_REG (0x70) 82#define CMOS_DATA (0x71) 83#define BIOS_RESET (0x0f) 84#define BIOS_WARM (0x0a) 85 86/* lock region used by kernel profiling */ 87int mcount_lock; 88 89int mp_naps; /* # of Applications processors */ 90int boot_cpu_id = -1; /* designated BSP */ 91 92extern struct pcpu __pcpu[]; 93 94/* AP uses this during bootstrap. Do not staticize. */ 95char *bootSTK; 96static int bootAP; 97 98/* Free these after use */ 99void *bootstacks[MAXCPU]; 100 101/* Temporary variables for init_secondary() */ 102char *doublefault_stack; 103char *nmi_stack; 104void *dpcpu; 105 106struct pcb stoppcbs[MAXCPU]; 107struct pcb **susppcbs; 108 109/* Variables needed for SMP tlb shootdown. */ 110vm_offset_t smp_tlb_addr2; 111struct invpcid_descr smp_tlb_invpcid; 112volatile int smp_tlb_wait; 113uint64_t pcid_cr3; 114pmap_t smp_tlb_pmap; 115 116#ifdef COUNT_IPIS 117/* Interrupt counts. */ 118static u_long *ipi_preempt_counts[MAXCPU]; 119static u_long *ipi_ast_counts[MAXCPU]; 120u_long *ipi_invltlb_counts[MAXCPU]; 121u_long *ipi_invlrng_counts[MAXCPU]; 122u_long *ipi_invlpg_counts[MAXCPU]; 123u_long *ipi_invlcache_counts[MAXCPU]; 124u_long *ipi_rendezvous_counts[MAXCPU]; 125static u_long *ipi_hardclock_counts[MAXCPU]; 126#endif 127 128extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 129 130extern int pmap_pcid_enabled; 131 132/* 133 * Local data and functions. 134 */ 135 136static volatile cpuset_t ipi_nmi_pending; 137 138/* used to hold the AP's until we are ready to release them */ 139static struct mtx ap_boot_mtx; 140 141/* Set to 1 once we're ready to let the APs out of the pen. */ 142static volatile int aps_ready = 0; 143 144/* 145 * Store data from cpu_add() until later in the boot when we actually setup 146 * the APs. 147 */ 148struct cpu_info { 149 int cpu_present:1; 150 int cpu_bsp:1; 151 int cpu_disabled:1; 152 int cpu_hyperthread:1; 153} static cpu_info[MAX_APIC_ID + 1]; 154int cpu_apic_ids[MAXCPU]; 155int apic_cpuids[MAX_APIC_ID + 1]; 156 157/* Holds pending bitmap based IPIs per CPU */ 158static volatile u_int cpu_ipi_pending[MAXCPU]; 159 160static u_int boot_address; 161static int cpu_logical; /* logical cpus per core */ 162static int cpu_cores; /* cores per package */ 163 164static void assign_cpu_ids(void); 165static void set_interrupt_apic_ids(void); 166static int start_all_aps(void); 167static int start_ap(int apic_id); 168static void release_aps(void *dummy); 169 170static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 171static int hyperthreading_allowed = 1; 172static u_int bootMP_size; 173 174static void 175mem_range_AP_init(void) 176{ 177 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 178 mem_range_softc.mr_op->initAP(&mem_range_softc); 179} 180 181static void 182topo_probe_amd(void) 183{ 184 int core_id_bits; 185 int id; 186 187 /* AMD processors do not support HTT. */ 188 cpu_logical = 1; 189 190 if ((amd_feature2 & AMDID2_CMP) == 0) { 191 cpu_cores = 1; 192 return; 193 } 194 195 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 196 AMDID_COREID_SIZE_SHIFT; 197 if (core_id_bits == 0) { 198 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 199 return; 200 } 201 202 /* Fam 10h and newer should get here. */ 203 for (id = 0; id <= MAX_APIC_ID; id++) { 204 /* Check logical CPU availability. */ 205 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 206 continue; 207 /* Check if logical CPU has the same package ID. */ 208 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 209 continue; 210 cpu_cores++; 211 } 212} 213 214/* 215 * Round up to the next power of two, if necessary, and then 216 * take log2. 217 * Returns -1 if argument is zero. 218 */ 219static __inline int 220mask_width(u_int x) 221{ 222 223 return (fls(x << (1 - powerof2(x))) - 1); 224} 225 226static void 227topo_probe_0x4(void) 228{ 229 u_int p[4]; 230 int pkg_id_bits; 231 int core_id_bits; 232 int max_cores; 233 int max_logical; 234 int id; 235 236 /* Both zero and one here mean one logical processor per package. */ 237 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 238 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 239 if (max_logical <= 1) 240 return; 241 242 /* 243 * Because of uniformity assumption we examine only 244 * those logical processors that belong to the same 245 * package as BSP. Further, we count number of 246 * logical processors that belong to the same core 247 * as BSP thus deducing number of threads per core. 248 */ 249 if (cpu_high >= 0x4) { 250 cpuid_count(0x04, 0, p); 251 max_cores = ((p[0] >> 26) & 0x3f) + 1; 252 } else 253 max_cores = 1; 254 core_id_bits = mask_width(max_logical/max_cores); 255 if (core_id_bits < 0) 256 return; 257 pkg_id_bits = core_id_bits + mask_width(max_cores); 258 259 for (id = 0; id <= MAX_APIC_ID; id++) { 260 /* Check logical CPU availability. */ 261 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 262 continue; 263 /* Check if logical CPU has the same package ID. */ 264 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 265 continue; 266 cpu_cores++; 267 /* Check if logical CPU has the same package and core IDs. */ 268 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 269 cpu_logical++; 270 } 271 272 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 273 ("topo_probe_0x4 couldn't find BSP")); 274 275 cpu_cores /= cpu_logical; 276 hyperthreading_cpus = cpu_logical; 277} 278 279static void 280topo_probe_0xb(void) 281{ 282 u_int p[4]; 283 int bits; 284 int cnt; 285 int i; 286 int logical; 287 int type; 288 int x; 289 290 /* We only support three levels for now. */ 291 for (i = 0; i < 3; i++) { 292 cpuid_count(0x0b, i, p); 293 294 /* Fall back if CPU leaf 11 doesn't really exist. */ 295 if (i == 0 && p[1] == 0) { 296 topo_probe_0x4(); 297 return; 298 } 299 300 bits = p[0] & 0x1f; 301 logical = p[1] &= 0xffff; 302 type = (p[2] >> 8) & 0xff; 303 if (type == 0 || logical == 0) 304 break; 305 /* 306 * Because of uniformity assumption we examine only 307 * those logical processors that belong to the same 308 * package as BSP. 309 */ 310 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 311 if (!cpu_info[x].cpu_present || 312 cpu_info[x].cpu_disabled) 313 continue; 314 if (x >> bits == boot_cpu_id >> bits) 315 cnt++; 316 } 317 if (type == CPUID_TYPE_SMT) 318 cpu_logical = cnt; 319 else if (type == CPUID_TYPE_CORE) 320 cpu_cores = cnt; 321 } 322 if (cpu_logical == 0) 323 cpu_logical = 1; 324 cpu_cores /= cpu_logical; 325} 326 327/* 328 * Both topology discovery code and code that consumes topology 329 * information assume top-down uniformity of the topology. 330 * That is, all physical packages must be identical and each 331 * core in a package must have the same number of threads. 332 * Topology information is queried only on BSP, on which this 333 * code runs and for which it can query CPUID information. 334 * Then topology is extrapolated on all packages using the 335 * uniformity assumption. 336 */ 337static void 338topo_probe(void) 339{ 340 static int cpu_topo_probed = 0; 341 342 if (cpu_topo_probed) 343 return; 344 345 CPU_ZERO(&logical_cpus_mask); 346 if (mp_ncpus <= 1) 347 cpu_cores = cpu_logical = 1; 348 else if (cpu_vendor_id == CPU_VENDOR_AMD) 349 topo_probe_amd(); 350 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 351 /* 352 * See Intel(R) 64 Architecture Processor 353 * Topology Enumeration article for details. 354 * 355 * Note that 0x1 <= cpu_high < 4 case should be 356 * compatible with topo_probe_0x4() logic when 357 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 358 * or it should trigger the fallback otherwise. 359 */ 360 if (cpu_high >= 0xb) 361 topo_probe_0xb(); 362 else if (cpu_high >= 0x1) 363 topo_probe_0x4(); 364 } 365 366 /* 367 * Fallback: assume each logical CPU is in separate 368 * physical package. That is, no multi-core, no SMT. 369 */ 370 if (cpu_cores == 0 || cpu_logical == 0) 371 cpu_cores = cpu_logical = 1; 372 cpu_topo_probed = 1; 373} 374 375struct cpu_group * 376cpu_topo(void) 377{ 378 int cg_flags; 379 380 /* 381 * Determine whether any threading flags are 382 * necessry. 383 */ 384 topo_probe(); 385 if (cpu_logical > 1 && hyperthreading_cpus) 386 cg_flags = CG_FLAG_HTT; 387 else if (cpu_logical > 1) 388 cg_flags = CG_FLAG_SMT; 389 else 390 cg_flags = 0; 391 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 392 printf("WARNING: Non-uniform processors.\n"); 393 printf("WARNING: Using suboptimal topology.\n"); 394 return (smp_topo_none()); 395 } 396 /* 397 * No multi-core or hyper-threaded. 398 */ 399 if (cpu_logical * cpu_cores == 1) 400 return (smp_topo_none()); 401 /* 402 * Only HTT no multi-core. 403 */ 404 if (cpu_logical > 1 && cpu_cores == 1) 405 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 406 /* 407 * Only multi-core no HTT. 408 */ 409 if (cpu_cores > 1 && cpu_logical == 1) 410 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 411 /* 412 * Both HTT and multi-core. 413 */ 414 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 415 CG_SHARE_L1, cpu_logical, cg_flags)); 416} 417 418/* 419 * Calculate usable address in base memory for AP trampoline code. 420 */ 421u_int 422mp_bootaddress(u_int basemem) 423{ 424 425 bootMP_size = mptramp_end - mptramp_start; 426 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 427 if (((basemem * 1024) - boot_address) < bootMP_size) 428 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 429 /* 3 levels of page table pages */ 430 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 431 432 return mptramp_pagetables; 433} 434 435void 436cpu_add(u_int apic_id, char boot_cpu) 437{ 438 439 if (apic_id > MAX_APIC_ID) { 440 panic("SMP: APIC ID %d too high", apic_id); 441 return; 442 } 443 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 444 apic_id)); 445 cpu_info[apic_id].cpu_present = 1; 446 if (boot_cpu) { 447 KASSERT(boot_cpu_id == -1, 448 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 449 boot_cpu_id)); 450 boot_cpu_id = apic_id; 451 cpu_info[apic_id].cpu_bsp = 1; 452 } 453 if (mp_ncpus < MAXCPU) { 454 mp_ncpus++; 455 mp_maxid = mp_ncpus - 1; 456 } 457 if (bootverbose) 458 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 459 "AP"); 460} 461 462void 463cpu_mp_setmaxid(void) 464{ 465 466 /* 467 * mp_maxid should be already set by calls to cpu_add(). 468 * Just sanity check its value here. 469 */ 470 if (mp_ncpus == 0) 471 KASSERT(mp_maxid == 0, 472 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 473 else if (mp_ncpus == 1) 474 mp_maxid = 0; 475 else 476 KASSERT(mp_maxid >= mp_ncpus - 1, 477 ("%s: counters out of sync: max %d, count %d", __func__, 478 mp_maxid, mp_ncpus)); 479} 480 481int 482cpu_mp_probe(void) 483{ 484 485 /* 486 * Always record BSP in CPU map so that the mbuf init code works 487 * correctly. 488 */ 489 CPU_SETOF(0, &all_cpus); 490 if (mp_ncpus == 0) { 491 /* 492 * No CPUs were found, so this must be a UP system. Setup 493 * the variables to represent a system with a single CPU 494 * with an id of 0. 495 */ 496 mp_ncpus = 1; 497 return (0); 498 } 499 500 /* At least one CPU was found. */ 501 if (mp_ncpus == 1) { 502 /* 503 * One CPU was found, so this must be a UP system with 504 * an I/O APIC. 505 */ 506 mp_maxid = 0; 507 return (0); 508 } 509 510 /* At least two CPUs were found. */ 511 return (1); 512} 513 514/* 515 * Initialize the IPI handlers and start up the AP's. 516 */ 517void 518cpu_mp_start(void) 519{ 520 int i; 521 522 /* Initialize the logical ID to APIC ID table. */ 523 for (i = 0; i < MAXCPU; i++) { 524 cpu_apic_ids[i] = -1; 525 cpu_ipi_pending[i] = 0; 526 } 527 528 /* Install an inter-CPU IPI for TLB invalidation */ 529 if (pmap_pcid_enabled) { 530 setidt(IPI_INVLTLB, IDTVEC(invltlb_pcid), SDT_SYSIGT, 531 SEL_KPL, 0); 532 setidt(IPI_INVLPG, IDTVEC(invlpg_pcid), SDT_SYSIGT, 533 SEL_KPL, 0); 534 } else { 535 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 536 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 537 } 538 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 539 540 /* Install an inter-CPU IPI for cache invalidation. */ 541 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0); 542 543 /* Install an inter-CPU IPI for all-CPU rendezvous */ 544 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 545 546 /* Install generic inter-CPU IPI handler */ 547 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 548 SDT_SYSIGT, SEL_KPL, 0); 549 550 /* Install an inter-CPU IPI for CPU stop/restart */ 551 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 552 553 /* Install an inter-CPU IPI for CPU suspend/resume */ 554 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0); 555 556 /* Set boot_cpu_id if needed. */ 557 if (boot_cpu_id == -1) { 558 boot_cpu_id = PCPU_GET(apic_id); 559 cpu_info[boot_cpu_id].cpu_bsp = 1; 560 } else 561 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 562 ("BSP's APIC ID doesn't match boot_cpu_id")); 563 564 /* Probe logical/physical core configuration. */ 565 topo_probe(); 566 567 assign_cpu_ids(); 568 569 /* Start each Application Processor */ 570 start_all_aps(); 571 572 set_interrupt_apic_ids(); 573} 574 575 576/* 577 * Print various information about the SMP system hardware and setup. 578 */ 579void 580cpu_mp_announce(void) 581{ 582 const char *hyperthread; 583 int i; 584 585 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 586 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 587 if (hyperthreading_cpus > 1) 588 printf(" x %d HTT threads", cpu_logical); 589 else if (cpu_logical > 1) 590 printf(" x %d SMT threads", cpu_logical); 591 printf("\n"); 592 593 /* List active CPUs first. */ 594 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 595 for (i = 1; i < mp_ncpus; i++) { 596 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 597 hyperthread = "/HT"; 598 else 599 hyperthread = ""; 600 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 601 cpu_apic_ids[i]); 602 } 603 604 /* List disabled CPUs last. */ 605 for (i = 0; i <= MAX_APIC_ID; i++) { 606 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 607 continue; 608 if (cpu_info[i].cpu_hyperthread) 609 hyperthread = "/HT"; 610 else 611 hyperthread = ""; 612 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 613 i); 614 } 615} 616 617/* 618 * AP CPU's call this to initialize themselves. 619 */ 620void 621init_secondary(void) 622{ 623 struct pcpu *pc; 624 struct nmi_pcpu *np; 625 u_int64_t msr, cr0; 626 u_int cpuid; 627 int cpu, gsel_tss, x; 628 struct region_descriptor ap_gdt; 629 630 /* Set by the startup code for us to use */ 631 cpu = bootAP; 632 633 /* Init tss */ 634 common_tss[cpu] = common_tss[0]; 635 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 636 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) + 637 IOPAGES * PAGE_SIZE; 638 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 639 640 /* The NMI stack runs on IST2. */ 641 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1; 642 common_tss[cpu].tss_ist2 = (long) np; 643 644 /* Prepare private GDT */ 645 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 646 for (x = 0; x < NGDT; x++) { 647 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 648 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1)) 649 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]); 650 } 651 ssdtosyssd(&gdt_segs[GPROC0_SEL], 652 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]); 653 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 654 ap_gdt.rd_base = (long) &gdt[NGDT * cpu]; 655 lgdt(&ap_gdt); /* does magic intra-segment return */ 656 657 /* Get per-cpu data */ 658 pc = &__pcpu[cpu]; 659 660 /* prime data page for it to use */ 661 pcpu_init(pc, cpu, sizeof(struct pcpu)); 662 dpcpu_init(dpcpu, cpu); 663 pc->pc_apic_id = cpu_apic_ids[cpu]; 664 pc->pc_prvspace = pc; 665 pc->pc_curthread = 0; 666 pc->pc_tssp = &common_tss[cpu]; 667 pc->pc_commontssp = &common_tss[cpu]; 668 pc->pc_rsp0 = 0; 669 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu + 670 GPROC0_SEL]; 671 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL]; 672 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL]; 673 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu + 674 GUSERLDT_SEL]; 675 676 /* Save the per-cpu pointer for use by the NMI handler. */ 677 np->np_pcpu = (register_t) pc; 678 679 wrmsr(MSR_FSBASE, 0); /* User value */ 680 wrmsr(MSR_GSBASE, (u_int64_t)pc); 681 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 682 683 lidt(&r_idt); 684 685 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 686 ltr(gsel_tss); 687 688 /* 689 * Set to a known state: 690 * Set by mpboot.s: CR0_PG, CR0_PE 691 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 692 */ 693 cr0 = rcr0(); 694 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 695 load_cr0(cr0); 696 697 /* Set up the fast syscall stuff */ 698 msr = rdmsr(MSR_EFER) | EFER_SCE; 699 wrmsr(MSR_EFER, msr); 700 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 701 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 702 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 703 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 704 wrmsr(MSR_STAR, msr); 705 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 706 707 /* Disable local APIC just to be sure. */ 708 lapic_disable(); 709 710 /* signal our startup to the BSP. */ 711 mp_naps++; 712 713 /* Spin until the BSP releases the AP's. */ 714 while (!aps_ready) 715 ia32_pause(); 716 717 /* Initialize the PAT MSR. */ 718 pmap_init_pat(); 719 720 /* set up CPU registers and state */ 721 cpu_setregs(); 722 723 /* set up SSE/NX registers */ 724 initializecpu(); 725 726 /* set up FPU state on the AP */ 727 fpuinit(); 728 729#ifdef XENHVM 730 /* register vcpu_info area */ 731 xen_hvm_init_cpu(); 732#endif 733 734 /* A quick check from sanity claus */ 735 cpuid = PCPU_GET(cpuid); 736 if (PCPU_GET(apic_id) != lapic_id()) { 737 printf("SMP: cpuid = %d\n", cpuid); 738 printf("SMP: actual apic_id = %d\n", lapic_id()); 739 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 740 panic("cpuid mismatch! boom!!"); 741 } 742 743 /* Initialize curthread. */ 744 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 745 PCPU_SET(curthread, PCPU_GET(idlethread)); 746 747 mca_init(); 748 749 mtx_lock_spin(&ap_boot_mtx); 750 751 /* Init local apic for irq's */ 752 lapic_setup(1); 753 754 /* Set memory range attributes for this CPU to match the BSP */ 755 mem_range_AP_init(); 756 757 smp_cpus++; 758 759 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 760 printf("SMP: AP CPU #%d Launched!\n", cpuid); 761 762 /* Determine if we are a logical CPU. */ 763 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 764 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 765 CPU_SET(cpuid, &logical_cpus_mask); 766 767 if (bootverbose) 768 lapic_dump("AP"); 769 770 if (smp_cpus == mp_ncpus) { 771 /* enable IPI's, tlb shootdown, freezes etc */ 772 atomic_store_rel_int(&smp_started, 1); 773 smp_active = 1; /* historic */ 774 } 775 776 /* 777 * Enable global pages TLB extension 778 * This also implicitly flushes the TLB 779 */ 780 781 load_cr4(rcr4() | CR4_PGE); 782 if (pmap_pcid_enabled) 783 load_cr4(rcr4() | CR4_PCIDE); 784 load_ds(_udatasel); 785 load_es(_udatasel); 786 load_fs(_ufssel); 787 mtx_unlock_spin(&ap_boot_mtx); 788 789 /* Wait until all the AP's are up. */ 790 while (smp_started == 0) 791 ia32_pause(); 792 793 /* Start per-CPU event timers. */ 794 cpu_initclocks_ap(); 795 796 sched_throw(NULL); 797 798 panic("scheduler returned us to %s", __func__); 799 /* NOTREACHED */ 800} 801 802/******************************************************************* 803 * local functions and data 804 */ 805 806/* 807 * We tell the I/O APIC code about all the CPUs we want to receive 808 * interrupts. If we don't want certain CPUs to receive IRQs we 809 * can simply not tell the I/O APIC code about them in this function. 810 * We also do not tell it about the BSP since it tells itself about 811 * the BSP internally to work with UP kernels and on UP machines. 812 */ 813static void 814set_interrupt_apic_ids(void) 815{ 816 u_int i, apic_id; 817 818 for (i = 0; i < MAXCPU; i++) { 819 apic_id = cpu_apic_ids[i]; 820 if (apic_id == -1) 821 continue; 822 if (cpu_info[apic_id].cpu_bsp) 823 continue; 824 if (cpu_info[apic_id].cpu_disabled) 825 continue; 826 827 /* Don't let hyperthreads service interrupts. */ 828 if (hyperthreading_cpus > 1 && 829 apic_id % hyperthreading_cpus != 0) 830 continue; 831 832 intr_add_cpu(i); 833 } 834} 835 836/* 837 * Assign logical CPU IDs to local APICs. 838 */ 839static void 840assign_cpu_ids(void) 841{ 842 u_int i; 843 844 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 845 &hyperthreading_allowed); 846 847 /* Check for explicitly disabled CPUs. */ 848 for (i = 0; i <= MAX_APIC_ID; i++) { 849 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 850 continue; 851 852 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 853 cpu_info[i].cpu_hyperthread = 1; 854 855 /* 856 * Don't use HT CPU if it has been disabled by a 857 * tunable. 858 */ 859 if (hyperthreading_allowed == 0) { 860 cpu_info[i].cpu_disabled = 1; 861 continue; 862 } 863 } 864 865 /* Don't use this CPU if it has been disabled by a tunable. */ 866 if (resource_disabled("lapic", i)) { 867 cpu_info[i].cpu_disabled = 1; 868 continue; 869 } 870 } 871 872 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 873 hyperthreading_cpus = 0; 874 cpu_logical = 1; 875 } 876 877 /* 878 * Assign CPU IDs to local APIC IDs and disable any CPUs 879 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 880 * 881 * To minimize confusion for userland, we attempt to number 882 * CPUs such that all threads and cores in a package are 883 * grouped together. For now we assume that the BSP is always 884 * the first thread in a package and just start adding APs 885 * starting with the BSP's APIC ID. 886 */ 887 mp_ncpus = 1; 888 cpu_apic_ids[0] = boot_cpu_id; 889 apic_cpuids[boot_cpu_id] = 0; 890 for (i = boot_cpu_id + 1; i != boot_cpu_id; 891 i == MAX_APIC_ID ? i = 0 : i++) { 892 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 893 cpu_info[i].cpu_disabled) 894 continue; 895 896 if (mp_ncpus < MAXCPU) { 897 cpu_apic_ids[mp_ncpus] = i; 898 apic_cpuids[i] = mp_ncpus; 899 mp_ncpus++; 900 } else 901 cpu_info[i].cpu_disabled = 1; 902 } 903 KASSERT(mp_maxid >= mp_ncpus - 1, 904 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 905 mp_ncpus)); 906} 907 908/* 909 * start each AP in our list 910 */ 911static int 912start_all_aps(void) 913{ 914 vm_offset_t va = boot_address + KERNBASE; 915 u_int64_t *pt4, *pt3, *pt2; 916 u_int32_t mpbioswarmvec; 917 int apic_id, cpu, i; 918 u_char mpbiosreason; 919 920 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 921 922 /* install the AP 1st level boot code */ 923 pmap_kenter(va, boot_address); 924 pmap_invalidate_page(kernel_pmap, va); 925 bcopy(mptramp_start, (void *)va, bootMP_size); 926 927 /* Locate the page tables, they'll be below the trampoline */ 928 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 929 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 930 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 931 932 /* Create the initial 1GB replicated page tables */ 933 for (i = 0; i < 512; i++) { 934 /* Each slot of the level 4 pages points to the same level 3 page */ 935 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 936 pt4[i] |= PG_V | PG_RW | PG_U; 937 938 /* Each slot of the level 3 pages points to the same level 2 page */ 939 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 940 pt3[i] |= PG_V | PG_RW | PG_U; 941 942 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 943 pt2[i] = i * (2 * 1024 * 1024); 944 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 945 } 946 947 /* save the current value of the warm-start vector */ 948 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 949 outb(CMOS_REG, BIOS_RESET); 950 mpbiosreason = inb(CMOS_DATA); 951 952 /* setup a vector to our boot code */ 953 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 954 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 955 outb(CMOS_REG, BIOS_RESET); 956 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 957 958 /* start each AP */ 959 for (cpu = 1; cpu < mp_ncpus; cpu++) { 960 apic_id = cpu_apic_ids[cpu]; 961 962 /* allocate and set up an idle stack data page */ 963 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena, 964 KSTACK_PAGES * PAGE_SIZE, M_WAITOK | M_ZERO); 965 doublefault_stack = (char *)kmem_malloc(kernel_arena, 966 PAGE_SIZE, M_WAITOK | M_ZERO); 967 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE, 968 M_WAITOK | M_ZERO); 969 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 970 M_WAITOK | M_ZERO); 971 972 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 973 bootAP = cpu; 974 975 /* attempt to start the Application Processor */ 976 if (!start_ap(apic_id)) { 977 /* restore the warmstart vector */ 978 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 979 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 980 } 981 982 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 983 } 984 985 /* restore the warmstart vector */ 986 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 987 988 outb(CMOS_REG, BIOS_RESET); 989 outb(CMOS_DATA, mpbiosreason); 990 991 /* number of APs actually started */ 992 return mp_naps; 993} 994 995 996/* 997 * This function starts the AP (application processor) identified 998 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 999 * to accomplish this. This is necessary because of the nuances 1000 * of the different hardware we might encounter. It isn't pretty, 1001 * but it seems to work. 1002 */ 1003static int 1004start_ap(int apic_id) 1005{ 1006 int vector, ms; 1007 int cpus; 1008 1009 /* calculate the vector */ 1010 vector = (boot_address >> 12) & 0xff; 1011 1012 /* used as a watchpoint to signal AP startup */ 1013 cpus = mp_naps; 1014 1015 ipi_startup(apic_id, vector); 1016 1017 /* Wait up to 5 seconds for it to start. */ 1018 for (ms = 0; ms < 5000; ms++) { 1019 if (mp_naps > cpus) 1020 return 1; /* return SUCCESS */ 1021 DELAY(1000); 1022 } 1023 return 0; /* return FAILURE */ 1024} 1025 1026#ifdef COUNT_XINVLTLB_HITS 1027u_int xhits_gbl[MAXCPU]; 1028u_int xhits_pg[MAXCPU]; 1029u_int xhits_rng[MAXCPU]; 1030static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1031SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1032 sizeof(xhits_gbl), "IU", ""); 1033SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1034 sizeof(xhits_pg), "IU", ""); 1035SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1036 sizeof(xhits_rng), "IU", ""); 1037 1038u_int ipi_global; 1039u_int ipi_page; 1040u_int ipi_range; 1041u_int ipi_range_size; 1042SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1043SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1044SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1045SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, 1046 &ipi_range_size, 0, ""); 1047 1048u_int ipi_masked_global; 1049u_int ipi_masked_page; 1050u_int ipi_masked_range; 1051u_int ipi_masked_range_size; 1052SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1053 &ipi_masked_global, 0, ""); 1054SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1055 &ipi_masked_page, 0, ""); 1056SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1057 &ipi_masked_range, 0, ""); 1058SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1059 &ipi_masked_range_size, 0, ""); 1060#endif /* COUNT_XINVLTLB_HITS */ 1061 1062/* 1063 * Init and startup IPI. 1064 */ 1065void 1066ipi_startup(int apic_id, int vector) 1067{ 1068 1069 /* 1070 * first we do an INIT IPI: this INIT IPI might be run, resetting 1071 * and running the target CPU. OR this INIT IPI might be latched (P5 1072 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1073 * ignored. 1074 */ 1075 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1076 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1077 lapic_ipi_wait(-1); 1078 DELAY(10000); /* wait ~10mS */ 1079 1080 /* 1081 * next we do a STARTUP IPI: the previous INIT IPI might still be 1082 * latched, (P5 bug) this 1st STARTUP would then terminate 1083 * immediately, and the previously started INIT IPI would continue. OR 1084 * the previous INIT IPI has already run. and this STARTUP IPI will 1085 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1086 * will run. 1087 */ 1088 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1089 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1090 vector, apic_id); 1091 lapic_ipi_wait(-1); 1092 DELAY(200); /* wait ~200uS */ 1093 1094 /* 1095 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1096 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1097 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1098 * recognized after hardware RESET or INIT IPI. 1099 */ 1100 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1101 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1102 vector, apic_id); 1103 lapic_ipi_wait(-1); 1104 DELAY(200); /* wait ~200uS */ 1105} 1106 1107/* 1108 * Send an IPI to specified CPU handling the bitmap logic. 1109 */ 1110static void 1111ipi_send_cpu(int cpu, u_int ipi) 1112{ 1113 u_int bitmap, old_pending, new_pending; 1114 1115 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1116 1117 if (IPI_IS_BITMAPED(ipi)) { 1118 bitmap = 1 << ipi; 1119 ipi = IPI_BITMAP_VECTOR; 1120 do { 1121 old_pending = cpu_ipi_pending[cpu]; 1122 new_pending = old_pending | bitmap; 1123 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1124 old_pending, new_pending)); 1125 if (old_pending) 1126 return; 1127 } 1128 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1129} 1130 1131/* 1132 * Flush the TLB on all other CPU's 1133 */ 1134static void 1135smp_tlb_shootdown(u_int vector, pmap_t pmap, vm_offset_t addr1, 1136 vm_offset_t addr2) 1137{ 1138 u_int ncpu; 1139 1140 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1141 if (ncpu < 1) 1142 return; /* no other cpus */ 1143 if (!(read_rflags() & PSL_I)) 1144 panic("%s: interrupts disabled", __func__); 1145 mtx_lock_spin(&smp_ipi_mtx); 1146 smp_tlb_invpcid.addr = addr1; 1147 if (pmap == NULL) { 1148 smp_tlb_invpcid.pcid = 0; 1149 } else { 1150 smp_tlb_invpcid.pcid = pmap->pm_pcid; 1151 pcid_cr3 = pmap->pm_cr3; 1152 } 1153 smp_tlb_addr2 = addr2; 1154 smp_tlb_pmap = pmap; 1155 atomic_store_rel_int(&smp_tlb_wait, 0); 1156 ipi_all_but_self(vector); 1157 while (smp_tlb_wait < ncpu) 1158 ia32_pause(); 1159 mtx_unlock_spin(&smp_ipi_mtx); 1160} 1161 1162static void 1163smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap, 1164 vm_offset_t addr1, vm_offset_t addr2) 1165{ 1166 int cpu, ncpu, othercpus; 1167 1168 othercpus = mp_ncpus - 1; 1169 if (CPU_ISFULLSET(&mask)) { 1170 if (othercpus < 1) 1171 return; 1172 } else { 1173 CPU_CLR(PCPU_GET(cpuid), &mask); 1174 if (CPU_EMPTY(&mask)) 1175 return; 1176 } 1177 if (!(read_rflags() & PSL_I)) 1178 panic("%s: interrupts disabled", __func__); 1179 mtx_lock_spin(&smp_ipi_mtx); 1180 smp_tlb_invpcid.addr = addr1; 1181 if (pmap == NULL) { 1182 smp_tlb_invpcid.pcid = 0; 1183 } else { 1184 smp_tlb_invpcid.pcid = pmap->pm_pcid; 1185 pcid_cr3 = pmap->pm_cr3; 1186 } 1187 smp_tlb_addr2 = addr2; 1188 smp_tlb_pmap = pmap; 1189 atomic_store_rel_int(&smp_tlb_wait, 0); 1190 if (CPU_ISFULLSET(&mask)) { 1191 ncpu = othercpus; 1192 ipi_all_but_self(vector); 1193 } else { 1194 ncpu = 0; 1195 while ((cpu = CPU_FFS(&mask)) != 0) { 1196 cpu--; 1197 CPU_CLR(cpu, &mask); 1198 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, 1199 cpu, vector); 1200 ipi_send_cpu(cpu, vector); 1201 ncpu++; 1202 } 1203 } 1204 while (smp_tlb_wait < ncpu) 1205 ia32_pause(); 1206 mtx_unlock_spin(&smp_ipi_mtx); 1207} 1208 1209void 1210smp_cache_flush(void) 1211{ 1212 1213 if (smp_started) 1214 smp_tlb_shootdown(IPI_INVLCACHE, NULL, 0, 0); 1215} 1216 1217void 1218smp_invltlb(pmap_t pmap) 1219{ 1220 1221 if (smp_started) { 1222 smp_tlb_shootdown(IPI_INVLTLB, pmap, 0, 0); 1223#ifdef COUNT_XINVLTLB_HITS 1224 ipi_global++; 1225#endif 1226 } 1227} 1228 1229void 1230smp_invlpg(pmap_t pmap, vm_offset_t addr) 1231{ 1232 1233 if (smp_started) { 1234 smp_tlb_shootdown(IPI_INVLPG, pmap, addr, 0); 1235#ifdef COUNT_XINVLTLB_HITS 1236 ipi_page++; 1237#endif 1238 } 1239} 1240 1241void 1242smp_invlpg_range(pmap_t pmap, vm_offset_t addr1, vm_offset_t addr2) 1243{ 1244 1245 if (smp_started) { 1246 smp_tlb_shootdown(IPI_INVLRNG, pmap, addr1, addr2); 1247#ifdef COUNT_XINVLTLB_HITS 1248 ipi_range++; 1249 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1250#endif 1251 } 1252} 1253 1254void 1255smp_masked_invltlb(cpuset_t mask, pmap_t pmap) 1256{ 1257 1258 if (smp_started) { 1259 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, NULL, 0, 0); 1260#ifdef COUNT_XINVLTLB_HITS 1261 ipi_masked_global++; 1262#endif 1263 } 1264} 1265 1266void 1267smp_masked_invlpg(cpuset_t mask, pmap_t pmap, vm_offset_t addr) 1268{ 1269 1270 if (smp_started) { 1271 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0); 1272#ifdef COUNT_XINVLTLB_HITS 1273 ipi_masked_page++; 1274#endif 1275 } 1276} 1277 1278void 1279smp_masked_invlpg_range(cpuset_t mask, pmap_t pmap, vm_offset_t addr1, 1280 vm_offset_t addr2) 1281{ 1282 1283 if (smp_started) { 1284 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, addr1, 1285 addr2); 1286#ifdef COUNT_XINVLTLB_HITS 1287 ipi_masked_range++; 1288 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1289#endif 1290 } 1291} 1292 1293void 1294ipi_bitmap_handler(struct trapframe frame) 1295{ 1296 struct trapframe *oldframe; 1297 struct thread *td; 1298 int cpu = PCPU_GET(cpuid); 1299 u_int ipi_bitmap; 1300 1301 critical_enter(); 1302 td = curthread; 1303 td->td_intr_nesting_level++; 1304 oldframe = td->td_intr_frame; 1305 td->td_intr_frame = &frame; 1306 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1307 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1308#ifdef COUNT_IPIS 1309 (*ipi_preempt_counts[cpu])++; 1310#endif 1311 sched_preempt(td); 1312 } 1313 if (ipi_bitmap & (1 << IPI_AST)) { 1314#ifdef COUNT_IPIS 1315 (*ipi_ast_counts[cpu])++; 1316#endif 1317 /* Nothing to do for AST */ 1318 } 1319 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1320#ifdef COUNT_IPIS 1321 (*ipi_hardclock_counts[cpu])++; 1322#endif 1323 hardclockintr(); 1324 } 1325 td->td_intr_frame = oldframe; 1326 td->td_intr_nesting_level--; 1327 critical_exit(); 1328} 1329 1330/* 1331 * send an IPI to a set of cpus. 1332 */ 1333void 1334ipi_selected(cpuset_t cpus, u_int ipi) 1335{ 1336 int cpu; 1337 1338 /* 1339 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1340 * of help in order to understand what is the source. 1341 * Set the mask of receiving CPUs for this purpose. 1342 */ 1343 if (ipi == IPI_STOP_HARD) 1344 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1345 1346 while ((cpu = CPU_FFS(&cpus)) != 0) { 1347 cpu--; 1348 CPU_CLR(cpu, &cpus); 1349 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1350 ipi_send_cpu(cpu, ipi); 1351 } 1352} 1353 1354/* 1355 * send an IPI to a specific CPU. 1356 */ 1357void 1358ipi_cpu(int cpu, u_int ipi) 1359{ 1360 1361 /* 1362 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1363 * of help in order to understand what is the source. 1364 * Set the mask of receiving CPUs for this purpose. 1365 */ 1366 if (ipi == IPI_STOP_HARD) 1367 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1368 1369 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1370 ipi_send_cpu(cpu, ipi); 1371} 1372 1373/* 1374 * send an IPI to all CPUs EXCEPT myself 1375 */ 1376void 1377ipi_all_but_self(u_int ipi) 1378{ 1379 cpuset_t other_cpus; 1380 1381 other_cpus = all_cpus; 1382 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1383 1384 if (IPI_IS_BITMAPED(ipi)) { 1385 ipi_selected(other_cpus, ipi); 1386 return; 1387 } 1388 1389 /* 1390 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1391 * of help in order to understand what is the source. 1392 * Set the mask of receiving CPUs for this purpose. 1393 */ 1394 if (ipi == IPI_STOP_HARD) 1395 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1396 1397 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1398 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1399} 1400 1401int 1402ipi_nmi_handler() 1403{ 1404 u_int cpuid; 1405 1406 /* 1407 * As long as there is not a simple way to know about a NMI's 1408 * source, if the bitmask for the current CPU is present in 1409 * the global pending bitword an IPI_STOP_HARD has been issued 1410 * and should be handled. 1411 */ 1412 cpuid = PCPU_GET(cpuid); 1413 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1414 return (1); 1415 1416 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1417 cpustop_handler(); 1418 return (0); 1419} 1420 1421/* 1422 * Handle an IPI_STOP by saving our current context and spinning until we 1423 * are resumed. 1424 */ 1425void 1426cpustop_handler(void) 1427{ 1428 u_int cpu; 1429 1430 cpu = PCPU_GET(cpuid); 1431 1432 savectx(&stoppcbs[cpu]); 1433 1434 /* Indicate that we are stopped */ 1435 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1436 1437 /* Wait for restart */ 1438 while (!CPU_ISSET(cpu, &started_cpus)) 1439 ia32_pause(); 1440 1441 CPU_CLR_ATOMIC(cpu, &started_cpus); 1442 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1443 1444#ifdef DDB 1445 amd64_db_resume_dbreg(); 1446#endif 1447 1448 if (cpu == 0 && cpustop_restartfunc != NULL) { 1449 cpustop_restartfunc(); 1450 cpustop_restartfunc = NULL; 1451 } 1452} 1453 1454/* 1455 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1456 * are resumed. 1457 */ 1458void 1459cpususpend_handler(void) 1460{ 1461 u_int cpu; 1462 1463 cpu = PCPU_GET(cpuid); 1464 1465 if (savectx(susppcbs[cpu])) { 1466 ctx_fpusave(susppcbs[cpu]->pcb_fpususpend); 1467 wbinvd(); 1468 CPU_SET_ATOMIC(cpu, &suspended_cpus); 1469 } else { 1470 pmap_init_pat(); 1471 initializecpu(); 1472 PCPU_SET(switchtime, 0); 1473 PCPU_SET(switchticks, ticks); 1474 1475 /* Indicate that we are resumed */ 1476 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1477 } 1478 1479 /* Wait for resume */ 1480 while (!CPU_ISSET(cpu, &started_cpus)) 1481 ia32_pause(); 1482 1483 /* Resume MCA and local APIC */ 1484 mca_resume(); 1485 lapic_setup(0); 1486 1487 CPU_CLR_ATOMIC(cpu, &started_cpus); 1488} 1489 1490/* 1491 * This is called once the rest of the system is up and running and we're 1492 * ready to let the AP's out of the pen. 1493 */ 1494static void 1495release_aps(void *dummy __unused) 1496{ 1497 1498 if (mp_ncpus == 1) 1499 return; 1500 atomic_store_rel_int(&aps_ready, 1); 1501 while (smp_started == 0) 1502 ia32_pause(); 1503} 1504SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1505 1506#ifdef COUNT_IPIS 1507/* 1508 * Setup interrupt counters for IPI handlers. 1509 */ 1510static void 1511mp_ipi_intrcnt(void *dummy) 1512{ 1513 char buf[64]; 1514 int i; 1515 1516 CPU_FOREACH(i) { 1517 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1518 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1519 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1520 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1521 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1522 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1523 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i); 1524 intrcnt_add(buf, &ipi_invlcache_counts[i]); 1525 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1526 intrcnt_add(buf, &ipi_preempt_counts[i]); 1527 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1528 intrcnt_add(buf, &ipi_ast_counts[i]); 1529 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1530 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1531 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1532 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1533 } 1534} 1535SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1536#endif 1537 1538