mp_machdep.c revision 191405
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 191405 2009-04-22 21:40:37Z jhb $"); 29 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#ifdef GPROF 39#include <sys/gmon.h> 40#endif 41#include <sys/kernel.h> 42#include <sys/ktr.h> 43#include <sys/lock.h> 44#include <sys/malloc.h> 45#include <sys/memrange.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/sched.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52 53#include <vm/vm.h> 54#include <vm/vm_param.h> 55#include <vm/pmap.h> 56#include <vm/vm_kern.h> 57#include <vm/vm_extern.h> 58 59#include <machine/apicreg.h> 60#include <machine/cputypes.h> 61#include <machine/cpufunc.h> 62#include <machine/md_var.h> 63#include <machine/mp_watchdog.h> 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#include <machine/smp.h> 67#include <machine/specialreg.h> 68#include <machine/tss.h> 69 70#define WARMBOOT_TARGET 0 71#define WARMBOOT_OFF (KERNBASE + 0x0467) 72#define WARMBOOT_SEG (KERNBASE + 0x0469) 73 74#define CMOS_REG (0x70) 75#define CMOS_DATA (0x71) 76#define BIOS_RESET (0x0f) 77#define BIOS_WARM (0x0a) 78 79/* lock region used by kernel profiling */ 80int mcount_lock; 81 82int mp_naps; /* # of Applications processors */ 83int boot_cpu_id = -1; /* designated BSP */ 84 85extern struct pcpu __pcpu[]; 86 87/* AP uses this during bootstrap. Do not staticize. */ 88char *bootSTK; 89static int bootAP; 90 91/* Free these after use */ 92void *bootstacks[MAXCPU]; 93 94/* Temporary holder for double fault stack */ 95char *doublefault_stack; 96char *nmi_stack; 97 98/* Hotwire a 0->4MB V==P mapping */ 99extern pt_entry_t *KPTphys; 100 101/* SMP page table page */ 102extern pt_entry_t *SMPpt; 103 104struct pcb stoppcbs[MAXCPU]; 105struct xpcb *stopxpcbs = NULL; 106 107/* Variables needed for SMP tlb shootdown. */ 108vm_offset_t smp_tlb_addr1; 109vm_offset_t smp_tlb_addr2; 110volatile int smp_tlb_wait; 111 112extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 113 114#ifdef STOP_NMI 115volatile cpumask_t ipi_nmi_pending; 116 117static void ipi_nmi_selected(u_int32_t cpus); 118#endif 119 120/* 121 * Local data and functions. 122 */ 123 124#ifdef STOP_NMI 125/* 126 * Provide an alternate method of stopping other CPUs. If another CPU has 127 * disabled interrupts the conventional STOP IPI will be blocked. This 128 * NMI-based stop should get through in that case. 129 */ 130static int stop_cpus_with_nmi = 1; 131SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 132 &stop_cpus_with_nmi, 0, ""); 133TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 134#else 135#define stop_cpus_with_nmi 0 136#endif 137 138static u_int logical_cpus; 139 140/* used to hold the AP's until we are ready to release them */ 141static struct mtx ap_boot_mtx; 142 143/* Set to 1 once we're ready to let the APs out of the pen. */ 144static volatile int aps_ready = 0; 145 146/* 147 * Store data from cpu_add() until later in the boot when we actually setup 148 * the APs. 149 */ 150struct cpu_info { 151 int cpu_present:1; 152 int cpu_bsp:1; 153 int cpu_disabled:1; 154 int cpu_hyperthread:1; 155} static cpu_info[MAX_APIC_ID + 1]; 156int cpu_apic_ids[MAXCPU]; 157int apic_cpuids[MAX_APIC_ID + 1]; 158 159/* Holds pending bitmap based IPIs per CPU */ 160static volatile u_int cpu_ipi_pending[MAXCPU]; 161 162static u_int boot_address; 163 164static void assign_cpu_ids(void); 165static void set_interrupt_apic_ids(void); 166static int start_all_aps(void); 167static int start_ap(int apic_id); 168static void release_aps(void *dummy); 169 170static int hlt_logical_cpus; 171static u_int hyperthreading_cpus; 172static cpumask_t hyperthreading_cpus_mask; 173static int hyperthreading_allowed = 1; 174static struct sysctl_ctx_list logical_cpu_clist; 175static u_int bootMP_size; 176 177static void 178mem_range_AP_init(void) 179{ 180 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 181 mem_range_softc.mr_op->initAP(&mem_range_softc); 182} 183 184struct cpu_group * 185cpu_topo(void) 186{ 187 if (cpu_cores == 0) 188 cpu_cores = 1; 189 if (cpu_logical == 0) 190 cpu_logical = 1; 191 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 192 printf("WARNING: Non-uniform processors.\n"); 193 printf("WARNING: Using suboptimal topology.\n"); 194 return (smp_topo_none()); 195 } 196 /* 197 * No multi-core or hyper-threaded. 198 */ 199 if (cpu_logical * cpu_cores == 1) 200 return (smp_topo_none()); 201 /* 202 * Only HTT no multi-core. 203 */ 204 if (cpu_logical > 1 && cpu_cores == 1) 205 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 206 /* 207 * Only multi-core no HTT. 208 */ 209 if (cpu_cores > 1 && cpu_logical == 1) 210 return (smp_topo_1level(CG_SHARE_NONE, cpu_cores, 0)); 211 /* 212 * Both HTT and multi-core. 213 */ 214 return (smp_topo_2level(CG_SHARE_NONE, cpu_cores, 215 CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 216} 217 218/* 219 * Calculate usable address in base memory for AP trampoline code. 220 */ 221u_int 222mp_bootaddress(u_int basemem) 223{ 224 225 bootMP_size = mptramp_end - mptramp_start; 226 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 227 if (((basemem * 1024) - boot_address) < bootMP_size) 228 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 229 /* 3 levels of page table pages */ 230 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 231 232 return mptramp_pagetables; 233} 234 235void 236cpu_add(u_int apic_id, char boot_cpu) 237{ 238 239 if (apic_id > MAX_APIC_ID) { 240 panic("SMP: APIC ID %d too high", apic_id); 241 return; 242 } 243 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 244 apic_id)); 245 cpu_info[apic_id].cpu_present = 1; 246 if (boot_cpu) { 247 KASSERT(boot_cpu_id == -1, 248 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 249 boot_cpu_id)); 250 boot_cpu_id = apic_id; 251 cpu_info[apic_id].cpu_bsp = 1; 252 } 253 if (mp_ncpus < MAXCPU) { 254 mp_ncpus++; 255 mp_maxid = mp_ncpus -1; 256 } 257 if (bootverbose) 258 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 259 "AP"); 260} 261 262void 263cpu_mp_setmaxid(void) 264{ 265 266 /* 267 * mp_maxid should be already set by calls to cpu_add(). 268 * Just sanity check its value here. 269 */ 270 if (mp_ncpus == 0) 271 KASSERT(mp_maxid == 0, 272 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 273 else if (mp_ncpus == 1) 274 mp_maxid = 0; 275 else 276 KASSERT(mp_maxid >= mp_ncpus - 1, 277 ("%s: counters out of sync: max %d, count %d", __func__, 278 mp_maxid, mp_ncpus)); 279} 280 281int 282cpu_mp_probe(void) 283{ 284 285 /* 286 * Always record BSP in CPU map so that the mbuf init code works 287 * correctly. 288 */ 289 all_cpus = 1; 290 if (mp_ncpus == 0) { 291 /* 292 * No CPUs were found, so this must be a UP system. Setup 293 * the variables to represent a system with a single CPU 294 * with an id of 0. 295 */ 296 mp_ncpus = 1; 297 return (0); 298 } 299 300 /* At least one CPU was found. */ 301 if (mp_ncpus == 1) { 302 /* 303 * One CPU was found, so this must be a UP system with 304 * an I/O APIC. 305 */ 306 mp_maxid = 0; 307 return (0); 308 } 309 310 /* At least two CPUs were found. */ 311 return (1); 312} 313 314/* 315 * Initialize the IPI handlers and start up the AP's. 316 */ 317void 318cpu_mp_start(void) 319{ 320 int i; 321 u_int threads_per_cache, p[4]; 322 323 /* Initialize the logical ID to APIC ID table. */ 324 for (i = 0; i < MAXCPU; i++) { 325 cpu_apic_ids[i] = -1; 326 cpu_ipi_pending[i] = 0; 327 } 328 329 /* Install an inter-CPU IPI for TLB invalidation */ 330 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 331 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 332 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 333 334 /* Install an inter-CPU IPI for cache invalidation. */ 335 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0); 336 337 /* Install an inter-CPU IPI for all-CPU rendezvous */ 338 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 339 340 /* Install generic inter-CPU IPI handler */ 341 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 342 SDT_SYSIGT, SEL_KPL, 0); 343 344 /* Install an inter-CPU IPI for CPU stop/restart */ 345 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 346 347 /* Install an inter-CPU IPI for CPU suspend/resume */ 348 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0); 349 350 /* Set boot_cpu_id if needed. */ 351 if (boot_cpu_id == -1) { 352 boot_cpu_id = PCPU_GET(apic_id); 353 cpu_info[boot_cpu_id].cpu_bsp = 1; 354 } else 355 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 356 ("BSP's APIC ID doesn't match boot_cpu_id")); 357 358 /* Setup the initial logical CPUs info. */ 359 logical_cpus = logical_cpus_mask = 0; 360 if (cpu_feature & CPUID_HTT) 361 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 362 363 /* 364 * Work out if hyperthreading is *really* enabled. This 365 * is made really ugly by the fact that processors lie: Dual 366 * core processors claim to be hyperthreaded even when they're 367 * not, presumably because they want to be treated the same 368 * way as HTT with respect to per-cpu software licensing. 369 * At the time of writing (May 12, 2005) the only hyperthreaded 370 * cpus are from Intel, and Intel's dual-core processors can be 371 * identified via the "deterministic cache parameters" cpuid 372 * calls. 373 */ 374 /* 375 * First determine if this is an Intel processor which claims 376 * to have hyperthreading support. 377 */ 378 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) { 379 /* 380 * If the "deterministic cache parameters" cpuid calls 381 * are available, use them. 382 */ 383 if (cpu_high >= 4) { 384 /* Ask the processor about the L1 cache. */ 385 for (i = 0; i < 1; i++) { 386 cpuid_count(4, i, p); 387 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 388 if (hyperthreading_cpus < threads_per_cache) 389 hyperthreading_cpus = threads_per_cache; 390 if ((p[0] & 0x1f) == 0) 391 break; 392 } 393 } 394 395 /* 396 * If the deterministic cache parameters are not 397 * available, or if no caches were reported to exist, 398 * just accept what the HTT flag indicated. 399 */ 400 if (hyperthreading_cpus == 0) 401 hyperthreading_cpus = logical_cpus; 402 } 403 404 assign_cpu_ids(); 405 406 /* Start each Application Processor */ 407 start_all_aps(); 408 409 set_interrupt_apic_ids(); 410} 411 412 413/* 414 * Print various information about the SMP system hardware and setup. 415 */ 416void 417cpu_mp_announce(void) 418{ 419 const char *hyperthread; 420 int i; 421 422 /* List active CPUs first. */ 423 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 424 for (i = 1; i < mp_ncpus; i++) { 425 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 426 hyperthread = "/HT"; 427 else 428 hyperthread = ""; 429 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 430 cpu_apic_ids[i]); 431 } 432 433 /* List disabled CPUs last. */ 434 for (i = 0; i <= MAX_APIC_ID; i++) { 435 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 436 continue; 437 if (cpu_info[i].cpu_hyperthread) 438 hyperthread = "/HT"; 439 else 440 hyperthread = ""; 441 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 442 i); 443 } 444} 445 446/* 447 * AP CPU's call this to initialize themselves. 448 */ 449void 450init_secondary(void) 451{ 452 struct pcpu *pc; 453 struct nmi_pcpu *np; 454 u_int64_t msr, cr0; 455 int cpu, gsel_tss, x; 456 struct region_descriptor ap_gdt; 457 458 /* Set by the startup code for us to use */ 459 cpu = bootAP; 460 461 /* Init tss */ 462 common_tss[cpu] = common_tss[0]; 463 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 464 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) + 465 IOPAGES * PAGE_SIZE; 466 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 467 468 /* The NMI stack runs on IST2. */ 469 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1; 470 common_tss[cpu].tss_ist2 = (long) np; 471 472 /* Prepare private GDT */ 473 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 474 for (x = 0; x < NGDT; x++) { 475 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 476 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1)) 477 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]); 478 } 479 ssdtosyssd(&gdt_segs[GPROC0_SEL], 480 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]); 481 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 482 ap_gdt.rd_base = (long) &gdt[NGDT * cpu]; 483 lgdt(&ap_gdt); /* does magic intra-segment return */ 484 485 /* Get per-cpu data */ 486 pc = &__pcpu[cpu]; 487 488 /* prime data page for it to use */ 489 pcpu_init(pc, cpu, sizeof(struct pcpu)); 490 pc->pc_apic_id = cpu_apic_ids[cpu]; 491 pc->pc_prvspace = pc; 492 pc->pc_curthread = 0; 493 pc->pc_tssp = &common_tss[cpu]; 494 pc->pc_commontssp = &common_tss[cpu]; 495 pc->pc_rsp0 = 0; 496 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu + 497 GPROC0_SEL]; 498 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL]; 499 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL]; 500 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu + 501 GUSERLDT_SEL]; 502 503 /* Save the per-cpu pointer for use by the NMI handler. */ 504 np->np_pcpu = (register_t) pc; 505 506 wrmsr(MSR_FSBASE, 0); /* User value */ 507 wrmsr(MSR_GSBASE, (u_int64_t)pc); 508 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 509 510 lidt(&r_idt); 511 512 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 513 ltr(gsel_tss); 514 515 /* 516 * Set to a known state: 517 * Set by mpboot.s: CR0_PG, CR0_PE 518 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 519 */ 520 cr0 = rcr0(); 521 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 522 load_cr0(cr0); 523 524 /* Set up the fast syscall stuff */ 525 msr = rdmsr(MSR_EFER) | EFER_SCE; 526 wrmsr(MSR_EFER, msr); 527 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 528 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 529 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 530 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 531 wrmsr(MSR_STAR, msr); 532 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 533 534 /* Disable local APIC just to be sure. */ 535 lapic_disable(); 536 537 /* signal our startup to the BSP. */ 538 mp_naps++; 539 540 /* Spin until the BSP releases the AP's. */ 541 while (!aps_ready) 542 ia32_pause(); 543 544 /* Initialize the PAT MSR. */ 545 pmap_init_pat(); 546 547 /* set up CPU registers and state */ 548 cpu_setregs(); 549 550 /* set up SSE/NX registers */ 551 initializecpu(); 552 553 /* set up FPU state on the AP */ 554 fpuinit(); 555 556 /* A quick check from sanity claus */ 557 if (PCPU_GET(apic_id) != lapic_id()) { 558 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 559 printf("SMP: actual apic_id = %d\n", lapic_id()); 560 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 561 panic("cpuid mismatch! boom!!"); 562 } 563 564 /* Initialize curthread. */ 565 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 566 PCPU_SET(curthread, PCPU_GET(idlethread)); 567 568 mtx_lock_spin(&ap_boot_mtx); 569 570 /* Init local apic for irq's */ 571 lapic_setup(1); 572 573 /* Set memory range attributes for this CPU to match the BSP */ 574 mem_range_AP_init(); 575 576 smp_cpus++; 577 578 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 579 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 580 581 /* Determine if we are a logical CPU. */ 582 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 583 logical_cpus_mask |= PCPU_GET(cpumask); 584 585 /* Determine if we are a hyperthread. */ 586 if (hyperthreading_cpus > 1 && 587 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 588 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 589 590 /* Build our map of 'other' CPUs. */ 591 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 592 593 if (bootverbose) 594 lapic_dump("AP"); 595 596 if (smp_cpus == mp_ncpus) { 597 /* enable IPI's, tlb shootdown, freezes etc */ 598 atomic_store_rel_int(&smp_started, 1); 599 smp_active = 1; /* historic */ 600 } 601 602 /* 603 * Enable global pages TLB extension 604 * This also implicitly flushes the TLB 605 */ 606 607 load_cr4(rcr4() | CR4_PGE); 608 load_ds(_udatasel); 609 load_es(_udatasel); 610 load_fs(_ufssel); 611 mtx_unlock_spin(&ap_boot_mtx); 612 613 /* wait until all the AP's are up */ 614 while (smp_started == 0) 615 ia32_pause(); 616 617 sched_throw(NULL); 618 619 panic("scheduler returned us to %s", __func__); 620 /* NOTREACHED */ 621} 622 623/******************************************************************* 624 * local functions and data 625 */ 626 627/* 628 * We tell the I/O APIC code about all the CPUs we want to receive 629 * interrupts. If we don't want certain CPUs to receive IRQs we 630 * can simply not tell the I/O APIC code about them in this function. 631 * We also do not tell it about the BSP since it tells itself about 632 * the BSP internally to work with UP kernels and on UP machines. 633 */ 634static void 635set_interrupt_apic_ids(void) 636{ 637 u_int i, apic_id; 638 639 for (i = 0; i < MAXCPU; i++) { 640 apic_id = cpu_apic_ids[i]; 641 if (apic_id == -1) 642 continue; 643 if (cpu_info[apic_id].cpu_bsp) 644 continue; 645 if (cpu_info[apic_id].cpu_disabled) 646 continue; 647 648 /* Don't let hyperthreads service interrupts. */ 649 if (hyperthreading_cpus > 1 && 650 apic_id % hyperthreading_cpus != 0) 651 continue; 652 653 intr_add_cpu(i); 654 } 655} 656 657/* 658 * Assign logical CPU IDs to local APICs. 659 */ 660static void 661assign_cpu_ids(void) 662{ 663 u_int i; 664 665 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 666 &hyperthreading_allowed); 667 668 /* Check for explicitly disabled CPUs. */ 669 for (i = 0; i <= MAX_APIC_ID; i++) { 670 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 671 continue; 672 673 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 674 cpu_info[i].cpu_hyperthread = 1; 675#if defined(SCHED_ULE) 676 /* 677 * Don't use HT CPU if it has been disabled by a 678 * tunable. 679 */ 680 if (hyperthreading_allowed == 0) { 681 cpu_info[i].cpu_disabled = 1; 682 continue; 683 } 684#endif 685 } 686 687 /* Don't use this CPU if it has been disabled by a tunable. */ 688 if (resource_disabled("lapic", i)) { 689 cpu_info[i].cpu_disabled = 1; 690 continue; 691 } 692 } 693 694 /* 695 * Assign CPU IDs to local APIC IDs and disable any CPUs 696 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 697 * 698 * To minimize confusion for userland, we attempt to number 699 * CPUs such that all threads and cores in a package are 700 * grouped together. For now we assume that the BSP is always 701 * the first thread in a package and just start adding APs 702 * starting with the BSP's APIC ID. 703 */ 704 mp_ncpus = 1; 705 cpu_apic_ids[0] = boot_cpu_id; 706 apic_cpuids[boot_cpu_id] = 0; 707 for (i = boot_cpu_id + 1; i != boot_cpu_id; 708 i == MAX_APIC_ID ? i = 0 : i++) { 709 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 710 cpu_info[i].cpu_disabled) 711 continue; 712 713 if (mp_ncpus < MAXCPU) { 714 cpu_apic_ids[mp_ncpus] = i; 715 apic_cpuids[i] = mp_ncpus; 716 mp_ncpus++; 717 } else 718 cpu_info[i].cpu_disabled = 1; 719 } 720 KASSERT(mp_maxid >= mp_ncpus - 1, 721 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 722 mp_ncpus)); 723} 724 725/* 726 * start each AP in our list 727 */ 728static int 729start_all_aps(void) 730{ 731 vm_offset_t va = boot_address + KERNBASE; 732 u_int64_t *pt4, *pt3, *pt2; 733 u_int32_t mpbioswarmvec; 734 int apic_id, cpu, i; 735 u_char mpbiosreason; 736 737 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 738 739 /* install the AP 1st level boot code */ 740 pmap_kenter(va, boot_address); 741 pmap_invalidate_page(kernel_pmap, va); 742 bcopy(mptramp_start, (void *)va, bootMP_size); 743 744 /* Locate the page tables, they'll be below the trampoline */ 745 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 746 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 747 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 748 749 /* Create the initial 1GB replicated page tables */ 750 for (i = 0; i < 512; i++) { 751 /* Each slot of the level 4 pages points to the same level 3 page */ 752 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 753 pt4[i] |= PG_V | PG_RW | PG_U; 754 755 /* Each slot of the level 3 pages points to the same level 2 page */ 756 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 757 pt3[i] |= PG_V | PG_RW | PG_U; 758 759 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 760 pt2[i] = i * (2 * 1024 * 1024); 761 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 762 } 763 764 /* save the current value of the warm-start vector */ 765 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 766 outb(CMOS_REG, BIOS_RESET); 767 mpbiosreason = inb(CMOS_DATA); 768 769 /* setup a vector to our boot code */ 770 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 771 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 772 outb(CMOS_REG, BIOS_RESET); 773 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 774 775 /* start each AP */ 776 for (cpu = 1; cpu < mp_ncpus; cpu++) { 777 apic_id = cpu_apic_ids[cpu]; 778 779 /* allocate and set up an idle stack data page */ 780 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 781 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 782 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 783 784 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 785 bootAP = cpu; 786 787 /* attempt to start the Application Processor */ 788 if (!start_ap(apic_id)) { 789 /* restore the warmstart vector */ 790 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 791 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 792 } 793 794 all_cpus |= (1 << cpu); /* record AP in CPU map */ 795 } 796 797 /* build our map of 'other' CPUs */ 798 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 799 800 /* restore the warmstart vector */ 801 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 802 803 outb(CMOS_REG, BIOS_RESET); 804 outb(CMOS_DATA, mpbiosreason); 805 806 /* number of APs actually started */ 807 return mp_naps; 808} 809 810 811/* 812 * This function starts the AP (application processor) identified 813 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 814 * to accomplish this. This is necessary because of the nuances 815 * of the different hardware we might encounter. It isn't pretty, 816 * but it seems to work. 817 */ 818static int 819start_ap(int apic_id) 820{ 821 int vector, ms; 822 int cpus; 823 824 /* calculate the vector */ 825 vector = (boot_address >> 12) & 0xff; 826 827 /* used as a watchpoint to signal AP startup */ 828 cpus = mp_naps; 829 830 /* 831 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 832 * and running the target CPU. OR this INIT IPI might be latched (P5 833 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 834 * ignored. 835 */ 836 837 /* do an INIT IPI: assert RESET */ 838 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 839 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 840 841 /* wait for pending status end */ 842 lapic_ipi_wait(-1); 843 844 /* do an INIT IPI: deassert RESET */ 845 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 846 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 847 848 /* wait for pending status end */ 849 DELAY(10000); /* wait ~10mS */ 850 lapic_ipi_wait(-1); 851 852 /* 853 * next we do a STARTUP IPI: the previous INIT IPI might still be 854 * latched, (P5 bug) this 1st STARTUP would then terminate 855 * immediately, and the previously started INIT IPI would continue. OR 856 * the previous INIT IPI has already run. and this STARTUP IPI will 857 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 858 * will run. 859 */ 860 861 /* do a STARTUP IPI */ 862 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 863 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 864 vector, apic_id); 865 lapic_ipi_wait(-1); 866 DELAY(200); /* wait ~200uS */ 867 868 /* 869 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 870 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 871 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 872 * recognized after hardware RESET or INIT IPI. 873 */ 874 875 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 876 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 877 vector, apic_id); 878 lapic_ipi_wait(-1); 879 DELAY(200); /* wait ~200uS */ 880 881 /* Wait up to 5 seconds for it to start. */ 882 for (ms = 0; ms < 5000; ms++) { 883 if (mp_naps > cpus) 884 return 1; /* return SUCCESS */ 885 DELAY(1000); 886 } 887 return 0; /* return FAILURE */ 888} 889 890/* 891 * Flush the TLB on all other CPU's 892 */ 893static void 894smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 895{ 896 u_int ncpu; 897 898 ncpu = mp_ncpus - 1; /* does not shootdown self */ 899 if (ncpu < 1) 900 return; /* no other cpus */ 901 if (!(read_rflags() & PSL_I)) 902 panic("%s: interrupts disabled", __func__); 903 mtx_lock_spin(&smp_ipi_mtx); 904 smp_tlb_addr1 = addr1; 905 smp_tlb_addr2 = addr2; 906 atomic_store_rel_int(&smp_tlb_wait, 0); 907 ipi_all_but_self(vector); 908 while (smp_tlb_wait < ncpu) 909 ia32_pause(); 910 mtx_unlock_spin(&smp_ipi_mtx); 911} 912 913static void 914smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 915{ 916 int ncpu, othercpus; 917 918 othercpus = mp_ncpus - 1; 919 if (mask == (u_int)-1) { 920 ncpu = othercpus; 921 if (ncpu < 1) 922 return; 923 } else { 924 mask &= ~PCPU_GET(cpumask); 925 if (mask == 0) 926 return; 927 ncpu = bitcount32(mask); 928 if (ncpu > othercpus) { 929 /* XXX this should be a panic offence */ 930 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 931 ncpu, othercpus); 932 ncpu = othercpus; 933 } 934 /* XXX should be a panic, implied by mask == 0 above */ 935 if (ncpu < 1) 936 return; 937 } 938 if (!(read_rflags() & PSL_I)) 939 panic("%s: interrupts disabled", __func__); 940 mtx_lock_spin(&smp_ipi_mtx); 941 smp_tlb_addr1 = addr1; 942 smp_tlb_addr2 = addr2; 943 atomic_store_rel_int(&smp_tlb_wait, 0); 944 if (mask == (u_int)-1) 945 ipi_all_but_self(vector); 946 else 947 ipi_selected(mask, vector); 948 while (smp_tlb_wait < ncpu) 949 ia32_pause(); 950 mtx_unlock_spin(&smp_ipi_mtx); 951} 952 953void 954smp_cache_flush(void) 955{ 956 957 if (smp_started) 958 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 959} 960 961void 962smp_invltlb(void) 963{ 964 965 if (smp_started) { 966 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 967 } 968} 969 970void 971smp_invlpg(vm_offset_t addr) 972{ 973 974 if (smp_started) 975 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 976} 977 978void 979smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 980{ 981 982 if (smp_started) { 983 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 984 } 985} 986 987void 988smp_masked_invltlb(u_int mask) 989{ 990 991 if (smp_started) { 992 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 993 } 994} 995 996void 997smp_masked_invlpg(u_int mask, vm_offset_t addr) 998{ 999 1000 if (smp_started) { 1001 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1002 } 1003} 1004 1005void 1006smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 1007{ 1008 1009 if (smp_started) { 1010 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1011 } 1012} 1013 1014void 1015ipi_bitmap_handler(struct trapframe frame) 1016{ 1017 int cpu = PCPU_GET(cpuid); 1018 u_int ipi_bitmap; 1019 1020 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1021 1022 if (ipi_bitmap & (1 << IPI_PREEMPT)) 1023 sched_preempt(curthread); 1024 1025 /* Nothing to do for AST */ 1026} 1027 1028/* 1029 * send an IPI to a set of cpus. 1030 */ 1031void 1032ipi_selected(u_int32_t cpus, u_int ipi) 1033{ 1034 int cpu; 1035 u_int bitmap = 0; 1036 u_int old_pending; 1037 u_int new_pending; 1038 1039 if (IPI_IS_BITMAPED(ipi)) { 1040 bitmap = 1 << ipi; 1041 ipi = IPI_BITMAP_VECTOR; 1042 } 1043 1044#ifdef STOP_NMI 1045 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1046 ipi_nmi_selected(cpus); 1047 return; 1048 } 1049#endif 1050 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1051 while ((cpu = ffs(cpus)) != 0) { 1052 cpu--; 1053 cpus &= ~(1 << cpu); 1054 1055 KASSERT(cpu_apic_ids[cpu] != -1, 1056 ("IPI to non-existent CPU %d", cpu)); 1057 1058 if (bitmap) { 1059 do { 1060 old_pending = cpu_ipi_pending[cpu]; 1061 new_pending = old_pending | bitmap; 1062 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1063 1064 if (old_pending) 1065 continue; 1066 } 1067 1068 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1069 } 1070 1071} 1072 1073/* 1074 * send an IPI to all CPUs EXCEPT myself 1075 */ 1076void 1077ipi_all_but_self(u_int ipi) 1078{ 1079 1080 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1081 ipi_selected(PCPU_GET(other_cpus), ipi); 1082 return; 1083 } 1084 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1085 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1086} 1087 1088#ifdef STOP_NMI 1089/* 1090 * send NMI IPI to selected CPUs 1091 */ 1092 1093#define BEFORE_SPIN 1000000 1094 1095void 1096ipi_nmi_selected(u_int32_t cpus) 1097{ 1098 int cpu; 1099 register_t icrlo; 1100 1101 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1102 | APIC_TRIGMOD_EDGE; 1103 1104 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1105 1106 atomic_set_int(&ipi_nmi_pending, cpus); 1107 1108 while ((cpu = ffs(cpus)) != 0) { 1109 cpu--; 1110 cpus &= ~(1 << cpu); 1111 1112 KASSERT(cpu_apic_ids[cpu] != -1, 1113 ("IPI NMI to non-existent CPU %d", cpu)); 1114 1115 /* Wait for an earlier IPI to finish. */ 1116 if (!lapic_ipi_wait(BEFORE_SPIN)) 1117 panic("ipi_nmi_selected: previous IPI has not cleared"); 1118 1119 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1120 } 1121} 1122 1123int 1124ipi_nmi_handler(void) 1125{ 1126 int cpumask = PCPU_GET(cpumask); 1127 1128 if (!(ipi_nmi_pending & cpumask)) 1129 return 1; 1130 1131 atomic_clear_int(&ipi_nmi_pending, cpumask); 1132 cpustop_handler(); 1133 return 0; 1134} 1135 1136#endif /* STOP_NMI */ 1137 1138/* 1139 * Handle an IPI_STOP by saving our current context and spinning until we 1140 * are resumed. 1141 */ 1142void 1143cpustop_handler(void) 1144{ 1145 int cpu = PCPU_GET(cpuid); 1146 int cpumask = PCPU_GET(cpumask); 1147 1148 savectx(&stoppcbs[cpu]); 1149 1150 /* Indicate that we are stopped */ 1151 atomic_set_int(&stopped_cpus, cpumask); 1152 1153 /* Wait for restart */ 1154 while (!(started_cpus & cpumask)) 1155 ia32_pause(); 1156 1157 atomic_clear_int(&started_cpus, cpumask); 1158 atomic_clear_int(&stopped_cpus, cpumask); 1159 1160 if (cpu == 0 && cpustop_restartfunc != NULL) { 1161 cpustop_restartfunc(); 1162 cpustop_restartfunc = NULL; 1163 } 1164} 1165 1166/* 1167 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1168 * are resumed. 1169 */ 1170void 1171cpususpend_handler(void) 1172{ 1173 struct savefpu *stopfpu; 1174 register_t cr3, rf; 1175 int cpu = PCPU_GET(cpuid); 1176 int cpumask = PCPU_GET(cpumask); 1177 1178 rf = intr_disable(); 1179 cr3 = rcr3(); 1180 stopfpu = &stopxpcbs[cpu].xpcb_pcb.pcb_save; 1181 if (savectx2(&stopxpcbs[cpu])) { 1182 fpugetregs(curthread, stopfpu); 1183 wbinvd(); 1184 atomic_set_int(&stopped_cpus, cpumask); 1185 } else 1186 fpusetregs(curthread, stopfpu); 1187 1188 /* Wait for resume */ 1189 while (!(started_cpus & cpumask)) 1190 ia32_pause(); 1191 1192 atomic_clear_int(&started_cpus, cpumask); 1193 atomic_clear_int(&stopped_cpus, cpumask); 1194 1195 /* Restore CR3 and enable interrupts */ 1196 load_cr3(cr3); 1197 lapic_setup(0); 1198 intr_restore(rf); 1199} 1200 1201/* 1202 * This is called once the rest of the system is up and running and we're 1203 * ready to let the AP's out of the pen. 1204 */ 1205static void 1206release_aps(void *dummy __unused) 1207{ 1208 1209 if (mp_ncpus == 1) 1210 return; 1211 atomic_store_rel_int(&aps_ready, 1); 1212 while (smp_started == 0) 1213 ia32_pause(); 1214} 1215SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1216 1217static int 1218sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1219{ 1220 u_int mask; 1221 int error; 1222 1223 mask = hlt_cpus_mask; 1224 error = sysctl_handle_int(oidp, &mask, 0, req); 1225 if (error || !req->newptr) 1226 return (error); 1227 1228 if (logical_cpus_mask != 0 && 1229 (mask & logical_cpus_mask) == logical_cpus_mask) 1230 hlt_logical_cpus = 1; 1231 else 1232 hlt_logical_cpus = 0; 1233 1234 if (! hyperthreading_allowed) 1235 mask |= hyperthreading_cpus_mask; 1236 1237 if ((mask & all_cpus) == all_cpus) 1238 mask &= ~(1<<0); 1239 hlt_cpus_mask = mask; 1240 return (error); 1241} 1242SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1243 0, 0, sysctl_hlt_cpus, "IU", 1244 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1245 1246static int 1247sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1248{ 1249 int disable, error; 1250 1251 disable = hlt_logical_cpus; 1252 error = sysctl_handle_int(oidp, &disable, 0, req); 1253 if (error || !req->newptr) 1254 return (error); 1255 1256 if (disable) 1257 hlt_cpus_mask |= logical_cpus_mask; 1258 else 1259 hlt_cpus_mask &= ~logical_cpus_mask; 1260 1261 if (! hyperthreading_allowed) 1262 hlt_cpus_mask |= hyperthreading_cpus_mask; 1263 1264 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1265 hlt_cpus_mask &= ~(1<<0); 1266 1267 hlt_logical_cpus = disable; 1268 return (error); 1269} 1270 1271static int 1272sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1273{ 1274 int allowed, error; 1275 1276 allowed = hyperthreading_allowed; 1277 error = sysctl_handle_int(oidp, &allowed, 0, req); 1278 if (error || !req->newptr) 1279 return (error); 1280 1281#ifdef SCHED_ULE 1282 /* 1283 * SCHED_ULE doesn't allow enabling/disabling HT cores at 1284 * run-time. 1285 */ 1286 if (allowed != hyperthreading_allowed) 1287 return (ENOTSUP); 1288 return (error); 1289#endif 1290 1291 if (allowed) 1292 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1293 else 1294 hlt_cpus_mask |= hyperthreading_cpus_mask; 1295 1296 if (logical_cpus_mask != 0 && 1297 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1298 hlt_logical_cpus = 1; 1299 else 1300 hlt_logical_cpus = 0; 1301 1302 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1303 hlt_cpus_mask &= ~(1<<0); 1304 1305 hyperthreading_allowed = allowed; 1306 return (error); 1307} 1308 1309static void 1310cpu_hlt_setup(void *dummy __unused) 1311{ 1312 1313 if (logical_cpus_mask != 0) { 1314 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1315 &hlt_logical_cpus); 1316 sysctl_ctx_init(&logical_cpu_clist); 1317 SYSCTL_ADD_PROC(&logical_cpu_clist, 1318 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1319 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1320 sysctl_hlt_logical_cpus, "IU", ""); 1321 SYSCTL_ADD_UINT(&logical_cpu_clist, 1322 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1323 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1324 &logical_cpus_mask, 0, ""); 1325 1326 if (hlt_logical_cpus) 1327 hlt_cpus_mask |= logical_cpus_mask; 1328 1329 /* 1330 * If necessary for security purposes, force 1331 * hyperthreading off, regardless of the value 1332 * of hlt_logical_cpus. 1333 */ 1334 if (hyperthreading_cpus_mask) { 1335 SYSCTL_ADD_PROC(&logical_cpu_clist, 1336 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1337 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1338 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1339 if (! hyperthreading_allowed) 1340 hlt_cpus_mask |= hyperthreading_cpus_mask; 1341 } 1342 } 1343} 1344SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1345 1346int 1347mp_grab_cpu_hlt(void) 1348{ 1349 u_int mask = PCPU_GET(cpumask); 1350#ifdef MP_WATCHDOG 1351 u_int cpuid = PCPU_GET(cpuid); 1352#endif 1353 int retval; 1354 1355#ifdef MP_WATCHDOG 1356 ap_watchdog(cpuid); 1357#endif 1358 1359 retval = mask & hlt_cpus_mask; 1360 while (mask & hlt_cpus_mask) 1361 __asm __volatile("sti; hlt" : : : "memory"); 1362 return (retval); 1363} 1364