mp_machdep.c revision 189903
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 189903 2009-03-17 00:48:11Z jkim $"); 29 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#ifdef GPROF 39#include <sys/gmon.h> 40#endif 41#include <sys/kernel.h> 42#include <sys/ktr.h> 43#include <sys/lock.h> 44#include <sys/malloc.h> 45#include <sys/memrange.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/sched.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52 53#include <vm/vm.h> 54#include <vm/vm_param.h> 55#include <vm/pmap.h> 56#include <vm/vm_kern.h> 57#include <vm/vm_extern.h> 58 59#include <machine/apicreg.h> 60#include <machine/cputypes.h> 61#include <machine/cpufunc.h> 62#include <machine/md_var.h> 63#include <machine/mp_watchdog.h> 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#include <machine/smp.h> 67#include <machine/specialreg.h> 68#include <machine/tss.h> 69 70#define WARMBOOT_TARGET 0 71#define WARMBOOT_OFF (KERNBASE + 0x0467) 72#define WARMBOOT_SEG (KERNBASE + 0x0469) 73 74#define CMOS_REG (0x70) 75#define CMOS_DATA (0x71) 76#define BIOS_RESET (0x0f) 77#define BIOS_WARM (0x0a) 78 79/* lock region used by kernel profiling */ 80int mcount_lock; 81 82int mp_naps; /* # of Applications processors */ 83int boot_cpu_id = -1; /* designated BSP */ 84 85extern struct pcpu __pcpu[]; 86 87/* AP uses this during bootstrap. Do not staticize. */ 88char *bootSTK; 89static int bootAP; 90 91/* Free these after use */ 92void *bootstacks[MAXCPU]; 93 94/* Temporary holder for double fault stack */ 95char *doublefault_stack; 96char *nmi_stack; 97 98/* Hotwire a 0->4MB V==P mapping */ 99extern pt_entry_t *KPTphys; 100 101/* SMP page table page */ 102extern pt_entry_t *SMPpt; 103 104extern int _udatasel; 105 106struct pcb stoppcbs[MAXCPU]; 107struct xpcb *stopxpcbs = NULL; 108 109/* Variables needed for SMP tlb shootdown. */ 110vm_offset_t smp_tlb_addr1; 111vm_offset_t smp_tlb_addr2; 112volatile int smp_tlb_wait; 113 114extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 115 116#ifdef STOP_NMI 117volatile cpumask_t ipi_nmi_pending; 118 119static void ipi_nmi_selected(u_int32_t cpus); 120#endif 121 122/* 123 * Local data and functions. 124 */ 125 126#ifdef STOP_NMI 127/* 128 * Provide an alternate method of stopping other CPUs. If another CPU has 129 * disabled interrupts the conventional STOP IPI will be blocked. This 130 * NMI-based stop should get through in that case. 131 */ 132static int stop_cpus_with_nmi = 1; 133SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 134 &stop_cpus_with_nmi, 0, ""); 135TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 136#else 137#define stop_cpus_with_nmi 0 138#endif 139 140static u_int logical_cpus; 141 142/* used to hold the AP's until we are ready to release them */ 143static struct mtx ap_boot_mtx; 144 145/* Set to 1 once we're ready to let the APs out of the pen. */ 146static volatile int aps_ready = 0; 147 148/* 149 * Store data from cpu_add() until later in the boot when we actually setup 150 * the APs. 151 */ 152struct cpu_info { 153 int cpu_present:1; 154 int cpu_bsp:1; 155 int cpu_disabled:1; 156 int cpu_hyperthread:1; 157} static cpu_info[MAX_APIC_ID + 1]; 158int cpu_apic_ids[MAXCPU]; 159int apic_cpuids[MAX_APIC_ID + 1]; 160 161/* Holds pending bitmap based IPIs per CPU */ 162static volatile u_int cpu_ipi_pending[MAXCPU]; 163 164static u_int boot_address; 165 166static void assign_cpu_ids(void); 167static void set_interrupt_apic_ids(void); 168static int start_all_aps(void); 169static int start_ap(int apic_id); 170static void release_aps(void *dummy); 171 172static int hlt_logical_cpus; 173static u_int hyperthreading_cpus; 174static cpumask_t hyperthreading_cpus_mask; 175static int hyperthreading_allowed = 1; 176static struct sysctl_ctx_list logical_cpu_clist; 177static u_int bootMP_size; 178 179static void 180mem_range_AP_init(void) 181{ 182 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 183 mem_range_softc.mr_op->initAP(&mem_range_softc); 184} 185 186struct cpu_group * 187cpu_topo(void) 188{ 189 if (cpu_cores == 0) 190 cpu_cores = 1; 191 if (cpu_logical == 0) 192 cpu_logical = 1; 193 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 194 printf("WARNING: Non-uniform processors.\n"); 195 printf("WARNING: Using suboptimal topology.\n"); 196 return (smp_topo_none()); 197 } 198 /* 199 * No multi-core or hyper-threaded. 200 */ 201 if (cpu_logical * cpu_cores == 1) 202 return (smp_topo_none()); 203 /* 204 * Only HTT no multi-core. 205 */ 206 if (cpu_logical > 1 && cpu_cores == 1) 207 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 208 /* 209 * Only multi-core no HTT. 210 */ 211 if (cpu_cores > 1 && cpu_logical == 1) 212 return (smp_topo_1level(CG_SHARE_NONE, cpu_cores, 0)); 213 /* 214 * Both HTT and multi-core. 215 */ 216 return (smp_topo_2level(CG_SHARE_NONE, cpu_cores, 217 CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 218} 219 220/* 221 * Calculate usable address in base memory for AP trampoline code. 222 */ 223u_int 224mp_bootaddress(u_int basemem) 225{ 226 227 bootMP_size = mptramp_end - mptramp_start; 228 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 229 if (((basemem * 1024) - boot_address) < bootMP_size) 230 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 231 /* 3 levels of page table pages */ 232 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 233 234 return mptramp_pagetables; 235} 236 237void 238cpu_add(u_int apic_id, char boot_cpu) 239{ 240 241 if (apic_id > MAX_APIC_ID) { 242 panic("SMP: APIC ID %d too high", apic_id); 243 return; 244 } 245 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 246 apic_id)); 247 cpu_info[apic_id].cpu_present = 1; 248 if (boot_cpu) { 249 KASSERT(boot_cpu_id == -1, 250 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 251 boot_cpu_id)); 252 boot_cpu_id = apic_id; 253 cpu_info[apic_id].cpu_bsp = 1; 254 } 255 if (mp_ncpus < MAXCPU) { 256 mp_ncpus++; 257 mp_maxid = mp_ncpus -1; 258 } 259 if (bootverbose) 260 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 261 "AP"); 262} 263 264void 265cpu_mp_setmaxid(void) 266{ 267 268 /* 269 * mp_maxid should be already set by calls to cpu_add(). 270 * Just sanity check its value here. 271 */ 272 if (mp_ncpus == 0) 273 KASSERT(mp_maxid == 0, 274 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 275 else if (mp_ncpus == 1) 276 mp_maxid = 0; 277 else 278 KASSERT(mp_maxid >= mp_ncpus - 1, 279 ("%s: counters out of sync: max %d, count %d", __func__, 280 mp_maxid, mp_ncpus)); 281} 282 283int 284cpu_mp_probe(void) 285{ 286 287 /* 288 * Always record BSP in CPU map so that the mbuf init code works 289 * correctly. 290 */ 291 all_cpus = 1; 292 if (mp_ncpus == 0) { 293 /* 294 * No CPUs were found, so this must be a UP system. Setup 295 * the variables to represent a system with a single CPU 296 * with an id of 0. 297 */ 298 mp_ncpus = 1; 299 return (0); 300 } 301 302 /* At least one CPU was found. */ 303 if (mp_ncpus == 1) { 304 /* 305 * One CPU was found, so this must be a UP system with 306 * an I/O APIC. 307 */ 308 mp_maxid = 0; 309 return (0); 310 } 311 312 /* At least two CPUs were found. */ 313 return (1); 314} 315 316/* 317 * Initialize the IPI handlers and start up the AP's. 318 */ 319void 320cpu_mp_start(void) 321{ 322 int i; 323 u_int threads_per_cache, p[4]; 324 325 /* Initialize the logical ID to APIC ID table. */ 326 for (i = 0; i < MAXCPU; i++) { 327 cpu_apic_ids[i] = -1; 328 cpu_ipi_pending[i] = 0; 329 } 330 331 /* Install an inter-CPU IPI for TLB invalidation */ 332 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 333 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 334 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 335 336 /* Install an inter-CPU IPI for cache invalidation. */ 337 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0); 338 339 /* Install an inter-CPU IPI for all-CPU rendezvous */ 340 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 341 342 /* Install generic inter-CPU IPI handler */ 343 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 344 SDT_SYSIGT, SEL_KPL, 0); 345 346 /* Install an inter-CPU IPI for CPU stop/restart */ 347 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 348 349 /* Install an inter-CPU IPI for CPU suspend/resume */ 350 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0); 351 352 /* Set boot_cpu_id if needed. */ 353 if (boot_cpu_id == -1) { 354 boot_cpu_id = PCPU_GET(apic_id); 355 cpu_info[boot_cpu_id].cpu_bsp = 1; 356 } else 357 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 358 ("BSP's APIC ID doesn't match boot_cpu_id")); 359 cpu_apic_ids[0] = boot_cpu_id; 360 apic_cpuids[boot_cpu_id] = 0; 361 362 /* Setup the initial logical CPUs info. */ 363 logical_cpus = logical_cpus_mask = 0; 364 if (cpu_feature & CPUID_HTT) 365 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 366 367 /* 368 * Work out if hyperthreading is *really* enabled. This 369 * is made really ugly by the fact that processors lie: Dual 370 * core processors claim to be hyperthreaded even when they're 371 * not, presumably because they want to be treated the same 372 * way as HTT with respect to per-cpu software licensing. 373 * At the time of writing (May 12, 2005) the only hyperthreaded 374 * cpus are from Intel, and Intel's dual-core processors can be 375 * identified via the "deterministic cache parameters" cpuid 376 * calls. 377 */ 378 /* 379 * First determine if this is an Intel processor which claims 380 * to have hyperthreading support. 381 */ 382 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) { 383 /* 384 * If the "deterministic cache parameters" cpuid calls 385 * are available, use them. 386 */ 387 if (cpu_high >= 4) { 388 /* Ask the processor about the L1 cache. */ 389 for (i = 0; i < 1; i++) { 390 cpuid_count(4, i, p); 391 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 392 if (hyperthreading_cpus < threads_per_cache) 393 hyperthreading_cpus = threads_per_cache; 394 if ((p[0] & 0x1f) == 0) 395 break; 396 } 397 } 398 399 /* 400 * If the deterministic cache parameters are not 401 * available, or if no caches were reported to exist, 402 * just accept what the HTT flag indicated. 403 */ 404 if (hyperthreading_cpus == 0) 405 hyperthreading_cpus = logical_cpus; 406 } 407 408 assign_cpu_ids(); 409 410 /* Start each Application Processor */ 411 start_all_aps(); 412 413 set_interrupt_apic_ids(); 414} 415 416 417/* 418 * Print various information about the SMP system hardware and setup. 419 */ 420void 421cpu_mp_announce(void) 422{ 423 int i, x; 424 const char *hyperthread; 425 426 /* List CPUs */ 427 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 428 for (i = 1, x = 0; x <= MAX_APIC_ID; x++) { 429 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 430 continue; 431 if (cpu_info[x].cpu_hyperthread) { 432 hyperthread = "/HT"; 433 } else { 434 hyperthread = ""; 435 } 436 if (cpu_info[x].cpu_disabled) 437 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", 438 hyperthread, x); 439 else { 440 KASSERT(i < mp_ncpus, 441 ("mp_ncpus and actual cpus are out of whack")); 442 printf(" cpu%d (AP%s): APIC ID: %2d\n", i++, 443 hyperthread, x); 444 } 445 } 446} 447 448/* 449 * AP CPU's call this to initialize themselves. 450 */ 451void 452init_secondary(void) 453{ 454 struct pcpu *pc; 455 struct nmi_pcpu *np; 456 u_int64_t msr, cr0; 457 int cpu, gsel_tss, x; 458 struct region_descriptor ap_gdt; 459 460 /* Set by the startup code for us to use */ 461 cpu = bootAP; 462 463 /* Init tss */ 464 common_tss[cpu] = common_tss[0]; 465 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 466 common_tss[cpu].tss_iobase = sizeof(struct amd64tss); 467 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 468 469 /* The NMI stack runs on IST2. */ 470 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1; 471 common_tss[cpu].tss_ist2 = (long) np; 472 473 /* Prepare private GDT */ 474 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 475 ssdtosyssd(&gdt_segs[GPROC0_SEL], 476 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]); 477 for (x = 0; x < NGDT; x++) { 478 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 479 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]); 480 } 481 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 482 ap_gdt.rd_base = (long) &gdt[NGDT * cpu]; 483 lgdt(&ap_gdt); /* does magic intra-segment return */ 484 485 /* Get per-cpu data */ 486 pc = &__pcpu[cpu]; 487 488 /* prime data page for it to use */ 489 pcpu_init(pc, cpu, sizeof(struct pcpu)); 490 pc->pc_apic_id = cpu_apic_ids[cpu]; 491 pc->pc_prvspace = pc; 492 pc->pc_curthread = 0; 493 pc->pc_tssp = &common_tss[cpu]; 494 pc->pc_rsp0 = 0; 495 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL]; 496 497 /* Save the per-cpu pointer for use by the NMI handler. */ 498 np->np_pcpu = (register_t) pc; 499 500 wrmsr(MSR_FSBASE, 0); /* User value */ 501 wrmsr(MSR_GSBASE, (u_int64_t)pc); 502 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 503 504 lidt(&r_idt); 505 506 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 507 ltr(gsel_tss); 508 509 /* 510 * Set to a known state: 511 * Set by mpboot.s: CR0_PG, CR0_PE 512 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 513 */ 514 cr0 = rcr0(); 515 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 516 load_cr0(cr0); 517 518 /* Set up the fast syscall stuff */ 519 msr = rdmsr(MSR_EFER) | EFER_SCE; 520 wrmsr(MSR_EFER, msr); 521 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 522 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 523 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 524 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 525 wrmsr(MSR_STAR, msr); 526 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 527 528 /* Disable local APIC just to be sure. */ 529 lapic_disable(); 530 531 /* signal our startup to the BSP. */ 532 mp_naps++; 533 534 /* Spin until the BSP releases the AP's. */ 535 while (!aps_ready) 536 ia32_pause(); 537 538 /* Initialize the PAT MSR. */ 539 pmap_init_pat(); 540 541 /* set up CPU registers and state */ 542 cpu_setregs(); 543 544 /* set up SSE/NX registers */ 545 initializecpu(); 546 547 /* set up FPU state on the AP */ 548 fpuinit(); 549 550 /* A quick check from sanity claus */ 551 if (PCPU_GET(apic_id) != lapic_id()) { 552 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 553 printf("SMP: actual apic_id = %d\n", lapic_id()); 554 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 555 panic("cpuid mismatch! boom!!"); 556 } 557 558 /* Initialize curthread. */ 559 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 560 PCPU_SET(curthread, PCPU_GET(idlethread)); 561 562 mtx_lock_spin(&ap_boot_mtx); 563 564 /* Init local apic for irq's */ 565 lapic_setup(1); 566 567 /* Set memory range attributes for this CPU to match the BSP */ 568 mem_range_AP_init(); 569 570 smp_cpus++; 571 572 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 573 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 574 575 /* Determine if we are a logical CPU. */ 576 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 577 logical_cpus_mask |= PCPU_GET(cpumask); 578 579 /* Determine if we are a hyperthread. */ 580 if (hyperthreading_cpus > 1 && 581 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 582 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 583 584 /* Build our map of 'other' CPUs. */ 585 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 586 587 if (bootverbose) 588 lapic_dump("AP"); 589 590 if (smp_cpus == mp_ncpus) { 591 /* enable IPI's, tlb shootdown, freezes etc */ 592 atomic_store_rel_int(&smp_started, 1); 593 smp_active = 1; /* historic */ 594 } 595 596 /* 597 * Enable global pages TLB extension 598 * This also implicitly flushes the TLB 599 */ 600 601 load_cr4(rcr4() | CR4_PGE); 602 load_ds(_udatasel); 603 load_es(_udatasel); 604 load_fs(_udatasel); 605 mtx_unlock_spin(&ap_boot_mtx); 606 607 /* wait until all the AP's are up */ 608 while (smp_started == 0) 609 ia32_pause(); 610 611 sched_throw(NULL); 612 613 panic("scheduler returned us to %s", __func__); 614 /* NOTREACHED */ 615} 616 617/******************************************************************* 618 * local functions and data 619 */ 620 621/* 622 * We tell the I/O APIC code about all the CPUs we want to receive 623 * interrupts. If we don't want certain CPUs to receive IRQs we 624 * can simply not tell the I/O APIC code about them in this function. 625 * We also do not tell it about the BSP since it tells itself about 626 * the BSP internally to work with UP kernels and on UP machines. 627 */ 628static void 629set_interrupt_apic_ids(void) 630{ 631 u_int i, apic_id; 632 633 for (i = 0; i < MAXCPU; i++) { 634 apic_id = cpu_apic_ids[i]; 635 if (apic_id == -1) 636 continue; 637 if (cpu_info[apic_id].cpu_bsp) 638 continue; 639 if (cpu_info[apic_id].cpu_disabled) 640 continue; 641 642 /* Don't let hyperthreads service interrupts. */ 643 if (hyperthreading_cpus > 1 && 644 apic_id % hyperthreading_cpus != 0) 645 continue; 646 647 intr_add_cpu(i); 648 } 649} 650 651/* 652 * Assign logical CPU IDs to local APICs. 653 */ 654static void 655assign_cpu_ids(void) 656{ 657 u_int i; 658 659 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 660 &hyperthreading_allowed); 661 662 /* Check for explicitly disabled CPUs. */ 663 for (i = 0; i <= MAX_APIC_ID; i++) { 664 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 665 continue; 666 667 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 668 cpu_info[i].cpu_hyperthread = 1; 669#if defined(SCHED_ULE) 670 /* 671 * Don't use HT CPU if it has been disabled by a 672 * tunable. 673 */ 674 if (hyperthreading_allowed == 0) { 675 cpu_info[i].cpu_disabled = 1; 676 continue; 677 } 678#endif 679 } 680 681 /* Don't use this CPU if it has been disabled by a tunable. */ 682 if (resource_disabled("lapic", i)) { 683 cpu_info[i].cpu_disabled = 1; 684 continue; 685 } 686 } 687 688 /* 689 * Assign CPU IDs to local APIC IDs and disable any CPUs 690 * beyond MAXCPU. CPU 0 has already been assigned to the BSP, 691 * so we only have to assign IDs for APs. 692 */ 693 mp_ncpus = 1; 694 for (i = 0; i <= MAX_APIC_ID; i++) { 695 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 696 cpu_info[i].cpu_disabled) 697 continue; 698 699 if (mp_ncpus < MAXCPU) { 700 cpu_apic_ids[mp_ncpus] = i; 701 apic_cpuids[i] = mp_ncpus; 702 mp_ncpus++; 703 } else 704 cpu_info[i].cpu_disabled = 1; 705 } 706 KASSERT(mp_maxid >= mp_ncpus - 1, 707 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 708 mp_ncpus)); 709} 710 711/* 712 * start each AP in our list 713 */ 714static int 715start_all_aps(void) 716{ 717 vm_offset_t va = boot_address + KERNBASE; 718 u_int64_t *pt4, *pt3, *pt2; 719 u_int32_t mpbioswarmvec; 720 int apic_id, cpu, i; 721 u_char mpbiosreason; 722 723 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 724 725 /* install the AP 1st level boot code */ 726 pmap_kenter(va, boot_address); 727 pmap_invalidate_page(kernel_pmap, va); 728 bcopy(mptramp_start, (void *)va, bootMP_size); 729 730 /* Locate the page tables, they'll be below the trampoline */ 731 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 732 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 733 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 734 735 /* Create the initial 1GB replicated page tables */ 736 for (i = 0; i < 512; i++) { 737 /* Each slot of the level 4 pages points to the same level 3 page */ 738 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 739 pt4[i] |= PG_V | PG_RW | PG_U; 740 741 /* Each slot of the level 3 pages points to the same level 2 page */ 742 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 743 pt3[i] |= PG_V | PG_RW | PG_U; 744 745 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 746 pt2[i] = i * (2 * 1024 * 1024); 747 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 748 } 749 750 /* save the current value of the warm-start vector */ 751 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 752 outb(CMOS_REG, BIOS_RESET); 753 mpbiosreason = inb(CMOS_DATA); 754 755 /* setup a vector to our boot code */ 756 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 757 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 758 outb(CMOS_REG, BIOS_RESET); 759 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 760 761 /* start each AP */ 762 for (cpu = 1; cpu < mp_ncpus; cpu++) { 763 apic_id = cpu_apic_ids[cpu]; 764 765 /* allocate and set up an idle stack data page */ 766 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 767 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 768 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 769 770 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 771 bootAP = cpu; 772 773 /* attempt to start the Application Processor */ 774 if (!start_ap(apic_id)) { 775 /* restore the warmstart vector */ 776 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 777 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 778 } 779 780 all_cpus |= (1 << cpu); /* record AP in CPU map */ 781 } 782 783 /* build our map of 'other' CPUs */ 784 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 785 786 /* restore the warmstart vector */ 787 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 788 789 outb(CMOS_REG, BIOS_RESET); 790 outb(CMOS_DATA, mpbiosreason); 791 792 /* number of APs actually started */ 793 return mp_naps; 794} 795 796 797/* 798 * This function starts the AP (application processor) identified 799 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 800 * to accomplish this. This is necessary because of the nuances 801 * of the different hardware we might encounter. It isn't pretty, 802 * but it seems to work. 803 */ 804static int 805start_ap(int apic_id) 806{ 807 int vector, ms; 808 int cpus; 809 810 /* calculate the vector */ 811 vector = (boot_address >> 12) & 0xff; 812 813 /* used as a watchpoint to signal AP startup */ 814 cpus = mp_naps; 815 816 /* 817 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 818 * and running the target CPU. OR this INIT IPI might be latched (P5 819 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 820 * ignored. 821 */ 822 823 /* do an INIT IPI: assert RESET */ 824 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 825 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 826 827 /* wait for pending status end */ 828 lapic_ipi_wait(-1); 829 830 /* do an INIT IPI: deassert RESET */ 831 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 832 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 833 834 /* wait for pending status end */ 835 DELAY(10000); /* wait ~10mS */ 836 lapic_ipi_wait(-1); 837 838 /* 839 * next we do a STARTUP IPI: the previous INIT IPI might still be 840 * latched, (P5 bug) this 1st STARTUP would then terminate 841 * immediately, and the previously started INIT IPI would continue. OR 842 * the previous INIT IPI has already run. and this STARTUP IPI will 843 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 844 * will run. 845 */ 846 847 /* do a STARTUP IPI */ 848 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 849 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 850 vector, apic_id); 851 lapic_ipi_wait(-1); 852 DELAY(200); /* wait ~200uS */ 853 854 /* 855 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 856 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 857 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 858 * recognized after hardware RESET or INIT IPI. 859 */ 860 861 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 862 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 863 vector, apic_id); 864 lapic_ipi_wait(-1); 865 DELAY(200); /* wait ~200uS */ 866 867 /* Wait up to 5 seconds for it to start. */ 868 for (ms = 0; ms < 5000; ms++) { 869 if (mp_naps > cpus) 870 return 1; /* return SUCCESS */ 871 DELAY(1000); 872 } 873 return 0; /* return FAILURE */ 874} 875 876/* 877 * Flush the TLB on all other CPU's 878 */ 879static void 880smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 881{ 882 u_int ncpu; 883 884 ncpu = mp_ncpus - 1; /* does not shootdown self */ 885 if (ncpu < 1) 886 return; /* no other cpus */ 887 if (!(read_rflags() & PSL_I)) 888 panic("%s: interrupts disabled", __func__); 889 mtx_lock_spin(&smp_ipi_mtx); 890 smp_tlb_addr1 = addr1; 891 smp_tlb_addr2 = addr2; 892 atomic_store_rel_int(&smp_tlb_wait, 0); 893 ipi_all_but_self(vector); 894 while (smp_tlb_wait < ncpu) 895 ia32_pause(); 896 mtx_unlock_spin(&smp_ipi_mtx); 897} 898 899static void 900smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 901{ 902 int ncpu, othercpus; 903 904 othercpus = mp_ncpus - 1; 905 if (mask == (u_int)-1) { 906 ncpu = othercpus; 907 if (ncpu < 1) 908 return; 909 } else { 910 mask &= ~PCPU_GET(cpumask); 911 if (mask == 0) 912 return; 913 ncpu = bitcount32(mask); 914 if (ncpu > othercpus) { 915 /* XXX this should be a panic offence */ 916 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 917 ncpu, othercpus); 918 ncpu = othercpus; 919 } 920 /* XXX should be a panic, implied by mask == 0 above */ 921 if (ncpu < 1) 922 return; 923 } 924 if (!(read_rflags() & PSL_I)) 925 panic("%s: interrupts disabled", __func__); 926 mtx_lock_spin(&smp_ipi_mtx); 927 smp_tlb_addr1 = addr1; 928 smp_tlb_addr2 = addr2; 929 atomic_store_rel_int(&smp_tlb_wait, 0); 930 if (mask == (u_int)-1) 931 ipi_all_but_self(vector); 932 else 933 ipi_selected(mask, vector); 934 while (smp_tlb_wait < ncpu) 935 ia32_pause(); 936 mtx_unlock_spin(&smp_ipi_mtx); 937} 938 939void 940smp_cache_flush(void) 941{ 942 943 if (smp_started) 944 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 945} 946 947void 948smp_invltlb(void) 949{ 950 951 if (smp_started) { 952 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 953 } 954} 955 956void 957smp_invlpg(vm_offset_t addr) 958{ 959 960 if (smp_started) 961 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 962} 963 964void 965smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 966{ 967 968 if (smp_started) { 969 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 970 } 971} 972 973void 974smp_masked_invltlb(u_int mask) 975{ 976 977 if (smp_started) { 978 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 979 } 980} 981 982void 983smp_masked_invlpg(u_int mask, vm_offset_t addr) 984{ 985 986 if (smp_started) { 987 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 988 } 989} 990 991void 992smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 993{ 994 995 if (smp_started) { 996 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 997 } 998} 999 1000void 1001ipi_bitmap_handler(struct trapframe frame) 1002{ 1003 int cpu = PCPU_GET(cpuid); 1004 u_int ipi_bitmap; 1005 1006 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1007 1008 if (ipi_bitmap & (1 << IPI_PREEMPT)) 1009 sched_preempt(curthread); 1010 1011 /* Nothing to do for AST */ 1012} 1013 1014/* 1015 * send an IPI to a set of cpus. 1016 */ 1017void 1018ipi_selected(u_int32_t cpus, u_int ipi) 1019{ 1020 int cpu; 1021 u_int bitmap = 0; 1022 u_int old_pending; 1023 u_int new_pending; 1024 1025 if (IPI_IS_BITMAPED(ipi)) { 1026 bitmap = 1 << ipi; 1027 ipi = IPI_BITMAP_VECTOR; 1028 } 1029 1030#ifdef STOP_NMI 1031 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1032 ipi_nmi_selected(cpus); 1033 return; 1034 } 1035#endif 1036 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1037 while ((cpu = ffs(cpus)) != 0) { 1038 cpu--; 1039 cpus &= ~(1 << cpu); 1040 1041 KASSERT(cpu_apic_ids[cpu] != -1, 1042 ("IPI to non-existent CPU %d", cpu)); 1043 1044 if (bitmap) { 1045 do { 1046 old_pending = cpu_ipi_pending[cpu]; 1047 new_pending = old_pending | bitmap; 1048 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1049 1050 if (old_pending) 1051 continue; 1052 } 1053 1054 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1055 } 1056 1057} 1058 1059/* 1060 * send an IPI to all CPUs EXCEPT myself 1061 */ 1062void 1063ipi_all_but_self(u_int ipi) 1064{ 1065 1066 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1067 ipi_selected(PCPU_GET(other_cpus), ipi); 1068 return; 1069 } 1070 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1071 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1072} 1073 1074#ifdef STOP_NMI 1075/* 1076 * send NMI IPI to selected CPUs 1077 */ 1078 1079#define BEFORE_SPIN 1000000 1080 1081void 1082ipi_nmi_selected(u_int32_t cpus) 1083{ 1084 int cpu; 1085 register_t icrlo; 1086 1087 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1088 | APIC_TRIGMOD_EDGE; 1089 1090 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1091 1092 atomic_set_int(&ipi_nmi_pending, cpus); 1093 1094 while ((cpu = ffs(cpus)) != 0) { 1095 cpu--; 1096 cpus &= ~(1 << cpu); 1097 1098 KASSERT(cpu_apic_ids[cpu] != -1, 1099 ("IPI NMI to non-existent CPU %d", cpu)); 1100 1101 /* Wait for an earlier IPI to finish. */ 1102 if (!lapic_ipi_wait(BEFORE_SPIN)) 1103 panic("ipi_nmi_selected: previous IPI has not cleared"); 1104 1105 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1106 } 1107} 1108 1109int 1110ipi_nmi_handler(void) 1111{ 1112 int cpumask = PCPU_GET(cpumask); 1113 1114 if (!(ipi_nmi_pending & cpumask)) 1115 return 1; 1116 1117 atomic_clear_int(&ipi_nmi_pending, cpumask); 1118 cpustop_handler(); 1119 return 0; 1120} 1121 1122#endif /* STOP_NMI */ 1123 1124/* 1125 * Handle an IPI_STOP by saving our current context and spinning until we 1126 * are resumed. 1127 */ 1128void 1129cpustop_handler(void) 1130{ 1131 int cpu = PCPU_GET(cpuid); 1132 int cpumask = PCPU_GET(cpumask); 1133 1134 savectx(&stoppcbs[cpu]); 1135 1136 /* Indicate that we are stopped */ 1137 atomic_set_int(&stopped_cpus, cpumask); 1138 1139 /* Wait for restart */ 1140 while (!(started_cpus & cpumask)) 1141 ia32_pause(); 1142 1143 atomic_clear_int(&started_cpus, cpumask); 1144 atomic_clear_int(&stopped_cpus, cpumask); 1145 1146 if (cpu == 0 && cpustop_restartfunc != NULL) { 1147 cpustop_restartfunc(); 1148 cpustop_restartfunc = NULL; 1149 } 1150} 1151 1152/* 1153 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1154 * are resumed. 1155 */ 1156void 1157cpususpend_handler(void) 1158{ 1159 struct savefpu *stopfpu; 1160 register_t cr3, rf; 1161 int cpu = PCPU_GET(cpuid); 1162 int cpumask = PCPU_GET(cpumask); 1163 1164 rf = intr_disable(); 1165 cr3 = rcr3(); 1166 stopfpu = &stopxpcbs[cpu].xpcb_pcb.pcb_save; 1167 if (savectx2(&stopxpcbs[cpu])) { 1168 fpugetregs(curthread, stopfpu); 1169 wbinvd(); 1170 atomic_set_int(&stopped_cpus, cpumask); 1171 } else 1172 fpusetregs(curthread, stopfpu); 1173 1174 /* Wait for resume */ 1175 while (!(started_cpus & cpumask)) 1176 ia32_pause(); 1177 1178 atomic_clear_int(&started_cpus, cpumask); 1179 atomic_clear_int(&stopped_cpus, cpumask); 1180 1181 /* Restore CR3 and enable interrupts */ 1182 load_cr3(cr3); 1183 lapic_setup(0); 1184 intr_restore(rf); 1185} 1186 1187/* 1188 * This is called once the rest of the system is up and running and we're 1189 * ready to let the AP's out of the pen. 1190 */ 1191static void 1192release_aps(void *dummy __unused) 1193{ 1194 1195 if (mp_ncpus == 1) 1196 return; 1197 atomic_store_rel_int(&aps_ready, 1); 1198 while (smp_started == 0) 1199 ia32_pause(); 1200} 1201SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1202 1203static int 1204sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1205{ 1206 u_int mask; 1207 int error; 1208 1209 mask = hlt_cpus_mask; 1210 error = sysctl_handle_int(oidp, &mask, 0, req); 1211 if (error || !req->newptr) 1212 return (error); 1213 1214 if (logical_cpus_mask != 0 && 1215 (mask & logical_cpus_mask) == logical_cpus_mask) 1216 hlt_logical_cpus = 1; 1217 else 1218 hlt_logical_cpus = 0; 1219 1220 if (! hyperthreading_allowed) 1221 mask |= hyperthreading_cpus_mask; 1222 1223 if ((mask & all_cpus) == all_cpus) 1224 mask &= ~(1<<0); 1225 hlt_cpus_mask = mask; 1226 return (error); 1227} 1228SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1229 0, 0, sysctl_hlt_cpus, "IU", 1230 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1231 1232static int 1233sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1234{ 1235 int disable, error; 1236 1237 disable = hlt_logical_cpus; 1238 error = sysctl_handle_int(oidp, &disable, 0, req); 1239 if (error || !req->newptr) 1240 return (error); 1241 1242 if (disable) 1243 hlt_cpus_mask |= logical_cpus_mask; 1244 else 1245 hlt_cpus_mask &= ~logical_cpus_mask; 1246 1247 if (! hyperthreading_allowed) 1248 hlt_cpus_mask |= hyperthreading_cpus_mask; 1249 1250 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1251 hlt_cpus_mask &= ~(1<<0); 1252 1253 hlt_logical_cpus = disable; 1254 return (error); 1255} 1256 1257static int 1258sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1259{ 1260 int allowed, error; 1261 1262 allowed = hyperthreading_allowed; 1263 error = sysctl_handle_int(oidp, &allowed, 0, req); 1264 if (error || !req->newptr) 1265 return (error); 1266 1267#ifdef SCHED_ULE 1268 /* 1269 * SCHED_ULE doesn't allow enabling/disabling HT cores at 1270 * run-time. 1271 */ 1272 if (allowed != hyperthreading_allowed) 1273 return (ENOTSUP); 1274 return (error); 1275#endif 1276 1277 if (allowed) 1278 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1279 else 1280 hlt_cpus_mask |= hyperthreading_cpus_mask; 1281 1282 if (logical_cpus_mask != 0 && 1283 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1284 hlt_logical_cpus = 1; 1285 else 1286 hlt_logical_cpus = 0; 1287 1288 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1289 hlt_cpus_mask &= ~(1<<0); 1290 1291 hyperthreading_allowed = allowed; 1292 return (error); 1293} 1294 1295static void 1296cpu_hlt_setup(void *dummy __unused) 1297{ 1298 1299 if (logical_cpus_mask != 0) { 1300 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1301 &hlt_logical_cpus); 1302 sysctl_ctx_init(&logical_cpu_clist); 1303 SYSCTL_ADD_PROC(&logical_cpu_clist, 1304 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1305 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1306 sysctl_hlt_logical_cpus, "IU", ""); 1307 SYSCTL_ADD_UINT(&logical_cpu_clist, 1308 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1309 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1310 &logical_cpus_mask, 0, ""); 1311 1312 if (hlt_logical_cpus) 1313 hlt_cpus_mask |= logical_cpus_mask; 1314 1315 /* 1316 * If necessary for security purposes, force 1317 * hyperthreading off, regardless of the value 1318 * of hlt_logical_cpus. 1319 */ 1320 if (hyperthreading_cpus_mask) { 1321 SYSCTL_ADD_PROC(&logical_cpu_clist, 1322 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1323 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1324 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1325 if (! hyperthreading_allowed) 1326 hlt_cpus_mask |= hyperthreading_cpus_mask; 1327 } 1328 } 1329} 1330SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1331 1332int 1333mp_grab_cpu_hlt(void) 1334{ 1335 u_int mask = PCPU_GET(cpumask); 1336#ifdef MP_WATCHDOG 1337 u_int cpuid = PCPU_GET(cpuid); 1338#endif 1339 int retval; 1340 1341#ifdef MP_WATCHDOG 1342 ap_watchdog(cpuid); 1343#endif 1344 1345 retval = mask & hlt_cpus_mask; 1346 while (mask & hlt_cpus_mask) 1347 __asm __volatile("sti; hlt" : : : "memory"); 1348 return (retval); 1349} 1350