mp_machdep.c revision 189509
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 189509 2009-03-08 05:01:39Z sobomax $"); 29 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#ifdef GPROF 39#include <sys/gmon.h> 40#endif 41#include <sys/kernel.h> 42#include <sys/ktr.h> 43#include <sys/lock.h> 44#include <sys/malloc.h> 45#include <sys/memrange.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/sched.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52 53#include <vm/vm.h> 54#include <vm/vm_param.h> 55#include <vm/pmap.h> 56#include <vm/vm_kern.h> 57#include <vm/vm_extern.h> 58 59#include <machine/apicreg.h> 60#include <machine/cputypes.h> 61#include <machine/md_var.h> 62#include <machine/mp_watchdog.h> 63#include <machine/pcb.h> 64#include <machine/psl.h> 65#include <machine/smp.h> 66#include <machine/specialreg.h> 67#include <machine/tss.h> 68 69#define WARMBOOT_TARGET 0 70#define WARMBOOT_OFF (KERNBASE + 0x0467) 71#define WARMBOOT_SEG (KERNBASE + 0x0469) 72 73#define CMOS_REG (0x70) 74#define CMOS_DATA (0x71) 75#define BIOS_RESET (0x0f) 76#define BIOS_WARM (0x0a) 77 78/* lock region used by kernel profiling */ 79int mcount_lock; 80 81int mp_naps; /* # of Applications processors */ 82int boot_cpu_id = -1; /* designated BSP */ 83 84extern struct pcpu __pcpu[]; 85 86/* AP uses this during bootstrap. Do not staticize. */ 87char *bootSTK; 88static int bootAP; 89 90/* Free these after use */ 91void *bootstacks[MAXCPU]; 92 93/* Temporary holder for double fault stack */ 94char *doublefault_stack; 95char *nmi_stack; 96 97/* Hotwire a 0->4MB V==P mapping */ 98extern pt_entry_t *KPTphys; 99 100/* SMP page table page */ 101extern pt_entry_t *SMPpt; 102 103extern int _udatasel; 104 105struct pcb stoppcbs[MAXCPU]; 106 107/* Variables needed for SMP tlb shootdown. */ 108vm_offset_t smp_tlb_addr1; 109vm_offset_t smp_tlb_addr2; 110volatile int smp_tlb_wait; 111 112extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 113 114#ifdef STOP_NMI 115volatile cpumask_t ipi_nmi_pending; 116 117static void ipi_nmi_selected(u_int32_t cpus); 118#endif 119 120/* 121 * Local data and functions. 122 */ 123 124#ifdef STOP_NMI 125/* 126 * Provide an alternate method of stopping other CPUs. If another CPU has 127 * disabled interrupts the conventional STOP IPI will be blocked. This 128 * NMI-based stop should get through in that case. 129 */ 130static int stop_cpus_with_nmi = 1; 131SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 132 &stop_cpus_with_nmi, 0, ""); 133TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 134#else 135#define stop_cpus_with_nmi 0 136#endif 137 138static u_int logical_cpus; 139 140/* used to hold the AP's until we are ready to release them */ 141static struct mtx ap_boot_mtx; 142 143/* Set to 1 once we're ready to let the APs out of the pen. */ 144static volatile int aps_ready = 0; 145 146/* 147 * Store data from cpu_add() until later in the boot when we actually setup 148 * the APs. 149 */ 150struct cpu_info { 151 int cpu_present:1; 152 int cpu_bsp:1; 153 int cpu_disabled:1; 154 int cpu_hyperthread:1; 155} static cpu_info[MAX_APIC_ID + 1]; 156int cpu_apic_ids[MAXCPU]; 157int apic_cpuids[MAX_APIC_ID + 1]; 158 159/* Holds pending bitmap based IPIs per CPU */ 160static volatile u_int cpu_ipi_pending[MAXCPU]; 161 162static u_int boot_address; 163 164static void assign_cpu_ids(void); 165static void set_interrupt_apic_ids(void); 166static int start_all_aps(void); 167static int start_ap(int apic_id); 168static void release_aps(void *dummy); 169 170static int hlt_logical_cpus; 171static u_int hyperthreading_cpus; 172static cpumask_t hyperthreading_cpus_mask; 173static int hyperthreading_allowed = 1; 174static struct sysctl_ctx_list logical_cpu_clist; 175static u_int bootMP_size; 176 177static void 178mem_range_AP_init(void) 179{ 180 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 181 mem_range_softc.mr_op->initAP(&mem_range_softc); 182} 183 184struct cpu_group * 185cpu_topo(void) 186{ 187 if (cpu_cores == 0) 188 cpu_cores = 1; 189 if (cpu_logical == 0) 190 cpu_logical = 1; 191 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 192 printf("WARNING: Non-uniform processors.\n"); 193 printf("WARNING: Using suboptimal topology.\n"); 194 return (smp_topo_none()); 195 } 196 /* 197 * No multi-core or hyper-threaded. 198 */ 199 if (cpu_logical * cpu_cores == 1) 200 return (smp_topo_none()); 201 /* 202 * Only HTT no multi-core. 203 */ 204 if (cpu_logical > 1 && cpu_cores == 1) 205 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 206 /* 207 * Only multi-core no HTT. 208 */ 209 if (cpu_cores > 1 && cpu_logical == 1) 210 return (smp_topo_1level(CG_SHARE_NONE, cpu_cores, 0)); 211 /* 212 * Both HTT and multi-core. 213 */ 214 return (smp_topo_2level(CG_SHARE_NONE, cpu_cores, 215 CG_SHARE_L1, cpu_logical, CG_FLAG_HTT)); 216} 217 218/* 219 * Calculate usable address in base memory for AP trampoline code. 220 */ 221u_int 222mp_bootaddress(u_int basemem) 223{ 224 225 bootMP_size = mptramp_end - mptramp_start; 226 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 227 if (((basemem * 1024) - boot_address) < bootMP_size) 228 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 229 /* 3 levels of page table pages */ 230 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 231 232 return mptramp_pagetables; 233} 234 235void 236cpu_add(u_int apic_id, char boot_cpu) 237{ 238 239 if (apic_id > MAX_APIC_ID) { 240 panic("SMP: APIC ID %d too high", apic_id); 241 return; 242 } 243 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 244 apic_id)); 245 cpu_info[apic_id].cpu_present = 1; 246 if (boot_cpu) { 247 KASSERT(boot_cpu_id == -1, 248 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 249 boot_cpu_id)); 250 boot_cpu_id = apic_id; 251 cpu_info[apic_id].cpu_bsp = 1; 252 } 253 if (mp_ncpus < MAXCPU) { 254 mp_ncpus++; 255 mp_maxid = mp_ncpus -1; 256 } 257 if (bootverbose) 258 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 259 "AP"); 260} 261 262void 263cpu_mp_setmaxid(void) 264{ 265 266 /* 267 * mp_maxid should be already set by calls to cpu_add(). 268 * Just sanity check its value here. 269 */ 270 if (mp_ncpus == 0) 271 KASSERT(mp_maxid == 0, 272 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 273 else if (mp_ncpus == 1) 274 mp_maxid = 0; 275 else 276 KASSERT(mp_maxid >= mp_ncpus - 1, 277 ("%s: counters out of sync: max %d, count %d", __func__, 278 mp_maxid, mp_ncpus)); 279} 280 281int 282cpu_mp_probe(void) 283{ 284 285 /* 286 * Always record BSP in CPU map so that the mbuf init code works 287 * correctly. 288 */ 289 all_cpus = 1; 290 if (mp_ncpus == 0) { 291 /* 292 * No CPUs were found, so this must be a UP system. Setup 293 * the variables to represent a system with a single CPU 294 * with an id of 0. 295 */ 296 mp_ncpus = 1; 297 return (0); 298 } 299 300 /* At least one CPU was found. */ 301 if (mp_ncpus == 1) { 302 /* 303 * One CPU was found, so this must be a UP system with 304 * an I/O APIC. 305 */ 306 mp_maxid = 0; 307 return (0); 308 } 309 310 /* At least two CPUs were found. */ 311 return (1); 312} 313 314/* 315 * Initialize the IPI handlers and start up the AP's. 316 */ 317void 318cpu_mp_start(void) 319{ 320 int i; 321 u_int threads_per_cache, p[4]; 322 323 /* Initialize the logical ID to APIC ID table. */ 324 for (i = 0; i < MAXCPU; i++) { 325 cpu_apic_ids[i] = -1; 326 cpu_ipi_pending[i] = 0; 327 } 328 329 /* Install an inter-CPU IPI for TLB invalidation */ 330 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 331 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 332 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 333 334 /* Install an inter-CPU IPI for cache invalidation. */ 335 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0); 336 337 /* Install an inter-CPU IPI for all-CPU rendezvous */ 338 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 339 340 /* Install generic inter-CPU IPI handler */ 341 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 342 SDT_SYSIGT, SEL_KPL, 0); 343 344 /* Install an inter-CPU IPI for CPU stop/restart */ 345 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 346 347 /* Set boot_cpu_id if needed. */ 348 if (boot_cpu_id == -1) { 349 boot_cpu_id = PCPU_GET(apic_id); 350 cpu_info[boot_cpu_id].cpu_bsp = 1; 351 } else 352 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 353 ("BSP's APIC ID doesn't match boot_cpu_id")); 354 cpu_apic_ids[0] = boot_cpu_id; 355 apic_cpuids[boot_cpu_id] = 0; 356 357 /* Setup the initial logical CPUs info. */ 358 logical_cpus = logical_cpus_mask = 0; 359 if (cpu_feature & CPUID_HTT) 360 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 361 362 /* 363 * Work out if hyperthreading is *really* enabled. This 364 * is made really ugly by the fact that processors lie: Dual 365 * core processors claim to be hyperthreaded even when they're 366 * not, presumably because they want to be treated the same 367 * way as HTT with respect to per-cpu software licensing. 368 * At the time of writing (May 12, 2005) the only hyperthreaded 369 * cpus are from Intel, and Intel's dual-core processors can be 370 * identified via the "deterministic cache parameters" cpuid 371 * calls. 372 */ 373 /* 374 * First determine if this is an Intel processor which claims 375 * to have hyperthreading support. 376 */ 377 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) { 378 /* 379 * If the "deterministic cache parameters" cpuid calls 380 * are available, use them. 381 */ 382 if (cpu_high >= 4) { 383 /* Ask the processor about the L1 cache. */ 384 for (i = 0; i < 1; i++) { 385 cpuid_count(4, i, p); 386 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 387 if (hyperthreading_cpus < threads_per_cache) 388 hyperthreading_cpus = threads_per_cache; 389 if ((p[0] & 0x1f) == 0) 390 break; 391 } 392 } 393 394 /* 395 * If the deterministic cache parameters are not 396 * available, or if no caches were reported to exist, 397 * just accept what the HTT flag indicated. 398 */ 399 if (hyperthreading_cpus == 0) 400 hyperthreading_cpus = logical_cpus; 401 } 402 403 assign_cpu_ids(); 404 405 /* Start each Application Processor */ 406 start_all_aps(); 407 408 set_interrupt_apic_ids(); 409} 410 411 412/* 413 * Print various information about the SMP system hardware and setup. 414 */ 415void 416cpu_mp_announce(void) 417{ 418 int i, x; 419 const char *hyperthread; 420 421 /* List CPUs */ 422 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 423 for (i = 1, x = 0; x <= MAX_APIC_ID; x++) { 424 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 425 continue; 426 if (cpu_info[x].cpu_hyperthread) { 427 hyperthread = "/HT"; 428 } else { 429 hyperthread = ""; 430 } 431 if (cpu_info[x].cpu_disabled) 432 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", 433 hyperthread, x); 434 else { 435 KASSERT(i < mp_ncpus, 436 ("mp_ncpus and actual cpus are out of whack")); 437 printf(" cpu%d (AP%s): APIC ID: %2d\n", i++, 438 hyperthread, x); 439 } 440 } 441} 442 443/* 444 * AP CPU's call this to initialize themselves. 445 */ 446void 447init_secondary(void) 448{ 449 struct pcpu *pc; 450 struct nmi_pcpu *np; 451 u_int64_t msr, cr0; 452 int cpu, gsel_tss, x; 453 struct region_descriptor ap_gdt; 454 455 /* Set by the startup code for us to use */ 456 cpu = bootAP; 457 458 /* Init tss */ 459 common_tss[cpu] = common_tss[0]; 460 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 461 common_tss[cpu].tss_iobase = sizeof(struct amd64tss); 462 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 463 464 /* The NMI stack runs on IST2. */ 465 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1; 466 common_tss[cpu].tss_ist2 = (long) np; 467 468 /* Prepare private GDT */ 469 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 470 ssdtosyssd(&gdt_segs[GPROC0_SEL], 471 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]); 472 for (x = 0; x < NGDT; x++) { 473 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 474 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]); 475 } 476 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 477 ap_gdt.rd_base = (long) &gdt[NGDT * cpu]; 478 lgdt(&ap_gdt); /* does magic intra-segment return */ 479 480 /* Get per-cpu data */ 481 pc = &__pcpu[cpu]; 482 483 /* prime data page for it to use */ 484 pcpu_init(pc, cpu, sizeof(struct pcpu)); 485 pc->pc_apic_id = cpu_apic_ids[cpu]; 486 pc->pc_prvspace = pc; 487 pc->pc_curthread = 0; 488 pc->pc_tssp = &common_tss[cpu]; 489 pc->pc_rsp0 = 0; 490 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL]; 491 492 /* Save the per-cpu pointer for use by the NMI handler. */ 493 np->np_pcpu = (register_t) pc; 494 495 wrmsr(MSR_FSBASE, 0); /* User value */ 496 wrmsr(MSR_GSBASE, (u_int64_t)pc); 497 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 498 499 lidt(&r_idt); 500 501 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 502 ltr(gsel_tss); 503 504 /* 505 * Set to a known state: 506 * Set by mpboot.s: CR0_PG, CR0_PE 507 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 508 */ 509 cr0 = rcr0(); 510 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 511 load_cr0(cr0); 512 513 /* Set up the fast syscall stuff */ 514 msr = rdmsr(MSR_EFER) | EFER_SCE; 515 wrmsr(MSR_EFER, msr); 516 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 517 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 518 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 519 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 520 wrmsr(MSR_STAR, msr); 521 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 522 523 /* Disable local APIC just to be sure. */ 524 lapic_disable(); 525 526 /* signal our startup to the BSP. */ 527 mp_naps++; 528 529 /* Spin until the BSP releases the AP's. */ 530 while (!aps_ready) 531 ia32_pause(); 532 533 /* Initialize the PAT MSR. */ 534 pmap_init_pat(); 535 536 /* set up CPU registers and state */ 537 cpu_setregs(); 538 539 /* set up SSE/NX registers */ 540 initializecpu(); 541 542 /* set up FPU state on the AP */ 543 fpuinit(); 544 545 /* A quick check from sanity claus */ 546 if (PCPU_GET(apic_id) != lapic_id()) { 547 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 548 printf("SMP: actual apic_id = %d\n", lapic_id()); 549 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 550 panic("cpuid mismatch! boom!!"); 551 } 552 553 /* Initialize curthread. */ 554 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 555 PCPU_SET(curthread, PCPU_GET(idlethread)); 556 557 mtx_lock_spin(&ap_boot_mtx); 558 559 /* Init local apic for irq's */ 560 lapic_setup(1); 561 562 /* Set memory range attributes for this CPU to match the BSP */ 563 mem_range_AP_init(); 564 565 smp_cpus++; 566 567 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 568 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 569 570 /* Determine if we are a logical CPU. */ 571 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 572 logical_cpus_mask |= PCPU_GET(cpumask); 573 574 /* Determine if we are a hyperthread. */ 575 if (hyperthreading_cpus > 1 && 576 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 577 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 578 579 /* Build our map of 'other' CPUs. */ 580 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 581 582 if (bootverbose) 583 lapic_dump("AP"); 584 585 if (smp_cpus == mp_ncpus) { 586 /* enable IPI's, tlb shootdown, freezes etc */ 587 atomic_store_rel_int(&smp_started, 1); 588 smp_active = 1; /* historic */ 589 } 590 591 /* 592 * Enable global pages TLB extension 593 * This also implicitly flushes the TLB 594 */ 595 596 load_cr4(rcr4() | CR4_PGE); 597 load_ds(_udatasel); 598 load_es(_udatasel); 599 load_fs(_udatasel); 600 mtx_unlock_spin(&ap_boot_mtx); 601 602 /* wait until all the AP's are up */ 603 while (smp_started == 0) 604 ia32_pause(); 605 606 sched_throw(NULL); 607 608 panic("scheduler returned us to %s", __func__); 609 /* NOTREACHED */ 610} 611 612/******************************************************************* 613 * local functions and data 614 */ 615 616/* 617 * We tell the I/O APIC code about all the CPUs we want to receive 618 * interrupts. If we don't want certain CPUs to receive IRQs we 619 * can simply not tell the I/O APIC code about them in this function. 620 * We also do not tell it about the BSP since it tells itself about 621 * the BSP internally to work with UP kernels and on UP machines. 622 */ 623static void 624set_interrupt_apic_ids(void) 625{ 626 u_int i, apic_id; 627 628 for (i = 0; i < MAXCPU; i++) { 629 apic_id = cpu_apic_ids[i]; 630 if (apic_id == -1) 631 continue; 632 if (cpu_info[apic_id].cpu_bsp) 633 continue; 634 if (cpu_info[apic_id].cpu_disabled) 635 continue; 636 637 /* Don't let hyperthreads service interrupts. */ 638 if (hyperthreading_cpus > 1 && 639 apic_id % hyperthreading_cpus != 0) 640 continue; 641 642 intr_add_cpu(i); 643 } 644} 645 646/* 647 * Assign logical CPU IDs to local APICs. 648 */ 649static void 650assign_cpu_ids(void) 651{ 652 u_int i; 653 654 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 655 &hyperthreading_allowed); 656 657 /* Check for explicitly disabled CPUs. */ 658 for (i = 0; i <= MAX_APIC_ID; i++) { 659 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 660 continue; 661 662 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 663 cpu_info[i].cpu_hyperthread = 1; 664#if defined(SCHED_ULE) 665 /* 666 * Don't use HT CPU if it has been disabled by a 667 * tunable. 668 */ 669 if (hyperthreading_allowed == 0) { 670 cpu_info[i].cpu_disabled = 1; 671 continue; 672 } 673#endif 674 } 675 676 /* Don't use this CPU if it has been disabled by a tunable. */ 677 if (resource_disabled("lapic", i)) { 678 cpu_info[i].cpu_disabled = 1; 679 continue; 680 } 681 } 682 683 /* 684 * Assign CPU IDs to local APIC IDs and disable any CPUs 685 * beyond MAXCPU. CPU 0 has already been assigned to the BSP, 686 * so we only have to assign IDs for APs. 687 */ 688 mp_ncpus = 1; 689 for (i = 0; i <= MAX_APIC_ID; i++) { 690 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 691 cpu_info[i].cpu_disabled) 692 continue; 693 694 if (mp_ncpus < MAXCPU) { 695 cpu_apic_ids[mp_ncpus] = i; 696 apic_cpuids[i] = mp_ncpus; 697 mp_ncpus++; 698 } else 699 cpu_info[i].cpu_disabled = 1; 700 } 701 KASSERT(mp_maxid >= mp_ncpus - 1, 702 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 703 mp_ncpus)); 704} 705 706/* 707 * start each AP in our list 708 */ 709static int 710start_all_aps(void) 711{ 712 vm_offset_t va = boot_address + KERNBASE; 713 u_int64_t *pt4, *pt3, *pt2; 714 u_int32_t mpbioswarmvec; 715 int apic_id, cpu, i; 716 u_char mpbiosreason; 717 718 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 719 720 /* install the AP 1st level boot code */ 721 pmap_kenter(va, boot_address); 722 pmap_invalidate_page(kernel_pmap, va); 723 bcopy(mptramp_start, (void *)va, bootMP_size); 724 725 /* Locate the page tables, they'll be below the trampoline */ 726 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 727 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 728 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 729 730 /* Create the initial 1GB replicated page tables */ 731 for (i = 0; i < 512; i++) { 732 /* Each slot of the level 4 pages points to the same level 3 page */ 733 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 734 pt4[i] |= PG_V | PG_RW | PG_U; 735 736 /* Each slot of the level 3 pages points to the same level 2 page */ 737 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 738 pt3[i] |= PG_V | PG_RW | PG_U; 739 740 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 741 pt2[i] = i * (2 * 1024 * 1024); 742 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 743 } 744 745 /* save the current value of the warm-start vector */ 746 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 747 outb(CMOS_REG, BIOS_RESET); 748 mpbiosreason = inb(CMOS_DATA); 749 750 /* setup a vector to our boot code */ 751 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 752 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 753 outb(CMOS_REG, BIOS_RESET); 754 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 755 756 /* start each AP */ 757 for (cpu = 1; cpu < mp_ncpus; cpu++) { 758 apic_id = cpu_apic_ids[cpu]; 759 760 /* allocate and set up an idle stack data page */ 761 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 762 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 763 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 764 765 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 766 bootAP = cpu; 767 768 /* attempt to start the Application Processor */ 769 if (!start_ap(apic_id)) { 770 /* restore the warmstart vector */ 771 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 772 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 773 } 774 775 all_cpus |= (1 << cpu); /* record AP in CPU map */ 776 } 777 778 /* build our map of 'other' CPUs */ 779 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 780 781 /* restore the warmstart vector */ 782 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 783 784 outb(CMOS_REG, BIOS_RESET); 785 outb(CMOS_DATA, mpbiosreason); 786 787 /* number of APs actually started */ 788 return mp_naps; 789} 790 791 792/* 793 * This function starts the AP (application processor) identified 794 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 795 * to accomplish this. This is necessary because of the nuances 796 * of the different hardware we might encounter. It isn't pretty, 797 * but it seems to work. 798 */ 799static int 800start_ap(int apic_id) 801{ 802 int vector, ms; 803 int cpus; 804 805 /* calculate the vector */ 806 vector = (boot_address >> 12) & 0xff; 807 808 /* used as a watchpoint to signal AP startup */ 809 cpus = mp_naps; 810 811 /* 812 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 813 * and running the target CPU. OR this INIT IPI might be latched (P5 814 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 815 * ignored. 816 */ 817 818 /* do an INIT IPI: assert RESET */ 819 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 820 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 821 822 /* wait for pending status end */ 823 lapic_ipi_wait(-1); 824 825 /* do an INIT IPI: deassert RESET */ 826 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 827 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 828 829 /* wait for pending status end */ 830 DELAY(10000); /* wait ~10mS */ 831 lapic_ipi_wait(-1); 832 833 /* 834 * next we do a STARTUP IPI: the previous INIT IPI might still be 835 * latched, (P5 bug) this 1st STARTUP would then terminate 836 * immediately, and the previously started INIT IPI would continue. OR 837 * the previous INIT IPI has already run. and this STARTUP IPI will 838 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 839 * will run. 840 */ 841 842 /* do a STARTUP IPI */ 843 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 844 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 845 vector, apic_id); 846 lapic_ipi_wait(-1); 847 DELAY(200); /* wait ~200uS */ 848 849 /* 850 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 851 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 852 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 853 * recognized after hardware RESET or INIT IPI. 854 */ 855 856 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 857 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 858 vector, apic_id); 859 lapic_ipi_wait(-1); 860 DELAY(200); /* wait ~200uS */ 861 862 /* Wait up to 5 seconds for it to start. */ 863 for (ms = 0; ms < 5000; ms++) { 864 if (mp_naps > cpus) 865 return 1; /* return SUCCESS */ 866 DELAY(1000); 867 } 868 return 0; /* return FAILURE */ 869} 870 871/* 872 * Flush the TLB on all other CPU's 873 */ 874static void 875smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 876{ 877 u_int ncpu; 878 879 ncpu = mp_ncpus - 1; /* does not shootdown self */ 880 if (ncpu < 1) 881 return; /* no other cpus */ 882 if (!(read_rflags() & PSL_I)) 883 panic("%s: interrupts disabled", __func__); 884 mtx_lock_spin(&smp_ipi_mtx); 885 smp_tlb_addr1 = addr1; 886 smp_tlb_addr2 = addr2; 887 atomic_store_rel_int(&smp_tlb_wait, 0); 888 ipi_all_but_self(vector); 889 while (smp_tlb_wait < ncpu) 890 ia32_pause(); 891 mtx_unlock_spin(&smp_ipi_mtx); 892} 893 894static void 895smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 896{ 897 int ncpu, othercpus; 898 899 othercpus = mp_ncpus - 1; 900 if (mask == (u_int)-1) { 901 ncpu = othercpus; 902 if (ncpu < 1) 903 return; 904 } else { 905 mask &= ~PCPU_GET(cpumask); 906 if (mask == 0) 907 return; 908 ncpu = bitcount32(mask); 909 if (ncpu > othercpus) { 910 /* XXX this should be a panic offence */ 911 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 912 ncpu, othercpus); 913 ncpu = othercpus; 914 } 915 /* XXX should be a panic, implied by mask == 0 above */ 916 if (ncpu < 1) 917 return; 918 } 919 if (!(read_rflags() & PSL_I)) 920 panic("%s: interrupts disabled", __func__); 921 mtx_lock_spin(&smp_ipi_mtx); 922 smp_tlb_addr1 = addr1; 923 smp_tlb_addr2 = addr2; 924 atomic_store_rel_int(&smp_tlb_wait, 0); 925 if (mask == (u_int)-1) 926 ipi_all_but_self(vector); 927 else 928 ipi_selected(mask, vector); 929 while (smp_tlb_wait < ncpu) 930 ia32_pause(); 931 mtx_unlock_spin(&smp_ipi_mtx); 932} 933 934void 935smp_cache_flush(void) 936{ 937 938 if (smp_started) 939 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 940} 941 942void 943smp_invltlb(void) 944{ 945 946 if (smp_started) { 947 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 948 } 949} 950 951void 952smp_invlpg(vm_offset_t addr) 953{ 954 955 if (smp_started) 956 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 957} 958 959void 960smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 961{ 962 963 if (smp_started) { 964 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 965 } 966} 967 968void 969smp_masked_invltlb(u_int mask) 970{ 971 972 if (smp_started) { 973 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 974 } 975} 976 977void 978smp_masked_invlpg(u_int mask, vm_offset_t addr) 979{ 980 981 if (smp_started) { 982 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 983 } 984} 985 986void 987smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 988{ 989 990 if (smp_started) { 991 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 992 } 993} 994 995void 996ipi_bitmap_handler(struct trapframe frame) 997{ 998 int cpu = PCPU_GET(cpuid); 999 u_int ipi_bitmap; 1000 1001 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1002 1003 if (ipi_bitmap & (1 << IPI_PREEMPT)) 1004 sched_preempt(curthread); 1005 1006 /* Nothing to do for AST */ 1007} 1008 1009/* 1010 * send an IPI to a set of cpus. 1011 */ 1012void 1013ipi_selected(u_int32_t cpus, u_int ipi) 1014{ 1015 int cpu; 1016 u_int bitmap = 0; 1017 u_int old_pending; 1018 u_int new_pending; 1019 1020 if (IPI_IS_BITMAPED(ipi)) { 1021 bitmap = 1 << ipi; 1022 ipi = IPI_BITMAP_VECTOR; 1023 } 1024 1025#ifdef STOP_NMI 1026 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 1027 ipi_nmi_selected(cpus); 1028 return; 1029 } 1030#endif 1031 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1032 while ((cpu = ffs(cpus)) != 0) { 1033 cpu--; 1034 cpus &= ~(1 << cpu); 1035 1036 KASSERT(cpu_apic_ids[cpu] != -1, 1037 ("IPI to non-existent CPU %d", cpu)); 1038 1039 if (bitmap) { 1040 do { 1041 old_pending = cpu_ipi_pending[cpu]; 1042 new_pending = old_pending | bitmap; 1043 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1044 1045 if (old_pending) 1046 continue; 1047 } 1048 1049 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1050 } 1051 1052} 1053 1054/* 1055 * send an IPI to all CPUs EXCEPT myself 1056 */ 1057void 1058ipi_all_but_self(u_int ipi) 1059{ 1060 1061 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1062 ipi_selected(PCPU_GET(other_cpus), ipi); 1063 return; 1064 } 1065 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1066 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1067} 1068 1069#ifdef STOP_NMI 1070/* 1071 * send NMI IPI to selected CPUs 1072 */ 1073 1074#define BEFORE_SPIN 1000000 1075 1076void 1077ipi_nmi_selected(u_int32_t cpus) 1078{ 1079 int cpu; 1080 register_t icrlo; 1081 1082 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1083 | APIC_TRIGMOD_EDGE; 1084 1085 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1086 1087 atomic_set_int(&ipi_nmi_pending, cpus); 1088 1089 while ((cpu = ffs(cpus)) != 0) { 1090 cpu--; 1091 cpus &= ~(1 << cpu); 1092 1093 KASSERT(cpu_apic_ids[cpu] != -1, 1094 ("IPI NMI to non-existent CPU %d", cpu)); 1095 1096 /* Wait for an earlier IPI to finish. */ 1097 if (!lapic_ipi_wait(BEFORE_SPIN)) 1098 panic("ipi_nmi_selected: previous IPI has not cleared"); 1099 1100 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1101 } 1102} 1103 1104int 1105ipi_nmi_handler(void) 1106{ 1107 int cpumask = PCPU_GET(cpumask); 1108 1109 if (!(ipi_nmi_pending & cpumask)) 1110 return 1; 1111 1112 atomic_clear_int(&ipi_nmi_pending, cpumask); 1113 cpustop_handler(); 1114 return 0; 1115} 1116 1117#endif /* STOP_NMI */ 1118 1119/* 1120 * Handle an IPI_STOP by saving our current context and spinning until we 1121 * are resumed. 1122 */ 1123void 1124cpustop_handler(void) 1125{ 1126 int cpu = PCPU_GET(cpuid); 1127 int cpumask = PCPU_GET(cpumask); 1128 1129 savectx(&stoppcbs[cpu]); 1130 1131 /* Indicate that we are stopped */ 1132 atomic_set_int(&stopped_cpus, cpumask); 1133 1134 /* Wait for restart */ 1135 while (!(started_cpus & cpumask)) 1136 ia32_pause(); 1137 1138 atomic_clear_int(&started_cpus, cpumask); 1139 atomic_clear_int(&stopped_cpus, cpumask); 1140 1141 if (cpu == 0 && cpustop_restartfunc != NULL) { 1142 cpustop_restartfunc(); 1143 cpustop_restartfunc = NULL; 1144 } 1145} 1146 1147/* 1148 * This is called once the rest of the system is up and running and we're 1149 * ready to let the AP's out of the pen. 1150 */ 1151static void 1152release_aps(void *dummy __unused) 1153{ 1154 1155 if (mp_ncpus == 1) 1156 return; 1157 atomic_store_rel_int(&aps_ready, 1); 1158 while (smp_started == 0) 1159 ia32_pause(); 1160} 1161SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1162 1163static int 1164sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1165{ 1166 u_int mask; 1167 int error; 1168 1169 mask = hlt_cpus_mask; 1170 error = sysctl_handle_int(oidp, &mask, 0, req); 1171 if (error || !req->newptr) 1172 return (error); 1173 1174 if (logical_cpus_mask != 0 && 1175 (mask & logical_cpus_mask) == logical_cpus_mask) 1176 hlt_logical_cpus = 1; 1177 else 1178 hlt_logical_cpus = 0; 1179 1180 if (! hyperthreading_allowed) 1181 mask |= hyperthreading_cpus_mask; 1182 1183 if ((mask & all_cpus) == all_cpus) 1184 mask &= ~(1<<0); 1185 hlt_cpus_mask = mask; 1186 return (error); 1187} 1188SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1189 0, 0, sysctl_hlt_cpus, "IU", 1190 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1191 1192static int 1193sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1194{ 1195 int disable, error; 1196 1197 disable = hlt_logical_cpus; 1198 error = sysctl_handle_int(oidp, &disable, 0, req); 1199 if (error || !req->newptr) 1200 return (error); 1201 1202 if (disable) 1203 hlt_cpus_mask |= logical_cpus_mask; 1204 else 1205 hlt_cpus_mask &= ~logical_cpus_mask; 1206 1207 if (! hyperthreading_allowed) 1208 hlt_cpus_mask |= hyperthreading_cpus_mask; 1209 1210 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1211 hlt_cpus_mask &= ~(1<<0); 1212 1213 hlt_logical_cpus = disable; 1214 return (error); 1215} 1216 1217static int 1218sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1219{ 1220 int allowed, error; 1221 1222 allowed = hyperthreading_allowed; 1223 error = sysctl_handle_int(oidp, &allowed, 0, req); 1224 if (error || !req->newptr) 1225 return (error); 1226 1227#ifdef SCHED_ULE 1228 /* 1229 * SCHED_ULE doesn't allow enabling/disabling HT cores at 1230 * run-time. 1231 */ 1232 if (allowed != hyperthreading_allowed) 1233 return (ENOTSUP); 1234 return (error); 1235#endif 1236 1237 if (allowed) 1238 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1239 else 1240 hlt_cpus_mask |= hyperthreading_cpus_mask; 1241 1242 if (logical_cpus_mask != 0 && 1243 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1244 hlt_logical_cpus = 1; 1245 else 1246 hlt_logical_cpus = 0; 1247 1248 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1249 hlt_cpus_mask &= ~(1<<0); 1250 1251 hyperthreading_allowed = allowed; 1252 return (error); 1253} 1254 1255static void 1256cpu_hlt_setup(void *dummy __unused) 1257{ 1258 1259 if (logical_cpus_mask != 0) { 1260 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1261 &hlt_logical_cpus); 1262 sysctl_ctx_init(&logical_cpu_clist); 1263 SYSCTL_ADD_PROC(&logical_cpu_clist, 1264 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1265 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1266 sysctl_hlt_logical_cpus, "IU", ""); 1267 SYSCTL_ADD_UINT(&logical_cpu_clist, 1268 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1269 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1270 &logical_cpus_mask, 0, ""); 1271 1272 if (hlt_logical_cpus) 1273 hlt_cpus_mask |= logical_cpus_mask; 1274 1275 /* 1276 * If necessary for security purposes, force 1277 * hyperthreading off, regardless of the value 1278 * of hlt_logical_cpus. 1279 */ 1280 if (hyperthreading_cpus_mask) { 1281 SYSCTL_ADD_PROC(&logical_cpu_clist, 1282 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1283 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1284 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1285 if (! hyperthreading_allowed) 1286 hlt_cpus_mask |= hyperthreading_cpus_mask; 1287 } 1288 } 1289} 1290SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1291 1292int 1293mp_grab_cpu_hlt(void) 1294{ 1295 u_int mask = PCPU_GET(cpumask); 1296#ifdef MP_WATCHDOG 1297 u_int cpuid = PCPU_GET(cpuid); 1298#endif 1299 int retval; 1300 1301#ifdef MP_WATCHDOG 1302 ap_watchdog(cpuid); 1303#endif 1304 1305 retval = mask & hlt_cpus_mask; 1306 while (mask & hlt_cpus_mask) 1307 __asm __volatile("sti; hlt" : : : "memory"); 1308 return (retval); 1309} 1310