mp_machdep.c revision 158238
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 158238 2006-05-01 22:07:00Z jhb $"); 29 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#ifdef GPROF 39#include <sys/gmon.h> 40#endif 41#include <sys/kernel.h> 42#include <sys/ktr.h> 43#include <sys/lock.h> 44#include <sys/malloc.h> 45#include <sys/memrange.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/smp.h> 50#include <sys/sysctl.h> 51 52#include <vm/vm.h> 53#include <vm/vm_param.h> 54#include <vm/pmap.h> 55#include <vm/vm_kern.h> 56#include <vm/vm_extern.h> 57 58#include <machine/apicreg.h> 59#include <machine/clock.h> 60#include <machine/md_var.h> 61#include <machine/mp_watchdog.h> 62#include <machine/pcb.h> 63#include <machine/psl.h> 64#include <machine/smp.h> 65#include <machine/specialreg.h> 66#include <machine/tss.h> 67 68#define WARMBOOT_TARGET 0 69#define WARMBOOT_OFF (KERNBASE + 0x0467) 70#define WARMBOOT_SEG (KERNBASE + 0x0469) 71 72#define CMOS_REG (0x70) 73#define CMOS_DATA (0x71) 74#define BIOS_RESET (0x0f) 75#define BIOS_WARM (0x0a) 76 77/* lock region used by kernel profiling */ 78int mcount_lock; 79 80int mp_naps; /* # of Applications processors */ 81int boot_cpu_id = -1; /* designated BSP */ 82extern int nkpt; 83 84/* 85 * CPU topology map datastructures for HTT. 86 */ 87static struct cpu_group mp_groups[MAXCPU]; 88static struct cpu_top mp_top; 89 90/* AP uses this during bootstrap. Do not staticize. */ 91char *bootSTK; 92static int bootAP; 93 94/* Free these after use */ 95void *bootstacks[MAXCPU]; 96 97/* Temporary holder for double fault stack */ 98char *doublefault_stack; 99 100/* Hotwire a 0->4MB V==P mapping */ 101extern pt_entry_t *KPTphys; 102 103/* SMP page table page */ 104extern pt_entry_t *SMPpt; 105 106struct pcb stoppcbs[MAXCPU]; 107 108/* Variables needed for SMP tlb shootdown. */ 109vm_offset_t smp_tlb_addr1; 110vm_offset_t smp_tlb_addr2; 111volatile int smp_tlb_wait; 112 113extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 114 115#ifdef STOP_NMI 116volatile cpumask_t ipi_nmi_pending; 117 118static void ipi_nmi_selected(u_int32_t cpus); 119#endif 120 121/* 122 * Local data and functions. 123 */ 124 125#ifdef STOP_NMI 126/* 127 * Provide an alternate method of stopping other CPUs. If another CPU has 128 * disabled interrupts the conventional STOP IPI will be blocked. This 129 * NMI-based stop should get through in that case. 130 */ 131static int stop_cpus_with_nmi = 1; 132SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 133 &stop_cpus_with_nmi, 0, ""); 134TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 135#else 136#define stop_cpus_with_nmi 0 137#endif 138 139static u_int logical_cpus; 140 141/* used to hold the AP's until we are ready to release them */ 142static struct mtx ap_boot_mtx; 143 144/* Set to 1 once we're ready to let the APs out of the pen. */ 145static volatile int aps_ready = 0; 146 147/* 148 * Store data from cpu_add() until later in the boot when we actually setup 149 * the APs. 150 */ 151struct cpu_info { 152 int cpu_present:1; 153 int cpu_bsp:1; 154 int cpu_disabled:1; 155} static cpu_info[MAXCPU]; 156static int cpu_apic_ids[MAXCPU]; 157 158/* Holds pending bitmap based IPIs per CPU */ 159static volatile u_int cpu_ipi_pending[MAXCPU]; 160 161static u_int boot_address; 162 163static void set_interrupt_apic_ids(void); 164static int start_all_aps(void); 165static int start_ap(int apic_id); 166static void release_aps(void *dummy); 167 168static int hlt_logical_cpus; 169static u_int hyperthreading_cpus; 170static cpumask_t hyperthreading_cpus_mask; 171static int hyperthreading_allowed = 1; 172static struct sysctl_ctx_list logical_cpu_clist; 173static u_int bootMP_size; 174 175static void 176mem_range_AP_init(void) 177{ 178 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 179 mem_range_softc.mr_op->initAP(&mem_range_softc); 180} 181 182void 183mp_topology(void) 184{ 185 struct cpu_group *group; 186 u_int regs[4]; 187 int logical_cpus; 188 int apic_id; 189 int groups; 190 int cpu; 191 192 /* Build the smp_topology map. */ 193 /* Nothing to do if there is no HTT support. */ 194 if ((cpu_feature & CPUID_HTT) == 0) 195 return; 196 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 197 if (logical_cpus <= 1) 198 return; 199 /* Nothing to do if reported cores are physical cores. */ 200 if (strcmp(cpu_vendor, "GenuineIntel") == 0 && cpu_high >= 4) { 201 cpuid_count(4, 0, regs); 202 if ((regs[0] & 0x1f) != 0 && 203 logical_cpus <= ((regs[0] >> 26) & 0x3f) + 1) 204 return; 205 } 206 group = &mp_groups[0]; 207 groups = 1; 208 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 209 if (!cpu_info[apic_id].cpu_present) 210 continue; 211 /* 212 * If the current group has members and we're not a logical 213 * cpu, create a new group. 214 */ 215 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 216 group++; 217 groups++; 218 } 219 group->cg_count++; 220 group->cg_mask |= 1 << cpu; 221 cpu++; 222 } 223 224 mp_top.ct_count = groups; 225 mp_top.ct_group = mp_groups; 226 smp_topology = &mp_top; 227} 228 229/* 230 * Calculate usable address in base memory for AP trampoline code. 231 */ 232u_int 233mp_bootaddress(u_int basemem) 234{ 235 236 bootMP_size = mptramp_end - mptramp_start; 237 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 238 if (((basemem * 1024) - boot_address) < bootMP_size) 239 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 240 /* 3 levels of page table pages */ 241 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 242 243 return mptramp_pagetables; 244} 245 246void 247cpu_add(u_int apic_id, char boot_cpu) 248{ 249 250 if (apic_id >= MAXCPU) { 251 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 252 apic_id, MAXCPU - 1); 253 return; 254 } 255 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 256 apic_id)); 257 cpu_info[apic_id].cpu_present = 1; 258 if (boot_cpu) { 259 KASSERT(boot_cpu_id == -1, 260 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 261 boot_cpu_id)); 262 boot_cpu_id = apic_id; 263 cpu_info[apic_id].cpu_bsp = 1; 264 } 265 mp_ncpus++; 266 if (apic_id > mp_maxid) 267 mp_maxid = apic_id; 268 if (bootverbose) 269 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 270 "AP"); 271 272} 273 274void 275cpu_mp_setmaxid(void) 276{ 277 278 /* 279 * mp_maxid should be already set by calls to cpu_add(). 280 * Just sanity check its value here. 281 */ 282 if (mp_ncpus == 0) 283 KASSERT(mp_maxid == 0, 284 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 285 else if (mp_ncpus == 1) 286 mp_maxid = 0; 287 else 288 KASSERT(mp_maxid >= mp_ncpus - 1, 289 ("%s: counters out of sync: max %d, count %d", __func__, 290 mp_maxid, mp_ncpus)); 291 292} 293 294int 295cpu_mp_probe(void) 296{ 297 298 /* 299 * Always record BSP in CPU map so that the mbuf init code works 300 * correctly. 301 */ 302 all_cpus = 1; 303 if (mp_ncpus == 0) { 304 /* 305 * No CPUs were found, so this must be a UP system. Setup 306 * the variables to represent a system with a single CPU 307 * with an id of 0. 308 */ 309 mp_ncpus = 1; 310 return (0); 311 } 312 313 /* At least one CPU was found. */ 314 if (mp_ncpus == 1) { 315 /* 316 * One CPU was found, so this must be a UP system with 317 * an I/O APIC. 318 */ 319 mp_maxid = 0; 320 return (0); 321 } 322 323 /* At least two CPUs were found. */ 324 return (1); 325} 326 327/* 328 * Initialize the IPI handlers and start up the AP's. 329 */ 330void 331cpu_mp_start(void) 332{ 333 int i; 334 u_int threads_per_cache, p[4]; 335 336 /* Initialize the logical ID to APIC ID table. */ 337 for (i = 0; i < MAXCPU; i++) { 338 cpu_apic_ids[i] = -1; 339 cpu_ipi_pending[i] = 0; 340 } 341 342 /* Install an inter-CPU IPI for TLB invalidation */ 343 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 344 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 345 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 346 347 /* Install an inter-CPU IPI for all-CPU rendezvous */ 348 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 349 350 /* Install generic inter-CPU IPI handler */ 351 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 352 SDT_SYSIGT, SEL_KPL, 0); 353 354 /* Install an inter-CPU IPI for CPU stop/restart */ 355 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 356 357 /* Set boot_cpu_id if needed. */ 358 if (boot_cpu_id == -1) { 359 boot_cpu_id = PCPU_GET(apic_id); 360 cpu_info[boot_cpu_id].cpu_bsp = 1; 361 } else 362 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 363 ("BSP's APIC ID doesn't match boot_cpu_id")); 364 cpu_apic_ids[0] = boot_cpu_id; 365 366 /* Start each Application Processor */ 367 start_all_aps(); 368 369 /* Setup the initial logical CPUs info. */ 370 logical_cpus = logical_cpus_mask = 0; 371 if (cpu_feature & CPUID_HTT) 372 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 373 374 /* 375 * Work out if hyperthreading is *really* enabled. This 376 * is made really ugly by the fact that processors lie: Dual 377 * core processors claim to be hyperthreaded even when they're 378 * not, presumably because they want to be treated the same 379 * way as HTT with respect to per-cpu software licensing. 380 * At the time of writing (May 12, 2005) the only hyperthreaded 381 * cpus are from Intel, and Intel's dual-core processors can be 382 * identified via the "deterministic cache parameters" cpuid 383 * calls. 384 */ 385 /* 386 * First determine if this is an Intel processor which claims 387 * to have hyperthreading support. 388 */ 389 if ((cpu_feature & CPUID_HTT) && 390 (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 391 /* 392 * If the "deterministic cache parameters" cpuid calls 393 * are available, use them. 394 */ 395 if (cpu_high >= 4) { 396 /* Ask the processor about the L1 cache. */ 397 for (i = 0; i < 1; i++) { 398 cpuid_count(4, i, p); 399 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 400 if (hyperthreading_cpus < threads_per_cache) 401 hyperthreading_cpus = threads_per_cache; 402 if ((p[0] & 0x1f) == 0) 403 break; 404 } 405 } 406 407 /* 408 * If the deterministic cache parameters are not 409 * available, or if no caches were reported to exist, 410 * just accept what the HTT flag indicated. 411 */ 412 if (hyperthreading_cpus == 0) 413 hyperthreading_cpus = logical_cpus; 414 } 415 416 set_interrupt_apic_ids(); 417} 418 419 420/* 421 * Print various information about the SMP system hardware and setup. 422 */ 423void 424cpu_mp_announce(void) 425{ 426 int i, x; 427 428 /* List CPUs */ 429 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 430 for (i = 1, x = 0; x < MAXCPU; x++) { 431 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 432 continue; 433 if (cpu_info[x].cpu_disabled) 434 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 435 else { 436 KASSERT(i < mp_ncpus, 437 ("mp_ncpus and actual cpus are out of whack")); 438 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 439 } 440 } 441} 442 443/* 444 * AP CPU's call this to initialize themselves. 445 */ 446void 447init_secondary(void) 448{ 449 struct pcpu *pc; 450 u_int64_t msr, cr0; 451 int cpu, gsel_tss; 452 453 /* Set by the startup code for us to use */ 454 cpu = bootAP; 455 456 /* Init tss */ 457 common_tss[cpu] = common_tss[0]; 458 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 459 common_tss[cpu].tss_iobase = sizeof(struct amd64tss); 460 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 461 462 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 463 ssdtosyssd(&gdt_segs[GPROC0_SEL], 464 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 465 466 lgdt(&r_gdt); /* does magic intra-segment return */ 467 468 /* Get per-cpu data */ 469 pc = &__pcpu[cpu]; 470 471 /* prime data page for it to use */ 472 pcpu_init(pc, cpu, sizeof(struct pcpu)); 473 pc->pc_apic_id = cpu_apic_ids[cpu]; 474 pc->pc_prvspace = pc; 475 pc->pc_curthread = 0; 476 pc->pc_tssp = &common_tss[cpu]; 477 pc->pc_rsp0 = 0; 478 479 wrmsr(MSR_FSBASE, 0); /* User value */ 480 wrmsr(MSR_GSBASE, (u_int64_t)pc); 481 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 482 483 lidt(&r_idt); 484 485 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 486 ltr(gsel_tss); 487 488 /* 489 * Set to a known state: 490 * Set by mpboot.s: CR0_PG, CR0_PE 491 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 492 */ 493 cr0 = rcr0(); 494 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 495 load_cr0(cr0); 496 497 /* Set up the fast syscall stuff */ 498 msr = rdmsr(MSR_EFER) | EFER_SCE; 499 wrmsr(MSR_EFER, msr); 500 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 501 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 502 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 503 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 504 wrmsr(MSR_STAR, msr); 505 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 506 507 /* Disable local APIC just to be sure. */ 508 lapic_disable(); 509 510 /* signal our startup to the BSP. */ 511 mp_naps++; 512 513 /* Spin until the BSP releases the AP's. */ 514 while (!aps_ready) 515 ia32_pause(); 516 517 /* Initialize the PAT MSR. */ 518 pmap_init_pat(); 519 520 /* set up CPU registers and state */ 521 cpu_setregs(); 522 523 /* set up SSE/NX registers */ 524 initializecpu(); 525 526 /* set up FPU state on the AP */ 527 fpuinit(); 528 529 /* A quick check from sanity claus */ 530 if (PCPU_GET(apic_id) != lapic_id()) { 531 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 532 printf("SMP: actual apic_id = %d\n", lapic_id()); 533 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 534 panic("cpuid mismatch! boom!!"); 535 } 536 537 /* Initialize curthread. */ 538 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 539 PCPU_SET(curthread, PCPU_GET(idlethread)); 540 541 mtx_lock_spin(&ap_boot_mtx); 542 543 /* Init local apic for irq's */ 544 lapic_setup(); 545 546 /* Set memory range attributes for this CPU to match the BSP */ 547 mem_range_AP_init(); 548 549 smp_cpus++; 550 551 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 552 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 553 554 /* Determine if we are a logical CPU. */ 555 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 556 logical_cpus_mask |= PCPU_GET(cpumask); 557 558 /* Determine if we are a hyperthread. */ 559 if (hyperthreading_cpus > 1 && 560 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 561 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 562 563 /* Build our map of 'other' CPUs. */ 564 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 565 566 if (bootverbose) 567 lapic_dump("AP"); 568 569 if (smp_cpus == mp_ncpus) { 570 /* enable IPI's, tlb shootdown, freezes etc */ 571 atomic_store_rel_int(&smp_started, 1); 572 smp_active = 1; /* historic */ 573 } 574 575 /* 576 * Enable global pages TLB extension 577 * This also implicitly flushes the TLB 578 */ 579 580 load_cr4(rcr4() | CR4_PGE); 581 582 mtx_unlock_spin(&ap_boot_mtx); 583 584 /* wait until all the AP's are up */ 585 while (smp_started == 0) 586 ia32_pause(); 587 588 /* ok, now grab sched_lock and enter the scheduler */ 589 mtx_lock_spin(&sched_lock); 590 591 /* 592 * Correct spinlock nesting. The idle thread context that we are 593 * borrowing was created so that it would start out with a single 594 * spin lock (sched_lock) held in fork_trampoline(). Since we've 595 * explicitly acquired locks in this function, the nesting count 596 * is now 2 rather than 1. Since we are nested, calling 597 * spinlock_exit() will simply adjust the counts without allowing 598 * spin lock using code to interrupt us. 599 */ 600 spinlock_exit(); 601 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count")); 602 603 PCPU_SET(switchtime, cpu_ticks()); 604 PCPU_SET(switchticks, ticks); 605 606 cpu_throw(NULL, choosethread()); /* doesn't return */ 607 608 panic("scheduler returned us to %s", __func__); 609 /* NOTREACHED */ 610} 611 612/******************************************************************* 613 * local functions and data 614 */ 615 616/* 617 * We tell the I/O APIC code about all the CPUs we want to receive 618 * interrupts. If we don't want certain CPUs to receive IRQs we 619 * can simply not tell the I/O APIC code about them in this function. 620 * We also do not tell it about the BSP since it tells itself about 621 * the BSP internally to work with UP kernels and on UP machines. 622 */ 623static void 624set_interrupt_apic_ids(void) 625{ 626 u_int apic_id; 627 628 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 629 if (!cpu_info[apic_id].cpu_present) 630 continue; 631 if (cpu_info[apic_id].cpu_bsp) 632 continue; 633 634 /* Don't let hyperthreads service interrupts. */ 635 if (hyperthreading_cpus > 1 && 636 apic_id % hyperthreading_cpus != 0) 637 continue; 638 639 intr_add_cpu(apic_id); 640 } 641} 642 643/* 644 * start each AP in our list 645 */ 646static int 647start_all_aps(void) 648{ 649 vm_offset_t va = boot_address + KERNBASE; 650 u_int64_t *pt4, *pt3, *pt2; 651 u_int32_t mpbioswarmvec; 652 int apic_id, cpu, i; 653 u_char mpbiosreason; 654 655 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 656 657 /* install the AP 1st level boot code */ 658 pmap_kenter(va, boot_address); 659 pmap_invalidate_page(kernel_pmap, va); 660 bcopy(mptramp_start, (void *)va, bootMP_size); 661 662 /* Locate the page tables, they'll be below the trampoline */ 663 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 664 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 665 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 666 667 /* Create the initial 1GB replicated page tables */ 668 for (i = 0; i < 512; i++) { 669 /* Each slot of the level 4 pages points to the same level 3 page */ 670 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 671 pt4[i] |= PG_V | PG_RW | PG_U; 672 673 /* Each slot of the level 3 pages points to the same level 2 page */ 674 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 675 pt3[i] |= PG_V | PG_RW | PG_U; 676 677 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 678 pt2[i] = i * (2 * 1024 * 1024); 679 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 680 } 681 682 /* save the current value of the warm-start vector */ 683 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 684 outb(CMOS_REG, BIOS_RESET); 685 mpbiosreason = inb(CMOS_DATA); 686 687 /* setup a vector to our boot code */ 688 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 689 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 690 outb(CMOS_REG, BIOS_RESET); 691 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 692 693 /* start each AP */ 694 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 695 696 /* Ignore non-existent CPUs and the BSP. */ 697 if (!cpu_info[apic_id].cpu_present || 698 cpu_info[apic_id].cpu_bsp) 699 continue; 700 701 /* Don't use this CPU if it has been disabled by a tunable. */ 702 if (resource_disabled("lapic", apic_id)) { 703 cpu_info[apic_id].cpu_disabled = 1; 704 mp_ncpus--; 705 continue; 706 } 707 708 cpu++; 709 710 /* save APIC ID for this logical ID */ 711 cpu_apic_ids[cpu] = apic_id; 712 713 /* allocate and set up an idle stack data page */ 714 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 715 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 716 717 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 718 bootAP = cpu; 719 720 /* attempt to start the Application Processor */ 721 if (!start_ap(apic_id)) { 722 /* restore the warmstart vector */ 723 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 724 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 725 } 726 727 all_cpus |= (1 << cpu); /* record AP in CPU map */ 728 } 729 730 /* build our map of 'other' CPUs */ 731 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 732 733 /* restore the warmstart vector */ 734 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 735 736 outb(CMOS_REG, BIOS_RESET); 737 outb(CMOS_DATA, mpbiosreason); 738 739 /* number of APs actually started */ 740 return mp_naps; 741} 742 743 744/* 745 * This function starts the AP (application processor) identified 746 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 747 * to accomplish this. This is necessary because of the nuances 748 * of the different hardware we might encounter. It isn't pretty, 749 * but it seems to work. 750 */ 751static int 752start_ap(int apic_id) 753{ 754 int vector, ms; 755 int cpus; 756 757 /* calculate the vector */ 758 vector = (boot_address >> 12) & 0xff; 759 760 /* used as a watchpoint to signal AP startup */ 761 cpus = mp_naps; 762 763 /* 764 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 765 * and running the target CPU. OR this INIT IPI might be latched (P5 766 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 767 * ignored. 768 */ 769 770 /* do an INIT IPI: assert RESET */ 771 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 772 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 773 774 /* wait for pending status end */ 775 lapic_ipi_wait(-1); 776 777 /* do an INIT IPI: deassert RESET */ 778 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 779 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 780 781 /* wait for pending status end */ 782 DELAY(10000); /* wait ~10mS */ 783 lapic_ipi_wait(-1); 784 785 /* 786 * next we do a STARTUP IPI: the previous INIT IPI might still be 787 * latched, (P5 bug) this 1st STARTUP would then terminate 788 * immediately, and the previously started INIT IPI would continue. OR 789 * the previous INIT IPI has already run. and this STARTUP IPI will 790 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 791 * will run. 792 */ 793 794 /* do a STARTUP IPI */ 795 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 796 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 797 vector, apic_id); 798 lapic_ipi_wait(-1); 799 DELAY(200); /* wait ~200uS */ 800 801 /* 802 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 803 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 804 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 805 * recognized after hardware RESET or INIT IPI. 806 */ 807 808 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 809 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 810 vector, apic_id); 811 lapic_ipi_wait(-1); 812 DELAY(200); /* wait ~200uS */ 813 814 /* Wait up to 5 seconds for it to start. */ 815 for (ms = 0; ms < 5000; ms++) { 816 if (mp_naps > cpus) 817 return 1; /* return SUCCESS */ 818 DELAY(1000); 819 } 820 return 0; /* return FAILURE */ 821} 822 823/* 824 * Flush the TLB on all other CPU's 825 */ 826static void 827smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 828{ 829 u_int ncpu; 830 831 ncpu = mp_ncpus - 1; /* does not shootdown self */ 832 if (ncpu < 1) 833 return; /* no other cpus */ 834 mtx_assert(&smp_ipi_mtx, MA_OWNED); 835 smp_tlb_addr1 = addr1; 836 smp_tlb_addr2 = addr2; 837 atomic_store_rel_int(&smp_tlb_wait, 0); 838 ipi_all_but_self(vector); 839 while (smp_tlb_wait < ncpu) 840 ia32_pause(); 841} 842 843static void 844smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 845{ 846 int ncpu, othercpus; 847 848 othercpus = mp_ncpus - 1; 849 if (mask == (u_int)-1) { 850 ncpu = othercpus; 851 if (ncpu < 1) 852 return; 853 } else { 854 mask &= ~PCPU_GET(cpumask); 855 if (mask == 0) 856 return; 857 ncpu = bitcount32(mask); 858 if (ncpu > othercpus) { 859 /* XXX this should be a panic offence */ 860 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 861 ncpu, othercpus); 862 ncpu = othercpus; 863 } 864 /* XXX should be a panic, implied by mask == 0 above */ 865 if (ncpu < 1) 866 return; 867 } 868 mtx_assert(&smp_ipi_mtx, MA_OWNED); 869 smp_tlb_addr1 = addr1; 870 smp_tlb_addr2 = addr2; 871 atomic_store_rel_int(&smp_tlb_wait, 0); 872 if (mask == (u_int)-1) 873 ipi_all_but_self(vector); 874 else 875 ipi_selected(mask, vector); 876 while (smp_tlb_wait < ncpu) 877 ia32_pause(); 878} 879 880void 881smp_cache_flush(void) 882{ 883 884 if (smp_started) 885 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 886} 887 888void 889smp_invltlb(void) 890{ 891 892 if (smp_started) { 893 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 894 } 895} 896 897void 898smp_invlpg(vm_offset_t addr) 899{ 900 901 if (smp_started) 902 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 903} 904 905void 906smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 907{ 908 909 if (smp_started) { 910 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 911 } 912} 913 914void 915smp_masked_invltlb(u_int mask) 916{ 917 918 if (smp_started) { 919 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 920 } 921} 922 923void 924smp_masked_invlpg(u_int mask, vm_offset_t addr) 925{ 926 927 if (smp_started) { 928 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 929 } 930} 931 932void 933smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 934{ 935 936 if (smp_started) { 937 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 938 } 939} 940 941void 942ipi_bitmap_handler(struct trapframe frame) 943{ 944 int cpu = PCPU_GET(cpuid); 945 u_int ipi_bitmap; 946 947 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 948 949#ifdef IPI_PREEMPTION 950 if (ipi_bitmap & IPI_PREEMPT) { 951 mtx_lock_spin(&sched_lock); 952 /* Don't preempt the idle thread */ 953 if (curthread->td_priority < PRI_MIN_IDLE) { 954 struct thread *running_thread = curthread; 955 if (running_thread->td_critnest > 1) 956 running_thread->td_owepreempt = 1; 957 else 958 mi_switch(SW_INVOL | SW_PREEMPT, NULL); 959 } 960 mtx_unlock_spin(&sched_lock); 961 } 962#endif 963 964 /* Nothing to do for AST */ 965} 966 967/* 968 * send an IPI to a set of cpus. 969 */ 970void 971ipi_selected(u_int32_t cpus, u_int ipi) 972{ 973 int cpu; 974 u_int bitmap = 0; 975 u_int old_pending; 976 u_int new_pending; 977 978 if (IPI_IS_BITMAPED(ipi)) { 979 bitmap = 1 << ipi; 980 ipi = IPI_BITMAP_VECTOR; 981 } 982 983#ifdef STOP_NMI 984 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 985 ipi_nmi_selected(cpus); 986 return; 987 } 988#endif 989 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 990 while ((cpu = ffs(cpus)) != 0) { 991 cpu--; 992 cpus &= ~(1 << cpu); 993 994 KASSERT(cpu_apic_ids[cpu] != -1, 995 ("IPI to non-existent CPU %d", cpu)); 996 997 if (bitmap) { 998 do { 999 old_pending = cpu_ipi_pending[cpu]; 1000 new_pending = old_pending | bitmap; 1001 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1002 1003 if (old_pending) 1004 continue; 1005 } 1006 1007 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1008 } 1009 1010} 1011 1012/* 1013 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 1014 */ 1015void 1016ipi_all(u_int ipi) 1017{ 1018 1019 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1020 ipi_selected(all_cpus, ipi); 1021 return; 1022 } 1023 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1024 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1025} 1026 1027/* 1028 * send an IPI to all CPUs EXCEPT myself 1029 */ 1030void 1031ipi_all_but_self(u_int ipi) 1032{ 1033 1034 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1035 ipi_selected(PCPU_GET(other_cpus), ipi); 1036 return; 1037 } 1038 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1039 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1040} 1041 1042/* 1043 * send an IPI to myself 1044 */ 1045void 1046ipi_self(u_int ipi) 1047{ 1048 1049 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1050 ipi_selected(PCPU_GET(cpumask), ipi); 1051 return; 1052 } 1053 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1054 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1055} 1056 1057#ifdef STOP_NMI 1058/* 1059 * send NMI IPI to selected CPUs 1060 */ 1061 1062#define BEFORE_SPIN 1000000 1063 1064void 1065ipi_nmi_selected(u_int32_t cpus) 1066{ 1067 int cpu; 1068 register_t icrlo; 1069 1070 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1071 | APIC_TRIGMOD_EDGE; 1072 1073 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1074 1075 atomic_set_int(&ipi_nmi_pending, cpus); 1076 1077 while ((cpu = ffs(cpus)) != 0) { 1078 cpu--; 1079 cpus &= ~(1 << cpu); 1080 1081 KASSERT(cpu_apic_ids[cpu] != -1, 1082 ("IPI NMI to non-existent CPU %d", cpu)); 1083 1084 /* Wait for an earlier IPI to finish. */ 1085 if (!lapic_ipi_wait(BEFORE_SPIN)) 1086 panic("ipi_nmi_selected: previous IPI has not cleared"); 1087 1088 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1089 } 1090} 1091 1092int 1093ipi_nmi_handler(void) 1094{ 1095 int cpumask = PCPU_GET(cpumask); 1096 1097 if (!(ipi_nmi_pending & cpumask)) 1098 return 1; 1099 1100 atomic_clear_int(&ipi_nmi_pending, cpumask); 1101 cpustop_handler(); 1102 return 0; 1103} 1104 1105#endif /* STOP_NMI */ 1106 1107/* 1108 * Handle an IPI_STOP by saving our current context and spinning until we 1109 * are resumed. 1110 */ 1111void 1112cpustop_handler(void) 1113{ 1114 int cpu = PCPU_GET(cpuid); 1115 int cpumask = PCPU_GET(cpumask); 1116 1117 savectx(&stoppcbs[cpu]); 1118 1119 /* Indicate that we are stopped */ 1120 atomic_set_int(&stopped_cpus, cpumask); 1121 1122 /* Wait for restart */ 1123 while (!(started_cpus & cpumask)) 1124 ia32_pause(); 1125 1126 atomic_clear_int(&started_cpus, cpumask); 1127 atomic_clear_int(&stopped_cpus, cpumask); 1128 1129 if (cpu == 0 && cpustop_restartfunc != NULL) { 1130 cpustop_restartfunc(); 1131 cpustop_restartfunc = NULL; 1132 } 1133} 1134 1135/* 1136 * This is called once the rest of the system is up and running and we're 1137 * ready to let the AP's out of the pen. 1138 */ 1139static void 1140release_aps(void *dummy __unused) 1141{ 1142 1143 if (mp_ncpus == 1) 1144 return; 1145 mtx_lock_spin(&sched_lock); 1146 atomic_store_rel_int(&aps_ready, 1); 1147 while (smp_started == 0) 1148 ia32_pause(); 1149 mtx_unlock_spin(&sched_lock); 1150} 1151SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1152 1153static int 1154sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1155{ 1156 u_int mask; 1157 int error; 1158 1159 mask = hlt_cpus_mask; 1160 error = sysctl_handle_int(oidp, &mask, 0, req); 1161 if (error || !req->newptr) 1162 return (error); 1163 1164 if (logical_cpus_mask != 0 && 1165 (mask & logical_cpus_mask) == logical_cpus_mask) 1166 hlt_logical_cpus = 1; 1167 else 1168 hlt_logical_cpus = 0; 1169 1170 if (! hyperthreading_allowed) 1171 mask |= hyperthreading_cpus_mask; 1172 1173 if ((mask & all_cpus) == all_cpus) 1174 mask &= ~(1<<0); 1175 hlt_cpus_mask = mask; 1176 return (error); 1177} 1178SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1179 0, 0, sysctl_hlt_cpus, "IU", 1180 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1181 1182static int 1183sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1184{ 1185 int disable, error; 1186 1187 disable = hlt_logical_cpus; 1188 error = sysctl_handle_int(oidp, &disable, 0, req); 1189 if (error || !req->newptr) 1190 return (error); 1191 1192 if (disable) 1193 hlt_cpus_mask |= logical_cpus_mask; 1194 else 1195 hlt_cpus_mask &= ~logical_cpus_mask; 1196 1197 if (! hyperthreading_allowed) 1198 hlt_cpus_mask |= hyperthreading_cpus_mask; 1199 1200 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1201 hlt_cpus_mask &= ~(1<<0); 1202 1203 hlt_logical_cpus = disable; 1204 return (error); 1205} 1206 1207static int 1208sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1209{ 1210 int allowed, error; 1211 1212 allowed = hyperthreading_allowed; 1213 error = sysctl_handle_int(oidp, &allowed, 0, req); 1214 if (error || !req->newptr) 1215 return (error); 1216 1217 if (allowed) 1218 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1219 else 1220 hlt_cpus_mask |= hyperthreading_cpus_mask; 1221 1222 if (logical_cpus_mask != 0 && 1223 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1224 hlt_logical_cpus = 1; 1225 else 1226 hlt_logical_cpus = 0; 1227 1228 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1229 hlt_cpus_mask &= ~(1<<0); 1230 1231 hyperthreading_allowed = allowed; 1232 return (error); 1233} 1234 1235static void 1236cpu_hlt_setup(void *dummy __unused) 1237{ 1238 1239 if (logical_cpus_mask != 0) { 1240 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1241 &hlt_logical_cpus); 1242 sysctl_ctx_init(&logical_cpu_clist); 1243 SYSCTL_ADD_PROC(&logical_cpu_clist, 1244 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1245 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1246 sysctl_hlt_logical_cpus, "IU", ""); 1247 SYSCTL_ADD_UINT(&logical_cpu_clist, 1248 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1249 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1250 &logical_cpus_mask, 0, ""); 1251 1252 if (hlt_logical_cpus) 1253 hlt_cpus_mask |= logical_cpus_mask; 1254 1255 /* 1256 * If necessary for security purposes, force 1257 * hyperthreading off, regardless of the value 1258 * of hlt_logical_cpus. 1259 */ 1260 if (hyperthreading_cpus_mask) { 1261 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1262 &hyperthreading_allowed); 1263 SYSCTL_ADD_PROC(&logical_cpu_clist, 1264 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1265 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1266 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1267 if (! hyperthreading_allowed) 1268 hlt_cpus_mask |= hyperthreading_cpus_mask; 1269 } 1270 } 1271} 1272SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1273 1274int 1275mp_grab_cpu_hlt(void) 1276{ 1277 u_int mask = PCPU_GET(cpumask); 1278#ifdef MP_WATCHDOG 1279 u_int cpuid = PCPU_GET(cpuid); 1280#endif 1281 int retval; 1282 1283#ifdef MP_WATCHDOG 1284 ap_watchdog(cpuid); 1285#endif 1286 1287 retval = mask & hlt_cpus_mask; 1288 while (mask & hlt_cpus_mask) 1289 __asm __volatile("sti; hlt" : : : "memory"); 1290 return (retval); 1291} 1292