mp_machdep.c revision 153241
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 153241 2005-12-08 18:33:30Z jhb $"); 29 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33#include "opt_sched.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#ifdef GPROF 39#include <sys/gmon.h> 40#endif 41#include <sys/kernel.h> 42#include <sys/ktr.h> 43#include <sys/lock.h> 44#include <sys/malloc.h> 45#include <sys/memrange.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/proc.h> 49#include <sys/smp.h> 50#include <sys/sysctl.h> 51 52#include <vm/vm.h> 53#include <vm/vm_param.h> 54#include <vm/pmap.h> 55#include <vm/vm_kern.h> 56#include <vm/vm_extern.h> 57 58#include <machine/apicreg.h> 59#include <machine/clock.h> 60#include <machine/md_var.h> 61#include <machine/mp_watchdog.h> 62#include <machine/pcb.h> 63#include <machine/psl.h> 64#include <machine/smp.h> 65#include <machine/specialreg.h> 66#include <machine/tss.h> 67 68#define WARMBOOT_TARGET 0 69#define WARMBOOT_OFF (KERNBASE + 0x0467) 70#define WARMBOOT_SEG (KERNBASE + 0x0469) 71 72#define CMOS_REG (0x70) 73#define CMOS_DATA (0x71) 74#define BIOS_RESET (0x0f) 75#define BIOS_WARM (0x0a) 76 77/* lock region used by kernel profiling */ 78int mcount_lock; 79 80int mp_naps; /* # of Applications processors */ 81int boot_cpu_id = -1; /* designated BSP */ 82extern int nkpt; 83 84/* 85 * CPU topology map datastructures for HTT. 86 */ 87static struct cpu_group mp_groups[MAXCPU]; 88static struct cpu_top mp_top; 89 90/* AP uses this during bootstrap. Do not staticize. */ 91char *bootSTK; 92static int bootAP; 93 94/* Free these after use */ 95void *bootstacks[MAXCPU]; 96 97/* Temporary holder for double fault stack */ 98char *doublefault_stack; 99 100/* Hotwire a 0->4MB V==P mapping */ 101extern pt_entry_t *KPTphys; 102 103/* SMP page table page */ 104extern pt_entry_t *SMPpt; 105 106struct pcb stoppcbs[MAXCPU]; 107 108/* Variables needed for SMP tlb shootdown. */ 109vm_offset_t smp_tlb_addr1; 110vm_offset_t smp_tlb_addr2; 111volatile int smp_tlb_wait; 112 113extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 114 115#ifdef STOP_NMI 116volatile cpumask_t ipi_nmi_pending; 117 118static void ipi_nmi_selected(u_int32_t cpus); 119#endif 120 121/* 122 * Local data and functions. 123 */ 124 125#ifdef STOP_NMI 126/* 127 * Provide an alternate method of stopping other CPUs. If another CPU has 128 * disabled interrupts the conventional STOP IPI will be blocked. This 129 * NMI-based stop should get through in that case. 130 */ 131static int stop_cpus_with_nmi = 1; 132SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW, 133 &stop_cpus_with_nmi, 0, ""); 134TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi); 135#else 136#define stop_cpus_with_nmi 0 137#endif 138 139static u_int logical_cpus; 140 141/* used to hold the AP's until we are ready to release them */ 142static struct mtx ap_boot_mtx; 143 144/* Set to 1 once we're ready to let the APs out of the pen. */ 145static volatile int aps_ready = 0; 146 147/* 148 * Store data from cpu_add() until later in the boot when we actually setup 149 * the APs. 150 */ 151struct cpu_info { 152 int cpu_present:1; 153 int cpu_bsp:1; 154 int cpu_disabled:1; 155} static cpu_info[MAXCPU]; 156static int cpu_apic_ids[MAXCPU]; 157 158/* Holds pending bitmap based IPIs per CPU */ 159static volatile u_int cpu_ipi_pending[MAXCPU]; 160 161static u_int boot_address; 162 163static void set_logical_apic_ids(void); 164static int start_all_aps(void); 165static int start_ap(int apic_id); 166static void release_aps(void *dummy); 167 168static int hlt_logical_cpus; 169static u_int hyperthreading_cpus; 170static cpumask_t hyperthreading_cpus_mask; 171static int hyperthreading_allowed = 1; 172static struct sysctl_ctx_list logical_cpu_clist; 173static u_int bootMP_size; 174 175static void 176mem_range_AP_init(void) 177{ 178 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 179 mem_range_softc.mr_op->initAP(&mem_range_softc); 180} 181 182void 183mp_topology(void) 184{ 185 struct cpu_group *group; 186 int logical_cpus; 187 int apic_id; 188 int groups; 189 int cpu; 190 191 /* Build the smp_topology map. */ 192 /* Nothing to do if there is no HTT support. */ 193 if ((cpu_feature & CPUID_HTT) == 0) 194 return; 195 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 196 if (logical_cpus <= 1) 197 return; 198 group = &mp_groups[0]; 199 groups = 1; 200 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 201 if (!cpu_info[apic_id].cpu_present) 202 continue; 203 /* 204 * If the current group has members and we're not a logical 205 * cpu, create a new group. 206 */ 207 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 208 group++; 209 groups++; 210 } 211 group->cg_count++; 212 group->cg_mask |= 1 << cpu; 213 cpu++; 214 } 215 216 mp_top.ct_count = groups; 217 mp_top.ct_group = mp_groups; 218 smp_topology = &mp_top; 219} 220 221/* 222 * Calculate usable address in base memory for AP trampoline code. 223 */ 224u_int 225mp_bootaddress(u_int basemem) 226{ 227 228 bootMP_size = mptramp_end - mptramp_start; 229 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 230 if (((basemem * 1024) - boot_address) < bootMP_size) 231 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 232 /* 3 levels of page table pages */ 233 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 234 235 return mptramp_pagetables; 236} 237 238void 239cpu_add(u_int apic_id, char boot_cpu) 240{ 241 242 if (apic_id >= MAXCPU) { 243 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 244 apic_id, MAXCPU - 1); 245 return; 246 } 247 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 248 apic_id)); 249 cpu_info[apic_id].cpu_present = 1; 250 if (boot_cpu) { 251 KASSERT(boot_cpu_id == -1, 252 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 253 boot_cpu_id)); 254 boot_cpu_id = apic_id; 255 cpu_info[apic_id].cpu_bsp = 1; 256 } 257 mp_ncpus++; 258 if (apic_id > mp_maxid) 259 mp_maxid = apic_id; 260 if (bootverbose) 261 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 262 "AP"); 263 264} 265 266void 267cpu_mp_setmaxid(void) 268{ 269 270 /* 271 * mp_maxid should be already set by calls to cpu_add(). 272 * Just sanity check its value here. 273 */ 274 if (mp_ncpus == 0) 275 KASSERT(mp_maxid == 0, 276 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 277 else if (mp_ncpus == 1) 278 mp_maxid = 0; 279 else 280 KASSERT(mp_maxid >= mp_ncpus - 1, 281 ("%s: counters out of sync: max %d, count %d", __func__, 282 mp_maxid, mp_ncpus)); 283 284} 285 286int 287cpu_mp_probe(void) 288{ 289 290 /* 291 * Always record BSP in CPU map so that the mbuf init code works 292 * correctly. 293 */ 294 all_cpus = 1; 295 if (mp_ncpus == 0) { 296 /* 297 * No CPUs were found, so this must be a UP system. Setup 298 * the variables to represent a system with a single CPU 299 * with an id of 0. 300 */ 301 mp_ncpus = 1; 302 return (0); 303 } 304 305 /* At least one CPU was found. */ 306 if (mp_ncpus == 1) { 307 /* 308 * One CPU was found, so this must be a UP system with 309 * an I/O APIC. 310 */ 311 mp_maxid = 0; 312 return (0); 313 } 314 315 /* At least two CPUs were found. */ 316 return (1); 317} 318 319/* 320 * Initialize the IPI handlers and start up the AP's. 321 */ 322void 323cpu_mp_start(void) 324{ 325 int i; 326 u_int threads_per_cache, p[4]; 327 328 /* Initialize the logical ID to APIC ID table. */ 329 for (i = 0; i < MAXCPU; i++) { 330 cpu_apic_ids[i] = -1; 331 cpu_ipi_pending[i] = 0; 332 } 333 334 /* Install an inter-CPU IPI for TLB invalidation */ 335 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 336 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 337 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 338 339 /* Install an inter-CPU IPI for all-CPU rendezvous */ 340 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 341 342 /* Install generic inter-CPU IPI handler */ 343 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 344 SDT_SYSIGT, SEL_KPL, 0); 345 346 /* Install an inter-CPU IPI for CPU stop/restart */ 347 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 348 349 /* Set boot_cpu_id if needed. */ 350 if (boot_cpu_id == -1) { 351 boot_cpu_id = PCPU_GET(apic_id); 352 cpu_info[boot_cpu_id].cpu_bsp = 1; 353 } else 354 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 355 ("BSP's APIC ID doesn't match boot_cpu_id")); 356 cpu_apic_ids[0] = boot_cpu_id; 357 358 /* Start each Application Processor */ 359 start_all_aps(); 360 361 /* Setup the initial logical CPUs info. */ 362 logical_cpus = logical_cpus_mask = 0; 363 if (cpu_feature & CPUID_HTT) 364 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 365 366 /* 367 * Work out if hyperthreading is *really* enabled. This 368 * is made really ugly by the fact that processors lie: Dual 369 * core processors claim to be hyperthreaded even when they're 370 * not, presumably because they want to be treated the same 371 * way as HTT with respect to per-cpu software licensing. 372 * At the time of writing (May 12, 2005) the only hyperthreaded 373 * cpus are from Intel, and Intel's dual-core processors can be 374 * identified via the "deterministic cache parameters" cpuid 375 * calls. 376 */ 377 /* 378 * First determine if this is an Intel processor which claims 379 * to have hyperthreading support. 380 */ 381 if ((cpu_feature & CPUID_HTT) && 382 (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 383 /* 384 * If the "deterministic cache parameters" cpuid calls 385 * are available, use them. 386 */ 387 if (cpu_high >= 4) { 388 /* Ask the processor about up to 32 caches. */ 389 for (i = 0; i < 32; i++) { 390 cpuid_count(4, i, p); 391 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 392 if (hyperthreading_cpus < threads_per_cache) 393 hyperthreading_cpus = threads_per_cache; 394 if ((p[0] & 0x1f) == 0) 395 break; 396 } 397 } 398 399 /* 400 * If the deterministic cache parameters are not 401 * available, or if no caches were reported to exist, 402 * just accept what the HTT flag indicated. 403 */ 404 if (hyperthreading_cpus == 0) 405 hyperthreading_cpus = logical_cpus; 406 } 407 408 set_logical_apic_ids(); 409} 410 411 412/* 413 * Print various information about the SMP system hardware and setup. 414 */ 415void 416cpu_mp_announce(void) 417{ 418 int i, x; 419 420 /* List CPUs */ 421 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 422 for (i = 1, x = 0; x < MAXCPU; x++) { 423 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 424 continue; 425 if (cpu_info[x].cpu_disabled) 426 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 427 else { 428 KASSERT(i < mp_ncpus, 429 ("mp_ncpus and actual cpus are out of whack")); 430 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 431 } 432 } 433} 434 435/* 436 * AP CPU's call this to initialize themselves. 437 */ 438void 439init_secondary(void) 440{ 441 struct pcpu *pc; 442 u_int64_t msr, cr0; 443 int cpu, gsel_tss; 444 445 /* Set by the startup code for us to use */ 446 cpu = bootAP; 447 448 /* Init tss */ 449 common_tss[cpu] = common_tss[0]; 450 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 451 common_tss[cpu].tss_iobase = sizeof(struct amd64tss); 452 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 453 454 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 455 ssdtosyssd(&gdt_segs[GPROC0_SEL], 456 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 457 458 lgdt(&r_gdt); /* does magic intra-segment return */ 459 460 /* Get per-cpu data */ 461 pc = &__pcpu[cpu]; 462 463 /* prime data page for it to use */ 464 pcpu_init(pc, cpu, sizeof(struct pcpu)); 465 pc->pc_apic_id = cpu_apic_ids[cpu]; 466 pc->pc_prvspace = pc; 467 pc->pc_curthread = 0; 468 pc->pc_tssp = &common_tss[cpu]; 469 pc->pc_rsp0 = 0; 470 471 wrmsr(MSR_FSBASE, 0); /* User value */ 472 wrmsr(MSR_GSBASE, (u_int64_t)pc); 473 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 474 475 lidt(&r_idt); 476 477 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 478 ltr(gsel_tss); 479 480 /* 481 * Set to a known state: 482 * Set by mpboot.s: CR0_PG, CR0_PE 483 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 484 */ 485 cr0 = rcr0(); 486 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 487 load_cr0(cr0); 488 489 /* Set up the fast syscall stuff */ 490 msr = rdmsr(MSR_EFER) | EFER_SCE; 491 wrmsr(MSR_EFER, msr); 492 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 493 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 494 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 495 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 496 wrmsr(MSR_STAR, msr); 497 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 498 499 /* Disable local APIC just to be sure. */ 500 lapic_disable(); 501 502 /* signal our startup to the BSP. */ 503 mp_naps++; 504 505 /* Spin until the BSP releases the AP's. */ 506 while (!aps_ready) 507 ia32_pause(); 508 509 /* set up CPU registers and state */ 510 cpu_setregs(); 511 512 /* set up SSE/NX registers */ 513 initializecpu(); 514 515 /* set up FPU state on the AP */ 516 fpuinit(); 517 518 /* A quick check from sanity claus */ 519 if (PCPU_GET(apic_id) != lapic_id()) { 520 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 521 printf("SMP: actual apic_id = %d\n", lapic_id()); 522 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 523 panic("cpuid mismatch! boom!!"); 524 } 525 526 /* Initialize curthread. */ 527 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 528 PCPU_SET(curthread, PCPU_GET(idlethread)); 529 530 mtx_lock_spin(&ap_boot_mtx); 531 532 /* Init local apic for irq's */ 533 lapic_setup(); 534 535 /* Set memory range attributes for this CPU to match the BSP */ 536 mem_range_AP_init(); 537 538 smp_cpus++; 539 540 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 541 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 542 543 /* Determine if we are a logical CPU. */ 544 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 545 logical_cpus_mask |= PCPU_GET(cpumask); 546 547 /* Determine if we are a hyperthread. */ 548 if (hyperthreading_cpus > 1 && 549 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 550 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 551 552 /* Build our map of 'other' CPUs. */ 553 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 554 555 if (bootverbose) 556 lapic_dump("AP"); 557 558 if (smp_cpus == mp_ncpus) { 559 /* enable IPI's, tlb shootdown, freezes etc */ 560 atomic_store_rel_int(&smp_started, 1); 561 smp_active = 1; /* historic */ 562 } 563 564 mtx_unlock_spin(&ap_boot_mtx); 565 566 /* wait until all the AP's are up */ 567 while (smp_started == 0) 568 ia32_pause(); 569 570 /* ok, now grab sched_lock and enter the scheduler */ 571 mtx_lock_spin(&sched_lock); 572 573 /* 574 * Correct spinlock nesting. The idle thread context that we are 575 * borrowing was created so that it would start out with a single 576 * spin lock (sched_lock) held in fork_trampoline(). Since we've 577 * explicitly acquired locks in this function, the nesting count 578 * is now 2 rather than 1. Since we are nested, calling 579 * spinlock_exit() will simply adjust the counts without allowing 580 * spin lock using code to interrupt us. 581 */ 582 spinlock_exit(); 583 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count")); 584 585 binuptime(PCPU_PTR(switchtime)); 586 PCPU_SET(switchticks, ticks); 587 588 cpu_throw(NULL, choosethread()); /* doesn't return */ 589 590 panic("scheduler returned us to %s", __func__); 591 /* NOTREACHED */ 592} 593 594/******************************************************************* 595 * local functions and data 596 */ 597 598/* 599 * Set the APIC logical IDs. 600 * 601 * We want to cluster logical CPU's within the same APIC ID cluster. 602 * Since logical CPU's are aligned simply filling in the clusters in 603 * APIC ID order works fine. Note that this does not try to balance 604 * the number of CPU's in each cluster. (XXX?) 605 */ 606static void 607set_logical_apic_ids(void) 608{ 609 u_int apic_id, cluster, cluster_id; 610 611 /* Force us to allocate cluster 0 at the start. */ 612 cluster = -1; 613 cluster_id = APIC_MAX_INTRACLUSTER_ID; 614 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 615 if (!cpu_info[apic_id].cpu_present) 616 continue; 617 if (cluster_id == APIC_MAX_INTRACLUSTER_ID) { 618 cluster = ioapic_next_logical_cluster(); 619 cluster_id = 0; 620 } else 621 cluster_id++; 622 if (bootverbose) 623 printf("APIC ID: physical %u, logical %u:%u\n", 624 apic_id, cluster, cluster_id); 625 lapic_set_logical_id(apic_id, cluster, cluster_id); 626 } 627} 628 629/* 630 * start each AP in our list 631 */ 632static int 633start_all_aps(void) 634{ 635 vm_offset_t va = boot_address + KERNBASE; 636 u_int64_t *pt4, *pt3, *pt2; 637 u_int32_t mpbioswarmvec; 638 int apic_id, cpu, i; 639 u_char mpbiosreason; 640 641 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 642 643 /* install the AP 1st level boot code */ 644 pmap_kenter(va, boot_address); 645 pmap_invalidate_page(kernel_pmap, va); 646 bcopy(mptramp_start, (void *)va, bootMP_size); 647 648 /* Locate the page tables, they'll be below the trampoline */ 649 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 650 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 651 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 652 653 /* Create the initial 1GB replicated page tables */ 654 for (i = 0; i < 512; i++) { 655 /* Each slot of the level 4 pages points to the same level 3 page */ 656 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 657 pt4[i] |= PG_V | PG_RW | PG_U; 658 659 /* Each slot of the level 3 pages points to the same level 2 page */ 660 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 661 pt3[i] |= PG_V | PG_RW | PG_U; 662 663 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 664 pt2[i] = i * (2 * 1024 * 1024); 665 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 666 } 667 668 /* save the current value of the warm-start vector */ 669 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 670 outb(CMOS_REG, BIOS_RESET); 671 mpbiosreason = inb(CMOS_DATA); 672 673 /* setup a vector to our boot code */ 674 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 675 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 676 outb(CMOS_REG, BIOS_RESET); 677 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 678 679 /* start each AP */ 680 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 681 682 /* Ignore non-existent CPUs and the BSP. */ 683 if (!cpu_info[apic_id].cpu_present || 684 cpu_info[apic_id].cpu_bsp) 685 continue; 686 687 /* Don't use this CPU if it has been disabled by a tunable. */ 688 if (resource_disabled("lapic", apic_id)) { 689 cpu_info[apic_id].cpu_disabled = 1; 690 mp_ncpus--; 691 continue; 692 } 693 694 cpu++; 695 696 /* save APIC ID for this logical ID */ 697 cpu_apic_ids[cpu] = apic_id; 698 699 /* allocate and set up an idle stack data page */ 700 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 701 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE); 702 703 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 704 bootAP = cpu; 705 706 /* attempt to start the Application Processor */ 707 if (!start_ap(apic_id)) { 708 /* restore the warmstart vector */ 709 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 710 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 711 } 712 713 all_cpus |= (1 << cpu); /* record AP in CPU map */ 714 } 715 716 /* build our map of 'other' CPUs */ 717 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 718 719 /* restore the warmstart vector */ 720 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 721 722 outb(CMOS_REG, BIOS_RESET); 723 outb(CMOS_DATA, mpbiosreason); 724 725 /* number of APs actually started */ 726 return mp_naps; 727} 728 729 730/* 731 * This function starts the AP (application processor) identified 732 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 733 * to accomplish this. This is necessary because of the nuances 734 * of the different hardware we might encounter. It isn't pretty, 735 * but it seems to work. 736 */ 737static int 738start_ap(int apic_id) 739{ 740 int vector, ms; 741 int cpus; 742 743 /* calculate the vector */ 744 vector = (boot_address >> 12) & 0xff; 745 746 /* used as a watchpoint to signal AP startup */ 747 cpus = mp_naps; 748 749 /* 750 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 751 * and running the target CPU. OR this INIT IPI might be latched (P5 752 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 753 * ignored. 754 */ 755 756 /* do an INIT IPI: assert RESET */ 757 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 758 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 759 760 /* wait for pending status end */ 761 lapic_ipi_wait(-1); 762 763 /* do an INIT IPI: deassert RESET */ 764 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 765 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 766 767 /* wait for pending status end */ 768 DELAY(10000); /* wait ~10mS */ 769 lapic_ipi_wait(-1); 770 771 /* 772 * next we do a STARTUP IPI: the previous INIT IPI might still be 773 * latched, (P5 bug) this 1st STARTUP would then terminate 774 * immediately, and the previously started INIT IPI would continue. OR 775 * the previous INIT IPI has already run. and this STARTUP IPI will 776 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 777 * will run. 778 */ 779 780 /* do a STARTUP IPI */ 781 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 782 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 783 vector, apic_id); 784 lapic_ipi_wait(-1); 785 DELAY(200); /* wait ~200uS */ 786 787 /* 788 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 789 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 790 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 791 * recognized after hardware RESET or INIT IPI. 792 */ 793 794 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 795 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 796 vector, apic_id); 797 lapic_ipi_wait(-1); 798 DELAY(200); /* wait ~200uS */ 799 800 /* Wait up to 5 seconds for it to start. */ 801 for (ms = 0; ms < 5000; ms++) { 802 if (mp_naps > cpus) 803 return 1; /* return SUCCESS */ 804 DELAY(1000); 805 } 806 return 0; /* return FAILURE */ 807} 808 809/* 810 * Flush the TLB on all other CPU's 811 */ 812static void 813smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 814{ 815 u_int ncpu; 816 817 ncpu = mp_ncpus - 1; /* does not shootdown self */ 818 if (ncpu < 1) 819 return; /* no other cpus */ 820 mtx_assert(&smp_ipi_mtx, MA_OWNED); 821 smp_tlb_addr1 = addr1; 822 smp_tlb_addr2 = addr2; 823 atomic_store_rel_int(&smp_tlb_wait, 0); 824 ipi_all_but_self(vector); 825 while (smp_tlb_wait < ncpu) 826 ia32_pause(); 827} 828 829static void 830smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 831{ 832 int ncpu, othercpus; 833 834 othercpus = mp_ncpus - 1; 835 if (mask == (u_int)-1) { 836 ncpu = othercpus; 837 if (ncpu < 1) 838 return; 839 } else { 840 mask &= ~PCPU_GET(cpumask); 841 if (mask == 0) 842 return; 843 ncpu = bitcount32(mask); 844 if (ncpu > othercpus) { 845 /* XXX this should be a panic offence */ 846 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 847 ncpu, othercpus); 848 ncpu = othercpus; 849 } 850 /* XXX should be a panic, implied by mask == 0 above */ 851 if (ncpu < 1) 852 return; 853 } 854 mtx_assert(&smp_ipi_mtx, MA_OWNED); 855 smp_tlb_addr1 = addr1; 856 smp_tlb_addr2 = addr2; 857 atomic_store_rel_int(&smp_tlb_wait, 0); 858 if (mask == (u_int)-1) 859 ipi_all_but_self(vector); 860 else 861 ipi_selected(mask, vector); 862 while (smp_tlb_wait < ncpu) 863 ia32_pause(); 864} 865 866void 867smp_invltlb(void) 868{ 869 870 if (smp_started) { 871 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 872 } 873} 874 875void 876smp_invlpg(vm_offset_t addr) 877{ 878 879 if (smp_started) 880 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 881} 882 883void 884smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 885{ 886 887 if (smp_started) { 888 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 889 } 890} 891 892void 893smp_masked_invltlb(u_int mask) 894{ 895 896 if (smp_started) { 897 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 898 } 899} 900 901void 902smp_masked_invlpg(u_int mask, vm_offset_t addr) 903{ 904 905 if (smp_started) { 906 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 907 } 908} 909 910void 911smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 912{ 913 914 if (smp_started) { 915 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 916 } 917} 918 919void 920ipi_bitmap_handler(struct clockframe frame) 921{ 922 int cpu = PCPU_GET(cpuid); 923 u_int ipi_bitmap; 924 925 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 926 927#ifdef IPI_PREEMPTION 928 if (ipi_bitmap & IPI_PREEMPT) { 929 mtx_lock_spin(&sched_lock); 930 /* Don't preempt the idle thread */ 931 if (curthread->td_priority < PRI_MIN_IDLE) { 932 struct thread *running_thread = curthread; 933 if (running_thread->td_critnest > 1) 934 running_thread->td_owepreempt = 1; 935 else 936 mi_switch(SW_INVOL | SW_PREEMPT, NULL); 937 } 938 mtx_unlock_spin(&sched_lock); 939 } 940#endif 941 942 /* Nothing to do for AST */ 943} 944 945/* 946 * send an IPI to a set of cpus. 947 */ 948void 949ipi_selected(u_int32_t cpus, u_int ipi) 950{ 951 int cpu; 952 u_int bitmap = 0; 953 u_int old_pending; 954 u_int new_pending; 955 956 if (IPI_IS_BITMAPED(ipi)) { 957 bitmap = 1 << ipi; 958 ipi = IPI_BITMAP_VECTOR; 959 } 960 961#ifdef STOP_NMI 962 if (ipi == IPI_STOP && stop_cpus_with_nmi) { 963 ipi_nmi_selected(cpus); 964 return; 965 } 966#endif 967 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 968 while ((cpu = ffs(cpus)) != 0) { 969 cpu--; 970 cpus &= ~(1 << cpu); 971 972 KASSERT(cpu_apic_ids[cpu] != -1, 973 ("IPI to non-existent CPU %d", cpu)); 974 975 if (bitmap) { 976 do { 977 old_pending = cpu_ipi_pending[cpu]; 978 new_pending = old_pending | bitmap; 979 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 980 981 if (old_pending) 982 continue; 983 } 984 985 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 986 } 987 988} 989 990/* 991 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 992 */ 993void 994ipi_all(u_int ipi) 995{ 996 997 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 998 ipi_selected(all_cpus, ipi); 999 return; 1000 } 1001 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1002 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1003} 1004 1005/* 1006 * send an IPI to all CPUs EXCEPT myself 1007 */ 1008void 1009ipi_all_but_self(u_int ipi) 1010{ 1011 1012 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1013 ipi_selected(PCPU_GET(other_cpus), ipi); 1014 return; 1015 } 1016 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1017 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1018} 1019 1020/* 1021 * send an IPI to myself 1022 */ 1023void 1024ipi_self(u_int ipi) 1025{ 1026 1027 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) { 1028 ipi_selected(PCPU_GET(cpumask), ipi); 1029 return; 1030 } 1031 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1032 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1033} 1034 1035#ifdef STOP_NMI 1036/* 1037 * send NMI IPI to selected CPUs 1038 */ 1039 1040#define BEFORE_SPIN 1000000 1041 1042void 1043ipi_nmi_selected(u_int32_t cpus) 1044{ 1045 int cpu; 1046 register_t icrlo; 1047 1048 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1049 | APIC_TRIGMOD_EDGE; 1050 1051 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1052 1053 atomic_set_int(&ipi_nmi_pending, cpus); 1054 1055 while ((cpu = ffs(cpus)) != 0) { 1056 cpu--; 1057 cpus &= ~(1 << cpu); 1058 1059 KASSERT(cpu_apic_ids[cpu] != -1, 1060 ("IPI NMI to non-existent CPU %d", cpu)); 1061 1062 /* Wait for an earlier IPI to finish. */ 1063 if (!lapic_ipi_wait(BEFORE_SPIN)) 1064 panic("ipi_nmi_selected: previous IPI has not cleared"); 1065 1066 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]); 1067 } 1068} 1069 1070int 1071ipi_nmi_handler(void) 1072{ 1073 int cpumask = PCPU_GET(cpumask); 1074 1075 if (!(ipi_nmi_pending & cpumask)) 1076 return 1; 1077 1078 atomic_clear_int(&ipi_nmi_pending, cpumask); 1079 cpustop_handler(); 1080 return 0; 1081} 1082 1083#endif /* STOP_NMI */ 1084 1085/* 1086 * Handle an IPI_STOP by saving our current context and spinning until we 1087 * are resumed. 1088 */ 1089void 1090cpustop_handler(void) 1091{ 1092 int cpu = PCPU_GET(cpuid); 1093 int cpumask = PCPU_GET(cpumask); 1094 1095 savectx(&stoppcbs[cpu]); 1096 1097 /* Indicate that we are stopped */ 1098 atomic_set_int(&stopped_cpus, cpumask); 1099 1100 /* Wait for restart */ 1101 while (!(started_cpus & cpumask)) 1102 ia32_pause(); 1103 1104 atomic_clear_int(&started_cpus, cpumask); 1105 atomic_clear_int(&stopped_cpus, cpumask); 1106 1107 if (cpu == 0 && cpustop_restartfunc != NULL) { 1108 cpustop_restartfunc(); 1109 cpustop_restartfunc = NULL; 1110 } 1111} 1112 1113/* 1114 * This is called once the rest of the system is up and running and we're 1115 * ready to let the AP's out of the pen. 1116 */ 1117static void 1118release_aps(void *dummy __unused) 1119{ 1120 1121 if (mp_ncpus == 1) 1122 return; 1123 mtx_lock_spin(&sched_lock); 1124 atomic_store_rel_int(&aps_ready, 1); 1125 while (smp_started == 0) 1126 ia32_pause(); 1127 mtx_unlock_spin(&sched_lock); 1128} 1129SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1130 1131static int 1132sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1133{ 1134 u_int mask; 1135 int error; 1136 1137 mask = hlt_cpus_mask; 1138 error = sysctl_handle_int(oidp, &mask, 0, req); 1139 if (error || !req->newptr) 1140 return (error); 1141 1142 if (logical_cpus_mask != 0 && 1143 (mask & logical_cpus_mask) == logical_cpus_mask) 1144 hlt_logical_cpus = 1; 1145 else 1146 hlt_logical_cpus = 0; 1147 1148 if (! hyperthreading_allowed) 1149 mask |= hyperthreading_cpus_mask; 1150 1151 if ((mask & all_cpus) == all_cpus) 1152 mask &= ~(1<<0); 1153 hlt_cpus_mask = mask; 1154 return (error); 1155} 1156SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1157 0, 0, sysctl_hlt_cpus, "IU", 1158 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1159 1160static int 1161sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1162{ 1163 int disable, error; 1164 1165 disable = hlt_logical_cpus; 1166 error = sysctl_handle_int(oidp, &disable, 0, req); 1167 if (error || !req->newptr) 1168 return (error); 1169 1170 if (disable) 1171 hlt_cpus_mask |= logical_cpus_mask; 1172 else 1173 hlt_cpus_mask &= ~logical_cpus_mask; 1174 1175 if (! hyperthreading_allowed) 1176 hlt_cpus_mask |= hyperthreading_cpus_mask; 1177 1178 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1179 hlt_cpus_mask &= ~(1<<0); 1180 1181 hlt_logical_cpus = disable; 1182 return (error); 1183} 1184 1185static int 1186sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1187{ 1188 int allowed, error; 1189 1190 allowed = hyperthreading_allowed; 1191 error = sysctl_handle_int(oidp, &allowed, 0, req); 1192 if (error || !req->newptr) 1193 return (error); 1194 1195 if (allowed) 1196 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1197 else 1198 hlt_cpus_mask |= hyperthreading_cpus_mask; 1199 1200 if (logical_cpus_mask != 0 && 1201 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1202 hlt_logical_cpus = 1; 1203 else 1204 hlt_logical_cpus = 0; 1205 1206 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1207 hlt_cpus_mask &= ~(1<<0); 1208 1209 hyperthreading_allowed = allowed; 1210 return (error); 1211} 1212 1213static void 1214cpu_hlt_setup(void *dummy __unused) 1215{ 1216 1217 if (logical_cpus_mask != 0) { 1218 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1219 &hlt_logical_cpus); 1220 sysctl_ctx_init(&logical_cpu_clist); 1221 SYSCTL_ADD_PROC(&logical_cpu_clist, 1222 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1223 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1224 sysctl_hlt_logical_cpus, "IU", ""); 1225 SYSCTL_ADD_UINT(&logical_cpu_clist, 1226 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1227 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1228 &logical_cpus_mask, 0, ""); 1229 1230 if (hlt_logical_cpus) 1231 hlt_cpus_mask |= logical_cpus_mask; 1232 1233 /* 1234 * If necessary for security purposes, force 1235 * hyperthreading off, regardless of the value 1236 * of hlt_logical_cpus. 1237 */ 1238 if (hyperthreading_cpus_mask) { 1239 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1240 &hyperthreading_allowed); 1241 SYSCTL_ADD_PROC(&logical_cpu_clist, 1242 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1243 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1244 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1245 if (! hyperthreading_allowed) 1246 hlt_cpus_mask |= hyperthreading_cpus_mask; 1247 } 1248 } 1249} 1250SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1251 1252int 1253mp_grab_cpu_hlt(void) 1254{ 1255 u_int mask = PCPU_GET(cpumask); 1256#ifdef MP_WATCHDOG 1257 u_int cpuid = PCPU_GET(cpuid); 1258#endif 1259 int retval; 1260 1261#ifdef MP_WATCHDOG 1262 ap_watchdog(cpuid); 1263#endif 1264 1265 retval = mask & hlt_cpus_mask; 1266 while (mask & hlt_cpus_mask) 1267 __asm __volatile("sti; hlt" : : : "memory"); 1268 return (retval); 1269} 1270