mp_machdep.c revision 146457
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/amd64/amd64/mp_machdep.c 146457 2005-05-20 16:25:08Z obrien $"); 29 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_mp_watchdog.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#ifdef GPROF 38#include <sys/gmon.h> 39#endif 40#include <sys/kernel.h> 41#include <sys/ktr.h> 42#include <sys/lock.h> 43#include <sys/malloc.h> 44#include <sys/memrange.h> 45#include <sys/mutex.h> 46#include <sys/pcpu.h> 47#include <sys/proc.h> 48#include <sys/smp.h> 49#include <sys/sysctl.h> 50 51#include <vm/vm.h> 52#include <vm/vm_param.h> 53#include <vm/pmap.h> 54#include <vm/vm_kern.h> 55#include <vm/vm_extern.h> 56 57#include <machine/apicreg.h> 58#include <machine/clock.h> 59#include <machine/md_var.h> 60#include <machine/mp_watchdog.h> 61#include <machine/pcb.h> 62#include <machine/psl.h> 63#include <machine/smp.h> 64#include <machine/specialreg.h> 65#include <machine/tss.h> 66 67#define WARMBOOT_TARGET 0 68#define WARMBOOT_OFF (KERNBASE + 0x0467) 69#define WARMBOOT_SEG (KERNBASE + 0x0469) 70 71#define CMOS_REG (0x70) 72#define CMOS_DATA (0x71) 73#define BIOS_RESET (0x0f) 74#define BIOS_WARM (0x0a) 75 76/* lock region used by kernel profiling */ 77int mcount_lock; 78 79int mp_naps; /* # of Applications processors */ 80int boot_cpu_id = -1; /* designated BSP */ 81extern int nkpt; 82 83/* 84 * CPU topology map datastructures for HTT. 85 */ 86static struct cpu_group mp_groups[MAXCPU]; 87static struct cpu_top mp_top; 88 89/* AP uses this during bootstrap. Do not staticize. */ 90char *bootSTK; 91static int bootAP; 92 93/* Free these after use */ 94void *bootstacks[MAXCPU]; 95 96/* Hotwire a 0->4MB V==P mapping */ 97extern pt_entry_t *KPTphys; 98 99/* SMP page table page */ 100extern pt_entry_t *SMPpt; 101 102struct pcb stoppcbs[MAXCPU]; 103 104/* Variables needed for SMP tlb shootdown. */ 105vm_offset_t smp_tlb_addr1; 106vm_offset_t smp_tlb_addr2; 107volatile int smp_tlb_wait; 108 109extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 110 111/* 112 * Local data and functions. 113 */ 114 115static u_int logical_cpus; 116 117/* used to hold the AP's until we are ready to release them */ 118static struct mtx ap_boot_mtx; 119 120/* Set to 1 once we're ready to let the APs out of the pen. */ 121static volatile int aps_ready = 0; 122 123/* 124 * Store data from cpu_add() until later in the boot when we actually setup 125 * the APs. 126 */ 127struct cpu_info { 128 int cpu_present:1; 129 int cpu_bsp:1; 130 int cpu_disabled:1; 131} static cpu_info[MAXCPU]; 132static int cpu_apic_ids[MAXCPU]; 133 134/* Holds pending bitmap based IPIs per CPU */ 135static volatile u_int cpu_ipi_pending[MAXCPU]; 136 137static u_int boot_address; 138 139static void set_logical_apic_ids(void); 140static int start_all_aps(void); 141static int start_ap(int apic_id); 142static void release_aps(void *dummy); 143 144static int hlt_logical_cpus; 145static u_int hyperthreading_cpus; 146static cpumask_t hyperthreading_cpus_mask; 147static int hyperthreading_allowed = 1; 148static struct sysctl_ctx_list logical_cpu_clist; 149static u_int bootMP_size; 150 151static void 152mem_range_AP_init(void) 153{ 154 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 155 mem_range_softc.mr_op->initAP(&mem_range_softc); 156} 157 158void 159mp_topology(void) 160{ 161 struct cpu_group *group; 162 int logical_cpus; 163 int apic_id; 164 int groups; 165 int cpu; 166 167 /* Build the smp_topology map. */ 168 /* Nothing to do if there is no HTT support. */ 169 if ((cpu_feature & CPUID_HTT) == 0) 170 return; 171 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 172 if (logical_cpus <= 1) 173 return; 174 group = &mp_groups[0]; 175 groups = 1; 176 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) { 177 if (!cpu_info[apic_id].cpu_present) 178 continue; 179 /* 180 * If the current group has members and we're not a logical 181 * cpu, create a new group. 182 */ 183 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) { 184 group++; 185 groups++; 186 } 187 group->cg_count++; 188 group->cg_mask |= 1 << cpu; 189 cpu++; 190 } 191 192 mp_top.ct_count = groups; 193 mp_top.ct_group = mp_groups; 194 smp_topology = &mp_top; 195} 196 197 198#ifdef KDB_STOP_NMI 199volatile cpumask_t ipi_nmi_pending; 200#endif 201 202/* 203 * Calculate usable address in base memory for AP trampoline code. 204 */ 205u_int 206mp_bootaddress(u_int basemem) 207{ 208 209 bootMP_size = mptramp_end - mptramp_start; 210 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 211 if (((basemem * 1024) - boot_address) < bootMP_size) 212 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 213 /* 3 levels of page table pages */ 214 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 215 216 return mptramp_pagetables; 217} 218 219void 220cpu_add(u_int apic_id, char boot_cpu) 221{ 222 223 if (apic_id >= MAXCPU) { 224 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n", 225 apic_id, MAXCPU - 1); 226 return; 227 } 228 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 229 apic_id)); 230 cpu_info[apic_id].cpu_present = 1; 231 if (boot_cpu) { 232 KASSERT(boot_cpu_id == -1, 233 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 234 boot_cpu_id)); 235 boot_cpu_id = apic_id; 236 cpu_info[apic_id].cpu_bsp = 1; 237 } 238 mp_ncpus++; 239 if (apic_id > mp_maxid) 240 mp_maxid = apic_id; 241 if (bootverbose) 242 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 243 "AP"); 244 245} 246 247void 248cpu_mp_setmaxid(void) 249{ 250 251 /* 252 * mp_maxid should be already set by calls to cpu_add(). 253 * Just sanity check its value here. 254 */ 255 if (mp_ncpus == 0) 256 KASSERT(mp_maxid == 0, 257 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 258 else if (mp_ncpus == 1) 259 mp_maxid = 0; 260 else 261 KASSERT(mp_maxid >= mp_ncpus - 1, 262 ("%s: counters out of sync: max %d, count %d", __func__, 263 mp_maxid, mp_ncpus)); 264 265} 266 267int 268cpu_mp_probe(void) 269{ 270 271 /* 272 * Always record BSP in CPU map so that the mbuf init code works 273 * correctly. 274 */ 275 all_cpus = 1; 276 if (mp_ncpus == 0) { 277 /* 278 * No CPUs were found, so this must be a UP system. Setup 279 * the variables to represent a system with a single CPU 280 * with an id of 0. 281 */ 282 mp_ncpus = 1; 283 return (0); 284 } 285 286 /* At least one CPU was found. */ 287 if (mp_ncpus == 1) { 288 /* 289 * One CPU was found, so this must be a UP system with 290 * an I/O APIC. 291 */ 292 mp_maxid = 0; 293 return (0); 294 } 295 296 /* At least two CPUs were found. */ 297 return (1); 298} 299 300/* 301 * Initialize the IPI handlers and start up the AP's. 302 */ 303void 304cpu_mp_start(void) 305{ 306 int i; 307 u_int threads_per_cache, p[4]; 308 309 /* Initialize the logical ID to APIC ID table. */ 310 for (i = 0; i < MAXCPU; i++) { 311 cpu_apic_ids[i] = -1; 312 cpu_ipi_pending[i] = 0; 313 } 314 315 /* Install an inter-CPU IPI for TLB invalidation */ 316 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 317 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 318 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 319 320 /* Install an inter-CPU IPI for all-CPU rendezvous */ 321 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 322 323 /* Install generic inter-CPU IPI handler */ 324 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 325 SDT_SYSIGT, SEL_KPL, 0); 326 327 /* Install an inter-CPU IPI for CPU stop/restart */ 328 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 329 330 /* Set boot_cpu_id if needed. */ 331 if (boot_cpu_id == -1) { 332 boot_cpu_id = PCPU_GET(apic_id); 333 cpu_info[boot_cpu_id].cpu_bsp = 1; 334 } else 335 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 336 ("BSP's APIC ID doesn't match boot_cpu_id")); 337 cpu_apic_ids[0] = boot_cpu_id; 338 339 /* Start each Application Processor */ 340 start_all_aps(); 341 342 /* Setup the initial logical CPUs info. */ 343 logical_cpus = logical_cpus_mask = 0; 344 if (cpu_feature & CPUID_HTT) 345 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 346 347 /* 348 * Work out if hyperthreading is *really* enabled. This 349 * is made really ugly by the fact that processors lie: Dual 350 * core processors claim to be hyperthreaded even when they're 351 * not, presumably because they want to be treated the same 352 * way as HTT with respect to per-cpu software licensing. 353 * At the time of writing (May 12, 2005) the only hyperthreaded 354 * cpus are from Intel, and Intel's dual-core processors can be 355 * identified via the "deterministic cache parameters" cpuid 356 * calls. 357 */ 358 /* 359 * First determine if this is an Intel processor which claims 360 * to have hyperthreading support. 361 */ 362 if ((cpu_feature & CPUID_HTT) && 363 (strcmp(cpu_vendor, "GenuineIntel") == 0)) { 364 /* 365 * If the "deterministic cache parameters" cpuid calls 366 * are available, use them. 367 */ 368 if (cpu_high >= 4) { 369 /* Ask the processor about up to 32 caches. */ 370 for (i = 0; i < 32; i++) { 371 cpuid_count(4, i, p); 372 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 373 if (hyperthreading_cpus < threads_per_cache) 374 hyperthreading_cpus = threads_per_cache; 375 if ((p[0] & 0x1f) == 0) 376 break; 377 } 378 } 379 380 /* 381 * If the deterministic cache parameters are not 382 * available, or if no caches were reported to exist, 383 * just accept what the HTT flag indicated. 384 */ 385 if (hyperthreading_cpus == 0) 386 hyperthreading_cpus = logical_cpus; 387 } 388 389 set_logical_apic_ids(); 390} 391 392 393/* 394 * Print various information about the SMP system hardware and setup. 395 */ 396void 397cpu_mp_announce(void) 398{ 399 int i, x; 400 401 /* List CPUs */ 402 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 403 for (i = 1, x = 0; x < MAXCPU; x++) { 404 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp) 405 continue; 406 if (cpu_info[x].cpu_disabled) 407 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x); 408 else { 409 KASSERT(i < mp_ncpus, 410 ("mp_ncpus and actual cpus are out of whack")); 411 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x); 412 } 413 } 414} 415 416/* 417 * AP CPU's call this to initialize themselves. 418 */ 419void 420init_secondary(void) 421{ 422 struct pcpu *pc; 423 u_int64_t msr, cr0; 424 int cpu, gsel_tss; 425 426 /* Set by the startup code for us to use */ 427 cpu = bootAP; 428 429 /* Init tss */ 430 common_tss[cpu] = common_tss[0]; 431 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 432 common_tss[cpu].tss_iobase = sizeof(struct amd64tss); 433 434 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 435 ssdtosyssd(&gdt_segs[GPROC0_SEL], 436 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 437 438 lgdt(&r_gdt); /* does magic intra-segment return */ 439 440 /* Get per-cpu data */ 441 pc = &__pcpu[cpu]; 442 443 /* prime data page for it to use */ 444 pcpu_init(pc, cpu, sizeof(struct pcpu)); 445 pc->pc_apic_id = cpu_apic_ids[cpu]; 446 pc->pc_prvspace = pc; 447 pc->pc_curthread = 0; 448 pc->pc_tssp = &common_tss[cpu]; 449 pc->pc_rsp0 = 0; 450 451 wrmsr(MSR_FSBASE, 0); /* User value */ 452 wrmsr(MSR_GSBASE, (u_int64_t)pc); 453 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 454 455 lidt(&r_idt); 456 457 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 458 ltr(gsel_tss); 459 460 /* 461 * Set to a known state: 462 * Set by mpboot.s: CR0_PG, CR0_PE 463 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 464 */ 465 cr0 = rcr0(); 466 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 467 load_cr0(cr0); 468 469 /* Set up the fast syscall stuff */ 470 msr = rdmsr(MSR_EFER) | EFER_SCE; 471 wrmsr(MSR_EFER, msr); 472 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 473 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 474 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 475 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 476 wrmsr(MSR_STAR, msr); 477 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 478 479 /* Disable local apic just to be sure. */ 480 lapic_disable(); 481 482 /* signal our startup to the BSP. */ 483 mp_naps++; 484 485 /* Spin until the BSP releases the AP's. */ 486 while (!aps_ready) 487 ia32_pause(); 488 489 /* set up CPU registers and state */ 490 cpu_setregs(); 491 492 /* set up SSE/NX registers */ 493 initializecpu(); 494 495 /* set up FPU state on the AP */ 496 fpuinit(); 497 498 /* A quick check from sanity claus */ 499 if (PCPU_GET(apic_id) != lapic_id()) { 500 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 501 printf("SMP: actual apic_id = %d\n", lapic_id()); 502 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 503 panic("cpuid mismatch! boom!!"); 504 } 505 506 /* Initialize curthread. */ 507 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 508 PCPU_SET(curthread, PCPU_GET(idlethread)); 509 510 mtx_lock_spin(&ap_boot_mtx); 511 512 /* Init local apic for irq's */ 513 lapic_setup(); 514 515 /* Set memory range attributes for this CPU to match the BSP */ 516 mem_range_AP_init(); 517 518 smp_cpus++; 519 520 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 521 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 522 523 /* Determine if we are a logical CPU. */ 524 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 525 logical_cpus_mask |= PCPU_GET(cpumask); 526 527 /* Determine if we are a hyperthread. */ 528 if (hyperthreading_cpus > 1 && 529 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 530 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 531 532 /* Build our map of 'other' CPUs. */ 533 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 534 535 if (bootverbose) 536 lapic_dump("AP"); 537 538 if (smp_cpus == mp_ncpus) { 539 /* enable IPI's, tlb shootdown, freezes etc */ 540 atomic_store_rel_int(&smp_started, 1); 541 smp_active = 1; /* historic */ 542 } 543 544 mtx_unlock_spin(&ap_boot_mtx); 545 546 /* wait until all the AP's are up */ 547 while (smp_started == 0) 548 ia32_pause(); 549 550 /* ok, now grab sched_lock and enter the scheduler */ 551 mtx_lock_spin(&sched_lock); 552 553 /* 554 * Correct spinlock nesting. The idle thread context that we are 555 * borrowing was created so that it would start out with a single 556 * spin lock (sched_lock) held in fork_trampoline(). Since we've 557 * explicitly acquired locks in this function, the nesting count 558 * is now 2 rather than 1. Since we are nested, calling 559 * spinlock_exit() will simply adjust the counts without allowing 560 * spin lock using code to interrupt us. 561 */ 562 spinlock_exit(); 563 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count")); 564 565 binuptime(PCPU_PTR(switchtime)); 566 PCPU_SET(switchticks, ticks); 567 568 cpu_throw(NULL, choosethread()); /* doesn't return */ 569 570 panic("scheduler returned us to %s", __func__); 571 /* NOTREACHED */ 572} 573 574/******************************************************************* 575 * local functions and data 576 */ 577 578/* 579 * Set the APIC logical IDs. 580 * 581 * We want to cluster logical CPU's within the same APIC ID cluster. 582 * Since logical CPU's are aligned simply filling in the clusters in 583 * APIC ID order works fine. Note that this does not try to balance 584 * the number of CPU's in each cluster. (XXX?) 585 */ 586static void 587set_logical_apic_ids(void) 588{ 589 u_int apic_id, cluster, cluster_id; 590 591 /* Force us to allocate cluster 0 at the start. */ 592 cluster = -1; 593 cluster_id = APIC_MAX_INTRACLUSTER_ID; 594 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 595 if (!cpu_info[apic_id].cpu_present) 596 continue; 597 if (cluster_id == APIC_MAX_INTRACLUSTER_ID) { 598 cluster = ioapic_next_logical_cluster(); 599 cluster_id = 0; 600 } else 601 cluster_id++; 602 if (bootverbose) 603 printf("APIC ID: physical %u, logical %u:%u\n", 604 apic_id, cluster, cluster_id); 605 lapic_set_logical_id(apic_id, cluster, cluster_id); 606 } 607} 608 609/* 610 * start each AP in our list 611 */ 612static int 613start_all_aps(void) 614{ 615 u_char mpbiosreason; 616 u_int32_t mpbioswarmvec; 617 int apic_id, cpu, i; 618 u_int64_t *pt4, *pt3, *pt2; 619 vm_offset_t va = boot_address + KERNBASE; 620 621 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 622 623 /* install the AP 1st level boot code */ 624 pmap_kenter(va, boot_address); 625 pmap_invalidate_page(kernel_pmap, va); 626 bcopy(mptramp_start, (void *)va, bootMP_size); 627 628 /* Locate the page tables, they'll be below the trampoline */ 629 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 630 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 631 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 632 633 /* Create the initial 1GB replicated page tables */ 634 for (i = 0; i < 512; i++) { 635 /* Each slot of the level 4 pages points to the same level 3 page */ 636 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 637 pt4[i] |= PG_V | PG_RW | PG_U; 638 639 /* Each slot of the level 3 pages points to the same level 2 page */ 640 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 641 pt3[i] |= PG_V | PG_RW | PG_U; 642 643 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 644 pt2[i] = i * (2 * 1024 * 1024); 645 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 646 } 647 648 /* save the current value of the warm-start vector */ 649 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 650 outb(CMOS_REG, BIOS_RESET); 651 mpbiosreason = inb(CMOS_DATA); 652 653 /* setup a vector to our boot code */ 654 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 655 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 656 outb(CMOS_REG, BIOS_RESET); 657 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 658 659 /* start each AP */ 660 cpu = 0; 661 for (apic_id = 0; apic_id < MAXCPU; apic_id++) { 662 663 /* Ignore non-existent CPUs and the BSP. */ 664 if (!cpu_info[apic_id].cpu_present || 665 cpu_info[apic_id].cpu_bsp) 666 continue; 667 668 /* Don't use this CPU if it has been disabled by a tunable. */ 669 if (resource_disabled("lapic", apic_id)) { 670 cpu_info[apic_id].cpu_disabled = 1; 671 mp_ncpus--; 672 continue; 673 } 674 675 cpu++; 676 677 /* save APIC ID for this logical ID */ 678 cpu_apic_ids[cpu] = apic_id; 679 680 /* allocate and set up an idle stack data page */ 681 bootstacks[cpu] = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 682 683 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 684 bootAP = cpu; 685 686 /* attempt to start the Application Processor */ 687 if (!start_ap(apic_id)) { 688 /* restore the warmstart vector */ 689 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 690 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 691 } 692 693 all_cpus |= (1 << cpu); /* record AP in CPU map */ 694 } 695 696 /* build our map of 'other' CPUs */ 697 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 698 699 /* restore the warmstart vector */ 700 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 701 702 outb(CMOS_REG, BIOS_RESET); 703 outb(CMOS_DATA, mpbiosreason); 704 705 /* number of APs actually started */ 706 return mp_naps; 707} 708 709 710/* 711 * This function starts the AP (application processor) identified 712 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 713 * to accomplish this. This is necessary because of the nuances 714 * of the different hardware we might encounter. It isn't pretty, 715 * but it seems to work. 716 */ 717static int 718start_ap(int apic_id) 719{ 720 int vector, ms; 721 int cpus; 722 723 /* calculate the vector */ 724 vector = (boot_address >> 12) & 0xff; 725 726 /* used as a watchpoint to signal AP startup */ 727 cpus = mp_naps; 728 729 /* 730 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 731 * and running the target CPU. OR this INIT IPI might be latched (P5 732 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 733 * ignored. 734 */ 735 736 /* do an INIT IPI: assert RESET */ 737 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 738 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 739 740 /* wait for pending status end */ 741 lapic_ipi_wait(-1); 742 743 /* do an INIT IPI: deassert RESET */ 744 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 745 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 746 747 /* wait for pending status end */ 748 DELAY(10000); /* wait ~10mS */ 749 lapic_ipi_wait(-1); 750 751 /* 752 * next we do a STARTUP IPI: the previous INIT IPI might still be 753 * latched, (P5 bug) this 1st STARTUP would then terminate 754 * immediately, and the previously started INIT IPI would continue. OR 755 * the previous INIT IPI has already run. and this STARTUP IPI will 756 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 757 * will run. 758 */ 759 760 /* do a STARTUP IPI */ 761 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 762 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 763 vector, apic_id); 764 lapic_ipi_wait(-1); 765 DELAY(200); /* wait ~200uS */ 766 767 /* 768 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 769 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 770 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 771 * recognized after hardware RESET or INIT IPI. 772 */ 773 774 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 775 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 776 vector, apic_id); 777 lapic_ipi_wait(-1); 778 DELAY(200); /* wait ~200uS */ 779 780 /* Wait up to 5 seconds for it to start. */ 781 for (ms = 0; ms < 5000; ms++) { 782 if (mp_naps > cpus) 783 return 1; /* return SUCCESS */ 784 DELAY(1000); 785 } 786 return 0; /* return FAILURE */ 787} 788 789/* 790 * Flush the TLB on all other CPU's 791 */ 792static void 793smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 794{ 795 u_int ncpu; 796 797 ncpu = mp_ncpus - 1; /* does not shootdown self */ 798 if (ncpu < 1) 799 return; /* no other cpus */ 800 mtx_assert(&smp_ipi_mtx, MA_OWNED); 801 smp_tlb_addr1 = addr1; 802 smp_tlb_addr2 = addr2; 803 atomic_store_rel_int(&smp_tlb_wait, 0); 804 ipi_all_but_self(vector); 805 while (smp_tlb_wait < ncpu) 806 ia32_pause(); 807} 808 809/* 810 * This is about as magic as it gets. fortune(1) has got similar code 811 * for reversing bits in a word. Who thinks up this stuff?? 812 * 813 * Yes, it does appear to be consistently faster than: 814 * while (i = ffs(m)) { 815 * m >>= i; 816 * bits++; 817 * } 818 * and 819 * while (lsb = (m & -m)) { // This is magic too 820 * m &= ~lsb; // or: m ^= lsb 821 * bits++; 822 * } 823 * Both of these latter forms do some very strange things on gcc-3.1 with 824 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 825 * There is probably an SSE or MMX popcnt instruction. 826 * 827 * I wonder if this should be in libkern? 828 * 829 * XXX Stop the presses! Another one: 830 * static __inline u_int32_t 831 * popcnt1(u_int32_t v) 832 * { 833 * v -= ((v >> 1) & 0x55555555); 834 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 835 * v = (v + (v >> 4)) & 0x0F0F0F0F; 836 * return (v * 0x01010101) >> 24; 837 * } 838 * The downside is that it has a multiply. With a pentium3 with 839 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 840 * an imull, and in that case it is faster. In most other cases 841 * it appears slightly slower. 842 * 843 * Another variant (also from fortune): 844 * #define BITCOUNT(x) (((BX_(x)+(BX_(x)>>4)) & 0x0F0F0F0F) % 255) 845 * #define BX_(x) ((x) - (((x)>>1)&0x77777777) \ 846 * - (((x)>>2)&0x33333333) \ 847 * - (((x)>>3)&0x11111111)) 848 */ 849static __inline u_int32_t 850popcnt(u_int32_t m) 851{ 852 853 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 854 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 855 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 856 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 857 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 858 return m; 859} 860 861static void 862smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 863{ 864 int ncpu, othercpus; 865 866 othercpus = mp_ncpus - 1; 867 if (mask == (u_int)-1) { 868 ncpu = othercpus; 869 if (ncpu < 1) 870 return; 871 } else { 872 mask &= ~PCPU_GET(cpumask); 873 if (mask == 0) 874 return; 875 ncpu = popcnt(mask); 876 if (ncpu > othercpus) { 877 /* XXX this should be a panic offence */ 878 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 879 ncpu, othercpus); 880 ncpu = othercpus; 881 } 882 /* XXX should be a panic, implied by mask == 0 above */ 883 if (ncpu < 1) 884 return; 885 } 886 mtx_assert(&smp_ipi_mtx, MA_OWNED); 887 smp_tlb_addr1 = addr1; 888 smp_tlb_addr2 = addr2; 889 atomic_store_rel_int(&smp_tlb_wait, 0); 890 if (mask == (u_int)-1) 891 ipi_all_but_self(vector); 892 else 893 ipi_selected(mask, vector); 894 while (smp_tlb_wait < ncpu) 895 ia32_pause(); 896} 897 898void 899smp_invltlb(void) 900{ 901 902 if (smp_started) 903 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 904} 905 906void 907smp_invlpg(vm_offset_t addr) 908{ 909 910 if (smp_started) 911 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 912} 913 914void 915smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 916{ 917 918 if (smp_started) 919 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 920} 921 922void 923smp_masked_invltlb(u_int mask) 924{ 925 926 if (smp_started) 927 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 928} 929 930void 931smp_masked_invlpg(u_int mask, vm_offset_t addr) 932{ 933 934 if (smp_started) 935 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 936} 937 938void 939smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 940{ 941 942 if (smp_started) 943 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 944} 945 946 947void 948ipi_bitmap_handler(struct clockframe frame) 949{ 950 int cpu = PCPU_GET(cpuid); 951 u_int ipi_bitmap; 952 953 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 954 955 /* Nothing to do for AST */ 956} 957 958/* 959 * send an IPI to a set of cpus. 960 */ 961void 962ipi_selected(u_int32_t cpus, u_int ipi) 963{ 964 int cpu; 965 u_int bitmap = 0; 966 u_int old_pending; 967 u_int new_pending; 968 969 if (IPI_IS_BITMAPED(ipi)) { 970 bitmap = 1 << ipi; 971 ipi = IPI_BITMAP_VECTOR; 972 } 973 974 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 975 while ((cpu = ffs(cpus)) != 0) { 976 cpu--; 977 cpus &= ~(1 << cpu); 978 979 KASSERT(cpu_apic_ids[cpu] != -1, 980 ("IPI to non-existent CPU %d", cpu)); 981 982 if (bitmap) { 983 do { 984 old_pending = cpu_ipi_pending[cpu]; 985 new_pending = old_pending | bitmap; 986 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 987 988 if (old_pending) 989 continue; 990 } 991 992 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 993 } 994 995} 996 997/* 998 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 999 */ 1000void 1001ipi_all(u_int ipi) 1002{ 1003 1004 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1005 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL); 1006} 1007 1008/* 1009 * send an IPI to all CPUs EXCEPT myself 1010 */ 1011void 1012ipi_all_but_self(u_int ipi) 1013{ 1014 1015 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1016 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1017} 1018 1019/* 1020 * send an IPI to myself 1021 */ 1022void 1023ipi_self(u_int ipi) 1024{ 1025 1026 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1027 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF); 1028} 1029 1030#ifdef KDB_STOP_NMI 1031/* 1032 * send NMI IPI to selected CPUs 1033 */ 1034 1035#define BEFORE_SPIN 1000000 1036 1037void 1038ipi_nmi_selected(u_int32_t cpus) 1039{ 1040 1041 int cpu; 1042 register_t icrlo; 1043 1044 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT 1045 | APIC_TRIGMOD_EDGE; 1046 1047 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus); 1048 1049 1050 atomic_set_int(&ipi_nmi_pending, cpus); 1051 1052 1053 while ((cpu = ffs(cpus)) != 0) { 1054 cpu--; 1055 cpus &= ~(1 << cpu); 1056 1057 KASSERT(cpu_apic_ids[cpu] != -1, 1058 ("IPI NMI to non-existent CPU %d", cpu)); 1059 1060 /* Wait for an earlier IPI to finish. */ 1061 if (!lapic_ipi_wait(BEFORE_SPIN)) 1062 panic("ipi_nmi_selected: previous IPI has not cleared"); 1063 1064 lapic_ipi_raw(icrlo,cpu_apic_ids[cpu]); 1065 } 1066} 1067 1068 1069int 1070ipi_nmi_handler() 1071{ 1072 int cpu = PCPU_GET(cpuid); 1073 1074 if(!(atomic_load_acq_int(&ipi_nmi_pending) & (1 << cpu))) 1075 return 1; 1076 1077 atomic_clear_int(&ipi_nmi_pending,1 << cpu); 1078 1079 savectx(&stoppcbs[cpu]); 1080 1081 /* Indicate that we are stopped */ 1082 atomic_set_int(&stopped_cpus,1 << cpu); 1083 1084 1085 /* Wait for restart */ 1086 while(!(atomic_load_acq_int(&started_cpus) & (1 << cpu))) 1087 ia32_pause(); 1088 1089 atomic_clear_int(&started_cpus,1 << cpu); 1090 atomic_clear_int(&stopped_cpus,1 << cpu); 1091 1092 if(cpu == 0 && cpustop_restartfunc != NULL) 1093 cpustop_restartfunc(); 1094 1095 return 0; 1096} 1097 1098#endif /* KDB_STOP_NMI */ 1099 1100/* 1101 * This is called once the rest of the system is up and running and we're 1102 * ready to let the AP's out of the pen. 1103 */ 1104static void 1105release_aps(void *dummy __unused) 1106{ 1107 1108 if (mp_ncpus == 1) 1109 return; 1110 mtx_lock_spin(&sched_lock); 1111 atomic_store_rel_int(&aps_ready, 1); 1112 while (smp_started == 0) 1113 ia32_pause(); 1114 mtx_unlock_spin(&sched_lock); 1115} 1116SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1117 1118static int 1119sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1120{ 1121 u_int mask; 1122 int error; 1123 1124 mask = hlt_cpus_mask; 1125 error = sysctl_handle_int(oidp, &mask, 0, req); 1126 if (error || !req->newptr) 1127 return (error); 1128 1129 if (logical_cpus_mask != 0 && 1130 (mask & logical_cpus_mask) == logical_cpus_mask) 1131 hlt_logical_cpus = 1; 1132 else 1133 hlt_logical_cpus = 0; 1134 1135 if (! hyperthreading_allowed) 1136 mask |= hyperthreading_cpus_mask; 1137 1138 if ((mask & all_cpus) == all_cpus) 1139 mask &= ~(1<<0); 1140 hlt_cpus_mask = mask; 1141 return (error); 1142} 1143SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1144 0, 0, sysctl_hlt_cpus, "IU", 1145 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1146 1147static int 1148sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1149{ 1150 int disable, error; 1151 1152 disable = hlt_logical_cpus; 1153 error = sysctl_handle_int(oidp, &disable, 0, req); 1154 if (error || !req->newptr) 1155 return (error); 1156 1157 if (disable) 1158 hlt_cpus_mask |= logical_cpus_mask; 1159 else 1160 hlt_cpus_mask &= ~logical_cpus_mask; 1161 1162 if (! hyperthreading_allowed) 1163 hlt_cpus_mask |= hyperthreading_cpus_mask; 1164 1165 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1166 hlt_cpus_mask &= ~(1<<0); 1167 1168 hlt_logical_cpus = disable; 1169 return (error); 1170} 1171 1172static int 1173sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1174{ 1175 int allowed, error; 1176 1177 allowed = hyperthreading_allowed; 1178 error = sysctl_handle_int(oidp, &allowed, 0, req); 1179 if (error || !req->newptr) 1180 return (error); 1181 1182 if (allowed) 1183 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1184 else 1185 hlt_cpus_mask |= hyperthreading_cpus_mask; 1186 1187 if (logical_cpus_mask != 0 && 1188 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1189 hlt_logical_cpus = 1; 1190 else 1191 hlt_logical_cpus = 0; 1192 1193 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1194 hlt_cpus_mask &= ~(1<<0); 1195 1196 hyperthreading_allowed = allowed; 1197 return (error); 1198} 1199 1200static void 1201cpu_hlt_setup(void *dummy __unused) 1202{ 1203 1204 if (logical_cpus_mask != 0) { 1205 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1206 &hlt_logical_cpus); 1207 sysctl_ctx_init(&logical_cpu_clist); 1208 SYSCTL_ADD_PROC(&logical_cpu_clist, 1209 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1210 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1211 sysctl_hlt_logical_cpus, "IU", ""); 1212 SYSCTL_ADD_UINT(&logical_cpu_clist, 1213 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1214 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1215 &logical_cpus_mask, 0, ""); 1216 1217 if (hlt_logical_cpus) 1218 hlt_cpus_mask |= logical_cpus_mask; 1219 1220 /* 1221 * If necessary for security purposes, force 1222 * hyperthreading off, regardless of the value 1223 * of hlt_logical_cpus. 1224 */ 1225 if (hyperthreading_cpus_mask) { 1226 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 1227 &hyperthreading_allowed); 1228 SYSCTL_ADD_PROC(&logical_cpu_clist, 1229 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1230 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1231 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1232 if (! hyperthreading_allowed) 1233 hlt_cpus_mask |= hyperthreading_cpus_mask; 1234 } 1235 } 1236} 1237SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1238 1239int 1240mp_grab_cpu_hlt(void) 1241{ 1242 u_int mask = PCPU_GET(cpumask); 1243#ifdef MP_WATCHDOG 1244 u_int cpuid = PCPU_GET(cpuid); 1245#endif 1246 int retval; 1247 1248#ifdef MP_WATCHDOG 1249 ap_watchdog(cpuid); 1250#endif 1251 1252 retval = mask & hlt_cpus_mask; 1253 while (mask & hlt_cpus_mask) 1254 __asm __volatile("sti; hlt" : : : "memory"); 1255 return (retval); 1256} 1257