mp_machdep.c revision 111878
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/amd64/amd64/mp_machdep.c 111878 2003-03-04 20:24:53Z jhb $ 26 */ 27 28#include "opt_cpu.h" 29#include "opt_htt.h" 30#include "opt_kstack_pages.h" 31 32#ifdef SMP 33#include <machine/smptests.h> 34#else 35#error 36#endif 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/cons.h> /* cngetc() */ 42#ifdef GPROF 43#include <sys/gmon.h> 44#endif 45#include <sys/kernel.h> 46#include <sys/ktr.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/memrange.h> 50#include <sys/mutex.h> 51#include <sys/pcpu.h> 52#include <sys/proc.h> 53#include <sys/smp.h> 54#include <sys/sysctl.h> 55#include <sys/user.h> 56 57#include <vm/vm.h> 58#include <vm/vm_param.h> 59#include <vm/pmap.h> 60#include <vm/vm_kern.h> 61#include <vm/vm_extern.h> 62#include <vm/vm_map.h> 63 64#include <machine/apic.h> 65#include <machine/atomic.h> 66#include <machine/clock.h> 67#include <machine/cpu.h> 68#include <machine/cpufunc.h> 69#include <machine/mpapic.h> 70#include <machine/psl.h> 71#include <machine/segments.h> 72#include <machine/smp.h> 73#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 74#include <machine/tss.h> 75#include <machine/specialreg.h> 76#include <machine/privatespace.h> 77 78#if defined(APIC_IO) 79#include <machine/md_var.h> /* setidt() */ 80#include <i386/isa/icu.h> /* IPIs */ 81#include <i386/isa/intr_machdep.h> /* IPIs */ 82#endif /* APIC_IO */ 83 84#if defined(TEST_DEFAULT_CONFIG) 85#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 86#else 87#define MPFPS_MPFB1 mpfps->mpfb1 88#endif /* TEST_DEFAULT_CONFIG */ 89 90#define WARMBOOT_TARGET 0 91#define WARMBOOT_OFF (KERNBASE + 0x0467) 92#define WARMBOOT_SEG (KERNBASE + 0x0469) 93 94#ifdef PC98 95#define BIOS_BASE (0xe8000) 96#define BIOS_SIZE (0x18000) 97#else 98#define BIOS_BASE (0xf0000) 99#define BIOS_SIZE (0x10000) 100#endif 101#define BIOS_COUNT (BIOS_SIZE/4) 102 103#define CMOS_REG (0x70) 104#define CMOS_DATA (0x71) 105#define BIOS_RESET (0x0f) 106#define BIOS_WARM (0x0a) 107 108#define PROCENTRY_FLAG_EN 0x01 109#define PROCENTRY_FLAG_BP 0x02 110#define IOAPICENTRY_FLAG_EN 0x01 111 112 113/* MP Floating Pointer Structure */ 114typedef struct MPFPS { 115 char signature[4]; 116 void *pap; 117 u_char length; 118 u_char spec_rev; 119 u_char checksum; 120 u_char mpfb1; 121 u_char mpfb2; 122 u_char mpfb3; 123 u_char mpfb4; 124 u_char mpfb5; 125} *mpfps_t; 126 127/* MP Configuration Table Header */ 128typedef struct MPCTH { 129 char signature[4]; 130 u_short base_table_length; 131 u_char spec_rev; 132 u_char checksum; 133 u_char oem_id[8]; 134 u_char product_id[12]; 135 void *oem_table_pointer; 136 u_short oem_table_size; 137 u_short entry_count; 138 void *apic_address; 139 u_short extended_table_length; 140 u_char extended_table_checksum; 141 u_char reserved; 142} *mpcth_t; 143 144 145typedef struct PROCENTRY { 146 u_char type; 147 u_char apic_id; 148 u_char apic_version; 149 u_char cpu_flags; 150 u_long cpu_signature; 151 u_long feature_flags; 152 u_long reserved1; 153 u_long reserved2; 154} *proc_entry_ptr; 155 156typedef struct BUSENTRY { 157 u_char type; 158 u_char bus_id; 159 char bus_type[6]; 160} *bus_entry_ptr; 161 162typedef struct IOAPICENTRY { 163 u_char type; 164 u_char apic_id; 165 u_char apic_version; 166 u_char apic_flags; 167 void *apic_address; 168} *io_apic_entry_ptr; 169 170typedef struct INTENTRY { 171 u_char type; 172 u_char int_type; 173 u_short int_flags; 174 u_char src_bus_id; 175 u_char src_bus_irq; 176 u_char dst_apic_id; 177 u_char dst_apic_int; 178} *int_entry_ptr; 179 180/* descriptions of MP basetable entries */ 181typedef struct BASETABLE_ENTRY { 182 u_char type; 183 u_char length; 184 char name[16]; 185} basetable_entry; 186 187/* 188 * this code MUST be enabled here and in mpboot.s. 189 * it follows the very early stages of AP boot by placing values in CMOS ram. 190 * it NORMALLY will never be needed and thus the primitive method for enabling. 191 * 192#define CHECK_POINTS 193 */ 194 195#if defined(CHECK_POINTS) && !defined(PC98) 196#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 197#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 198 199#define CHECK_INIT(D); \ 200 CHECK_WRITE(0x34, (D)); \ 201 CHECK_WRITE(0x35, (D)); \ 202 CHECK_WRITE(0x36, (D)); \ 203 CHECK_WRITE(0x37, (D)); \ 204 CHECK_WRITE(0x38, (D)); \ 205 CHECK_WRITE(0x39, (D)); 206 207#define CHECK_PRINT(S); \ 208 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 209 (S), \ 210 CHECK_READ(0x34), \ 211 CHECK_READ(0x35), \ 212 CHECK_READ(0x36), \ 213 CHECK_READ(0x37), \ 214 CHECK_READ(0x38), \ 215 CHECK_READ(0x39)); 216 217#else /* CHECK_POINTS */ 218 219#define CHECK_INIT(D) 220#define CHECK_PRINT(S) 221 222#endif /* CHECK_POINTS */ 223 224/* 225 * Values to send to the POST hardware. 226 */ 227#define MP_BOOTADDRESS_POST 0x10 228#define MP_PROBE_POST 0x11 229#define MPTABLE_PASS1_POST 0x12 230 231#define MP_START_POST 0x13 232#define MP_ENABLE_POST 0x14 233#define MPTABLE_PASS2_POST 0x15 234 235#define START_ALL_APS_POST 0x16 236#define INSTALL_AP_TRAMP_POST 0x17 237#define START_AP_POST 0x18 238 239#define MP_ANNOUNCE_POST 0x19 240 241#ifdef HTT 242static int need_hyperthreading_fixup; 243static u_int logical_cpus; 244#endif 245 246/* used to hold the AP's until we are ready to release them */ 247static struct mtx ap_boot_mtx; 248 249/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 250int current_postcode; 251 252/** XXX FIXME: what system files declare these??? */ 253extern struct region_descriptor r_gdt, r_idt; 254 255int bsp_apic_ready = 0; /* flags useability of BSP apic */ 256int mp_naps; /* # of Applications processors */ 257int mp_nbusses; /* # of busses */ 258int mp_napics; /* # of IO APICs */ 259int boot_cpu_id; /* designated BSP */ 260vm_offset_t cpu_apic_address; 261vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 262extern int nkpt; 263 264u_int32_t cpu_apic_versions[MAXCPU]; 265u_int32_t *io_apic_versions; 266 267#ifdef APIC_INTR_REORDER 268struct { 269 volatile int *location; 270 int bit; 271} apic_isrbit_location[32]; 272#endif 273 274struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 275 276/* 277 * APIC ID logical/physical mapping structures. 278 * We oversize these to simplify boot-time config. 279 */ 280int cpu_num_to_apic_id[NAPICID]; 281int io_num_to_apic_id[NAPICID]; 282int apic_id_to_logical[NAPICID]; 283 284 285/* AP uses this during bootstrap. Do not staticize. */ 286char *bootSTK; 287static int bootAP; 288 289/* Hotwire a 0->4MB V==P mapping */ 290extern pt_entry_t *KPTphys; 291 292/* SMP page table page */ 293extern pt_entry_t *SMPpt; 294 295struct pcb stoppcbs[MAXCPU]; 296 297#ifdef APIC_IO 298/* Variables needed for SMP tlb shootdown. */ 299vm_offset_t smp_tlb_addr1; 300vm_offset_t smp_tlb_addr2; 301volatile int smp_tlb_wait; 302static struct mtx smp_tlb_mtx; 303#endif 304 305/* 306 * Local data and functions. 307 */ 308 309/* Set to 1 once we're ready to let the APs out of the pen. */ 310static volatile int aps_ready = 0; 311 312static int mp_capable; 313static u_int boot_address; 314static u_int base_memory; 315 316static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 317static mpfps_t mpfps; 318static int search_for_sig(u_int32_t target, int count); 319static void mp_enable(u_int boot_addr); 320 321#ifdef HTT 322static void mptable_hyperthread_fixup(u_int id_mask); 323#endif 324static void mptable_pass1(void); 325static int mptable_pass2(void); 326static void default_mp_table(int type); 327static void fix_mp_table(void); 328static void setup_apic_irq_mapping(void); 329static void init_locks(void); 330static int start_all_aps(u_int boot_addr); 331static void install_ap_tramp(u_int boot_addr); 332static int start_ap(int logicalCpu, u_int boot_addr); 333void ap_init(void); 334static int apic_int_is_bus_type(int intr, int bus_type); 335static void release_aps(void *dummy); 336 337/* 338 * initialize all the SMP locks 339 */ 340 341/* lock region used by kernel profiling */ 342int mcount_lock; 343 344#ifdef USE_COMLOCK 345/* locks com (tty) data/hardware accesses: a FASTINTR() */ 346struct mtx com_mtx; 347#endif /* USE_COMLOCK */ 348 349static void 350init_locks(void) 351{ 352 353#ifdef USE_COMLOCK 354 mtx_init(&com_mtx, "com", NULL, MTX_SPIN); 355#endif /* USE_COMLOCK */ 356#ifdef APIC_IO 357 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 358#endif 359} 360 361/* 362 * Calculate usable address in base memory for AP trampoline code. 363 */ 364u_int 365mp_bootaddress(u_int basemem) 366{ 367 POSTCODE(MP_BOOTADDRESS_POST); 368 369 base_memory = basemem * 1024; /* convert to bytes */ 370 371 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 372 if ((base_memory - boot_address) < bootMP_size) 373 boot_address -= 4096; /* not enough, lower by 4k */ 374 375 return boot_address; 376} 377 378 379/* 380 * Look for an Intel MP spec table (ie, SMP capable hardware). 381 */ 382void 383i386_mp_probe(void) 384{ 385 int x; 386 u_long segment; 387 u_int32_t target; 388 389 POSTCODE(MP_PROBE_POST); 390 391 /* see if EBDA exists */ 392 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 393 /* search first 1K of EBDA */ 394 target = (u_int32_t) (segment << 4); 395 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 396 goto found; 397 } else { 398 /* last 1K of base memory, effective 'top of base' passed in */ 399 target = (u_int32_t) (base_memory - 0x400); 400 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 401 goto found; 402 } 403 404 /* search the BIOS */ 405 target = (u_int32_t) BIOS_BASE; 406 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 407 goto found; 408 409 /* nothing found */ 410 mpfps = (mpfps_t)0; 411 mp_capable = 0; 412 return; 413 414found: 415 /* calculate needed resources */ 416 mpfps = (mpfps_t)x; 417 mptable_pass1(); 418 419 /* flag fact that we are running multiple processors */ 420 mp_capable = 1; 421} 422 423int 424cpu_mp_probe(void) 425{ 426 /* 427 * Record BSP in CPU map 428 * This is done here so that MBUF init code works correctly. 429 */ 430 all_cpus = 1; 431 432 return (mp_capable); 433} 434 435/* 436 * Initialize the SMP hardware and the APIC and start up the AP's. 437 */ 438void 439cpu_mp_start(void) 440{ 441 POSTCODE(MP_START_POST); 442 443 /* look for MP capable motherboard */ 444 if (mp_capable) 445 mp_enable(boot_address); 446 else 447 panic("MP hardware not found!"); 448 449 cpu_setregs(); 450} 451 452 453/* 454 * Print various information about the SMP system hardware and setup. 455 */ 456void 457cpu_mp_announce(void) 458{ 459 int x; 460 461 POSTCODE(MP_ANNOUNCE_POST); 462 463 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 464 printf(", version: 0x%08x", cpu_apic_versions[0]); 465 printf(", at 0x%08x\n", cpu_apic_address); 466 for (x = 1; x <= mp_naps; ++x) { 467 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 468 printf(", version: 0x%08x", cpu_apic_versions[x]); 469 printf(", at 0x%08x\n", cpu_apic_address); 470 } 471 472#if defined(APIC_IO) 473 for (x = 0; x < mp_napics; ++x) { 474 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 475 printf(", version: 0x%08x", io_apic_versions[x]); 476 printf(", at 0x%08x\n", io_apic_address[x]); 477 } 478#else 479 printf(" Warning: APIC I/O disabled\n"); 480#endif /* APIC_IO */ 481} 482 483/* 484 * AP cpu's call this to sync up protected mode. 485 */ 486void 487init_secondary(void) 488{ 489 int gsel_tss; 490 int x, myid = bootAP; 491 u_int cr0; 492 493 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 494 gdt_segs[GPROC0_SEL].ssd_base = 495 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 496 SMP_prvspace[myid].pcpu.pc_prvspace = 497 &SMP_prvspace[myid].pcpu; 498 499 for (x = 0; x < NGDT; x++) { 500 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 501 } 502 503 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 504 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 505 lgdt(&r_gdt); /* does magic intra-segment return */ 506 507 lidt(&r_idt); 508 509 lldt(_default_ldt); 510 PCPU_SET(currentldt, _default_ldt); 511 512 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 513 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 514 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 515 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 516 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 517 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 518 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 519 ltr(gsel_tss); 520 521 /* 522 * Set to a known state: 523 * Set by mpboot.s: CR0_PG, CR0_PE 524 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 525 */ 526 cr0 = rcr0(); 527 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 528 load_cr0(cr0); 529 530 pmap_set_opt(); 531} 532 533 534#if defined(APIC_IO) 535/* 536 * Final configuration of the BSP's local APIC: 537 * - disable 'pic mode'. 538 * - disable 'virtual wire mode'. 539 * - enable NMI. 540 */ 541void 542bsp_apic_configure(void) 543{ 544 u_char byte; 545 u_int32_t temp; 546 547 /* leave 'pic mode' if necessary */ 548 if (picmode) { 549 outb(0x22, 0x70); /* select IMCR */ 550 byte = inb(0x23); /* current contents */ 551 byte |= 0x01; /* mask external INTR */ 552 outb(0x23, byte); /* disconnect 8259s/NMI */ 553 } 554 555 /* mask lint0 (the 8259 'virtual wire' connection) */ 556 temp = lapic.lvt_lint0; 557 temp |= APIC_LVT_M; /* set the mask */ 558 lapic.lvt_lint0 = temp; 559 560 /* setup lint1 to handle NMI */ 561 temp = lapic.lvt_lint1; 562 temp &= ~APIC_LVT_M; /* clear the mask */ 563 lapic.lvt_lint1 = temp; 564 565 if (bootverbose) 566 apic_dump("bsp_apic_configure()"); 567} 568#endif /* APIC_IO */ 569 570 571/******************************************************************* 572 * local functions and data 573 */ 574 575/* 576 * start the SMP system 577 */ 578static void 579mp_enable(u_int boot_addr) 580{ 581 int x; 582#if defined(APIC_IO) 583 int apic; 584 u_int ux; 585#endif /* APIC_IO */ 586 587 POSTCODE(MP_ENABLE_POST); 588 589 /* turn on 4MB of V == P addressing so we can get to MP table */ 590 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 591 invltlb(); 592 593 /* examine the MP table for needed info, uses physical addresses */ 594 x = mptable_pass2(); 595 596 *(int *)PTD = 0; 597 invltlb(); 598 599 /* can't process default configs till the CPU APIC is pmapped */ 600 if (x) 601 default_mp_table(x); 602 603 /* post scan cleanup */ 604 fix_mp_table(); 605 setup_apic_irq_mapping(); 606 607#if defined(APIC_IO) 608 609 /* fill the LOGICAL io_apic_versions table */ 610 for (apic = 0; apic < mp_napics; ++apic) { 611 ux = io_apic_read(apic, IOAPIC_VER); 612 io_apic_versions[apic] = ux; 613 io_apic_set_id(apic, IO_TO_ID(apic)); 614 } 615 616 /* program each IO APIC in the system */ 617 for (apic = 0; apic < mp_napics; ++apic) 618 if (io_apic_setup(apic) < 0) 619 panic("IO APIC setup failure"); 620 621 /* install a 'Spurious INTerrupt' vector */ 622 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 623 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 624 625 /* install an inter-CPU IPI for TLB invalidation */ 626 setidt(XINVLTLB_OFFSET, Xinvltlb, 627 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 628 setidt(XINVLPG_OFFSET, Xinvlpg, 629 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 630 setidt(XINVLRNG_OFFSET, Xinvlrng, 631 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 632 633 /* install an inter-CPU IPI for forwarding hardclock() */ 634 setidt(XHARDCLOCK_OFFSET, Xhardclock, 635 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 636 637 /* install an inter-CPU IPI for forwarding statclock() */ 638 setidt(XSTATCLOCK_OFFSET, Xstatclock, 639 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 640 641 /* install an inter-CPU IPI for all-CPU rendezvous */ 642 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 643 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 644 645 /* install an inter-CPU IPI for forcing an additional software trap */ 646 setidt(XCPUAST_OFFSET, Xcpuast, 647 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 648 649 /* install an inter-CPU IPI for CPU stop/restart */ 650 setidt(XCPUSTOP_OFFSET, Xcpustop, 651 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 652 653#if defined(TEST_TEST1) 654 /* install a "fake hardware INTerrupt" vector */ 655 setidt(XTEST1_OFFSET, Xtest1, 656 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 657#endif /** TEST_TEST1 */ 658 659#endif /* APIC_IO */ 660 661 /* initialize all SMP locks */ 662 init_locks(); 663 664 /* start each Application Processor */ 665 start_all_aps(boot_addr); 666} 667 668 669/* 670 * look for the MP spec signature 671 */ 672 673/* string defined by the Intel MP Spec as identifying the MP table */ 674#define MP_SIG 0x5f504d5f /* _MP_ */ 675#define NEXT(X) ((X) += 4) 676static int 677search_for_sig(u_int32_t target, int count) 678{ 679 int x; 680 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 681 682 for (x = 0; x < count; NEXT(x)) 683 if (addr[x] == MP_SIG) 684 /* make array index a byte index */ 685 return (target + (x * sizeof(u_int32_t))); 686 687 return -1; 688} 689 690 691static basetable_entry basetable_entry_types[] = 692{ 693 {0, 20, "Processor"}, 694 {1, 8, "Bus"}, 695 {2, 8, "I/O APIC"}, 696 {3, 8, "I/O INT"}, 697 {4, 8, "Local INT"} 698}; 699 700typedef struct BUSDATA { 701 u_char bus_id; 702 enum busTypes bus_type; 703} bus_datum; 704 705typedef struct INTDATA { 706 u_char int_type; 707 u_short int_flags; 708 u_char src_bus_id; 709 u_char src_bus_irq; 710 u_char dst_apic_id; 711 u_char dst_apic_int; 712 u_char int_vector; 713} io_int, local_int; 714 715typedef struct BUSTYPENAME { 716 u_char type; 717 char name[7]; 718} bus_type_name; 719 720static bus_type_name bus_type_table[] = 721{ 722 {CBUS, "CBUS"}, 723 {CBUSII, "CBUSII"}, 724 {EISA, "EISA"}, 725 {MCA, "MCA"}, 726 {UNKNOWN_BUSTYPE, "---"}, 727 {ISA, "ISA"}, 728 {MCA, "MCA"}, 729 {UNKNOWN_BUSTYPE, "---"}, 730 {UNKNOWN_BUSTYPE, "---"}, 731 {UNKNOWN_BUSTYPE, "---"}, 732 {UNKNOWN_BUSTYPE, "---"}, 733 {UNKNOWN_BUSTYPE, "---"}, 734 {PCI, "PCI"}, 735 {UNKNOWN_BUSTYPE, "---"}, 736 {UNKNOWN_BUSTYPE, "---"}, 737 {UNKNOWN_BUSTYPE, "---"}, 738 {UNKNOWN_BUSTYPE, "---"}, 739 {XPRESS, "XPRESS"}, 740 {UNKNOWN_BUSTYPE, "---"} 741}; 742/* from MP spec v1.4, table 5-1 */ 743static int default_data[7][5] = 744{ 745/* nbus, id0, type0, id1, type1 */ 746 {1, 0, ISA, 255, 255}, 747 {1, 0, EISA, 255, 255}, 748 {1, 0, EISA, 255, 255}, 749 {1, 0, MCA, 255, 255}, 750 {2, 0, ISA, 1, PCI}, 751 {2, 0, EISA, 1, PCI}, 752 {2, 0, MCA, 1, PCI} 753}; 754 755 756/* the bus data */ 757static bus_datum *bus_data; 758 759/* the IO INT data, one entry per possible APIC INTerrupt */ 760static io_int *io_apic_ints; 761 762static int nintrs; 763 764static int processor_entry(proc_entry_ptr entry, int cpu); 765static int bus_entry(bus_entry_ptr entry, int bus); 766static int io_apic_entry(io_apic_entry_ptr entry, int apic); 767static int int_entry(int_entry_ptr entry, int intr); 768static int lookup_bus_type(char *name); 769 770 771/* 772 * 1st pass on motherboard's Intel MP specification table. 773 * 774 * initializes: 775 * mp_ncpus = 1 776 * 777 * determines: 778 * cpu_apic_address (common to all CPUs) 779 * io_apic_address[N] 780 * mp_naps 781 * mp_nbusses 782 * mp_napics 783 * nintrs 784 */ 785static void 786mptable_pass1(void) 787{ 788 int x; 789 mpcth_t cth; 790 int totalSize; 791 void* position; 792 int count; 793 int type; 794#ifdef HTT 795 u_int id_mask; 796#endif 797 798 POSTCODE(MPTABLE_PASS1_POST); 799 800 /* clear various tables */ 801 for (x = 0; x < NAPICID; ++x) { 802 io_apic_address[x] = ~0; /* IO APIC address table */ 803 } 804 805 /* init everything to empty */ 806 mp_naps = 0; 807 mp_nbusses = 0; 808 mp_napics = 0; 809 nintrs = 0; 810#ifdef HTT 811 id_mask = 0; 812#endif 813 814 /* check for use of 'default' configuration */ 815 if (MPFPS_MPFB1 != 0) { 816 /* use default addresses */ 817 cpu_apic_address = DEFAULT_APIC_BASE; 818 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 819 820 /* fill in with defaults */ 821 mp_naps = 2; /* includes BSP */ 822 mp_maxid = 1; 823 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 824#if defined(APIC_IO) 825 mp_napics = 1; 826 nintrs = 16; 827#endif /* APIC_IO */ 828 } 829 else { 830 if ((cth = mpfps->pap) == 0) 831 panic("MP Configuration Table Header MISSING!"); 832 833 cpu_apic_address = (vm_offset_t) cth->apic_address; 834 835 /* walk the table, recording info of interest */ 836 totalSize = cth->base_table_length - sizeof(struct MPCTH); 837 position = (u_char *) cth + sizeof(struct MPCTH); 838 count = cth->entry_count; 839 840 while (count--) { 841 switch (type = *(u_char *) position) { 842 case 0: /* processor_entry */ 843 if (((proc_entry_ptr)position)->cpu_flags 844 & PROCENTRY_FLAG_EN) { 845 ++mp_naps; 846 mp_maxid++; 847#ifdef HTT 848 id_mask |= 1 << 849 ((proc_entry_ptr)position)->apic_id; 850#endif 851 } 852 break; 853 case 1: /* bus_entry */ 854 ++mp_nbusses; 855 break; 856 case 2: /* io_apic_entry */ 857 if (((io_apic_entry_ptr)position)->apic_flags 858 & IOAPICENTRY_FLAG_EN) 859 io_apic_address[mp_napics++] = 860 (vm_offset_t)((io_apic_entry_ptr) 861 position)->apic_address; 862 break; 863 case 3: /* int_entry */ 864 ++nintrs; 865 break; 866 case 4: /* int_entry */ 867 break; 868 default: 869 panic("mpfps Base Table HOSED!"); 870 /* NOTREACHED */ 871 } 872 873 totalSize -= basetable_entry_types[type].length; 874 (u_char*)position += basetable_entry_types[type].length; 875 } 876 } 877 878 /* qualify the numbers */ 879 if (mp_naps > MAXCPU) { 880 printf("Warning: only using %d of %d available CPUs!\n", 881 MAXCPU, mp_naps); 882 mp_naps = MAXCPU; 883 } 884 885#ifdef HTT 886 /* See if we need to fixup HT logical CPUs. */ 887 mptable_hyperthread_fixup(id_mask); 888#endif 889 890 /* 891 * Count the BSP. 892 * This is also used as a counter while starting the APs. 893 */ 894 mp_ncpus = 1; 895 896 --mp_naps; /* subtract the BSP */ 897} 898 899 900/* 901 * 2nd pass on motherboard's Intel MP specification table. 902 * 903 * sets: 904 * boot_cpu_id 905 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 906 * CPU_TO_ID(N), logical CPU to APIC ID table 907 * IO_TO_ID(N), logical IO to APIC ID table 908 * bus_data[N] 909 * io_apic_ints[N] 910 */ 911static int 912mptable_pass2(void) 913{ 914#ifdef HTT 915 struct PROCENTRY proc; 916#endif 917 int x; 918 mpcth_t cth; 919 int totalSize; 920 void* position; 921 int count; 922 int type; 923 int apic, bus, cpu, intr; 924 int i, j; 925 int pgeflag; 926 927 POSTCODE(MPTABLE_PASS2_POST); 928 929#ifdef HTT 930 /* Initialize fake proc entry for use with HT fixup. */ 931 bzero(&proc, sizeof(proc)); 932 proc.type = 0; 933 proc.cpu_flags = PROCENTRY_FLAG_EN; 934#endif 935 936 pgeflag = 0; /* XXX - Not used under SMP yet. */ 937 938 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics, 939 M_DEVBUF, M_WAITOK); 940 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics, 941 M_DEVBUF, M_WAITOK); 942 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1), 943 M_DEVBUF, M_WAITOK); 944 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses, 945 M_DEVBUF, M_WAITOK); 946 947 bzero(ioapic, sizeof(ioapic_t *) * mp_napics); 948 949 for (i = 0; i < mp_napics; i++) { 950 for (j = 0; j < mp_napics; j++) { 951 /* same page frame as a previous IO apic? */ 952 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 953 (io_apic_address[i] & PG_FRAME)) { 954 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 955 + (NPTEPG-2-j) * PAGE_SIZE 956 + (io_apic_address[i] & PAGE_MASK)); 957 break; 958 } 959 /* use this slot if available */ 960 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) { 961 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW | 962 pgeflag | (io_apic_address[i] & PG_FRAME)); 963 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 964 + (NPTEPG-2-j) * PAGE_SIZE 965 + (io_apic_address[i] & PAGE_MASK)); 966 break; 967 } 968 } 969 } 970 971 /* clear various tables */ 972 for (x = 0; x < NAPICID; ++x) { 973 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 974 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 975 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 976 } 977 978 /* clear bus data table */ 979 for (x = 0; x < mp_nbusses; ++x) 980 bus_data[x].bus_id = 0xff; 981 982 /* clear IO APIC INT table */ 983 for (x = 0; x < (nintrs + 1); ++x) { 984 io_apic_ints[x].int_type = 0xff; 985 io_apic_ints[x].int_vector = 0xff; 986 } 987 988 /* setup the cpu/apic mapping arrays */ 989 boot_cpu_id = -1; 990 991 /* record whether PIC or virtual-wire mode */ 992 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 993 994 /* check for use of 'default' configuration */ 995 if (MPFPS_MPFB1 != 0) 996 return MPFPS_MPFB1; /* return default configuration type */ 997 998 if ((cth = mpfps->pap) == 0) 999 panic("MP Configuration Table Header MISSING!"); 1000 1001 /* walk the table, recording info of interest */ 1002 totalSize = cth->base_table_length - sizeof(struct MPCTH); 1003 position = (u_char *) cth + sizeof(struct MPCTH); 1004 count = cth->entry_count; 1005 apic = bus = intr = 0; 1006 cpu = 1; /* pre-count the BSP */ 1007 1008 while (count--) { 1009 switch (type = *(u_char *) position) { 1010 case 0: 1011 if (processor_entry(position, cpu)) 1012 ++cpu; 1013 1014#ifdef HTT 1015 if (need_hyperthreading_fixup) { 1016 /* 1017 * Create fake mptable processor entries 1018 * and feed them to processor_entry() to 1019 * enumerate the logical CPUs. 1020 */ 1021 proc.apic_id = ((proc_entry_ptr)position)->apic_id; 1022 for (i = 1; i < logical_cpus; i++) { 1023 proc.apic_id++; 1024 (void)processor_entry(&proc, cpu); 1025 cpu++; 1026 } 1027 } 1028#endif 1029 break; 1030 case 1: 1031 if (bus_entry(position, bus)) 1032 ++bus; 1033 break; 1034 case 2: 1035 if (io_apic_entry(position, apic)) 1036 ++apic; 1037 break; 1038 case 3: 1039 if (int_entry(position, intr)) 1040 ++intr; 1041 break; 1042 case 4: 1043 /* int_entry(position); */ 1044 break; 1045 default: 1046 panic("mpfps Base Table HOSED!"); 1047 /* NOTREACHED */ 1048 } 1049 1050 totalSize -= basetable_entry_types[type].length; 1051 (u_char *) position += basetable_entry_types[type].length; 1052 } 1053 1054 if (boot_cpu_id == -1) 1055 panic("NO BSP found!"); 1056 1057 /* report fact that its NOT a default configuration */ 1058 return 0; 1059} 1060 1061#ifdef HTT 1062/* 1063 * Check if we should perform a hyperthreading "fix-up" to 1064 * enumerate any logical CPU's that aren't already listed 1065 * in the table. 1066 * 1067 * XXX: We assume that all of the physical CPUs in the 1068 * system have the same number of logical CPUs. 1069 * 1070 * XXX: We assume that APIC ID's are allocated such that 1071 * the APIC ID's for a physical processor are aligned 1072 * with the number of logical CPU's in the processor. 1073 */ 1074static void 1075mptable_hyperthread_fixup(u_int id_mask) 1076{ 1077 u_int i, id; 1078 1079 /* Nothing to do if there is no HTT support. */ 1080 if ((cpu_feature & CPUID_HTT) == 0) 1081 return; 1082 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 1083 if (logical_cpus <= 1) 1084 return; 1085 1086 /* 1087 * For each APIC ID of a CPU that is set in the mask, 1088 * scan the other candidate APIC ID's for this 1089 * physical processor. If any of those ID's are 1090 * already in the table, then kill the fixup. 1091 */ 1092 for (id = 0; id <= MAXCPU; id++) { 1093 if ((id_mask & 1 << id) == 0) 1094 continue; 1095 /* First, make sure we are on a logical_cpus boundary. */ 1096 if (id % logical_cpus != 0) 1097 return; 1098 for (i = id + 1; i < id + logical_cpus; i++) 1099 if ((id_mask & 1 << i) != 0) 1100 return; 1101 } 1102 1103 /* 1104 * Ok, the ID's checked out, so enable the fixup. We have to fixup 1105 * mp_naps and mp_maxid right now. 1106 */ 1107 need_hyperthreading_fixup = 1; 1108 mp_maxid *= logical_cpus; 1109 mp_naps *= logical_cpus; 1110} 1111#endif 1112 1113void 1114assign_apic_irq(int apic, int intpin, int irq) 1115{ 1116 int x; 1117 1118 if (int_to_apicintpin[irq].ioapic != -1) 1119 panic("assign_apic_irq: inconsistent table"); 1120 1121 int_to_apicintpin[irq].ioapic = apic; 1122 int_to_apicintpin[irq].int_pin = intpin; 1123 int_to_apicintpin[irq].apic_address = ioapic[apic]; 1124 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 1125 1126 for (x = 0; x < nintrs; x++) { 1127 if ((io_apic_ints[x].int_type == 0 || 1128 io_apic_ints[x].int_type == 3) && 1129 io_apic_ints[x].int_vector == 0xff && 1130 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 1131 io_apic_ints[x].dst_apic_int == intpin) 1132 io_apic_ints[x].int_vector = irq; 1133 } 1134} 1135 1136void 1137revoke_apic_irq(int irq) 1138{ 1139 int x; 1140 int oldapic; 1141 int oldintpin; 1142 1143 if (int_to_apicintpin[irq].ioapic == -1) 1144 panic("revoke_apic_irq: inconsistent table"); 1145 1146 oldapic = int_to_apicintpin[irq].ioapic; 1147 oldintpin = int_to_apicintpin[irq].int_pin; 1148 1149 int_to_apicintpin[irq].ioapic = -1; 1150 int_to_apicintpin[irq].int_pin = 0; 1151 int_to_apicintpin[irq].apic_address = NULL; 1152 int_to_apicintpin[irq].redirindex = 0; 1153 1154 for (x = 0; x < nintrs; x++) { 1155 if ((io_apic_ints[x].int_type == 0 || 1156 io_apic_ints[x].int_type == 3) && 1157 io_apic_ints[x].int_vector != 0xff && 1158 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) && 1159 io_apic_ints[x].dst_apic_int == oldintpin) 1160 io_apic_ints[x].int_vector = 0xff; 1161 } 1162} 1163 1164 1165static void 1166allocate_apic_irq(int intr) 1167{ 1168 int apic; 1169 int intpin; 1170 int irq; 1171 1172 if (io_apic_ints[intr].int_vector != 0xff) 1173 return; /* Interrupt handler already assigned */ 1174 1175 if (io_apic_ints[intr].int_type != 0 && 1176 (io_apic_ints[intr].int_type != 3 || 1177 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) && 1178 io_apic_ints[intr].dst_apic_int == 0))) 1179 return; /* Not INT or ExtInt on != (0, 0) */ 1180 1181 irq = 0; 1182 while (irq < APIC_INTMAPSIZE && 1183 int_to_apicintpin[irq].ioapic != -1) 1184 irq++; 1185 1186 if (irq >= APIC_INTMAPSIZE) 1187 return; /* No free interrupt handlers */ 1188 1189 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id); 1190 intpin = io_apic_ints[intr].dst_apic_int; 1191 1192 assign_apic_irq(apic, intpin, irq); 1193 io_apic_setup_intpin(apic, intpin); 1194} 1195 1196 1197static void 1198swap_apic_id(int apic, int oldid, int newid) 1199{ 1200 int x; 1201 int oapic; 1202 1203 1204 if (oldid == newid) 1205 return; /* Nothing to do */ 1206 1207 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n", 1208 apic, oldid, newid); 1209 1210 /* Swap physical APIC IDs in interrupt entries */ 1211 for (x = 0; x < nintrs; x++) { 1212 if (io_apic_ints[x].dst_apic_id == oldid) 1213 io_apic_ints[x].dst_apic_id = newid; 1214 else if (io_apic_ints[x].dst_apic_id == newid) 1215 io_apic_ints[x].dst_apic_id = oldid; 1216 } 1217 1218 /* Swap physical APIC IDs in IO_TO_ID mappings */ 1219 for (oapic = 0; oapic < mp_napics; oapic++) 1220 if (IO_TO_ID(oapic) == newid) 1221 break; 1222 1223 if (oapic < mp_napics) { 1224 printf("Changing APIC ID for IO APIC #%d from " 1225 "%d to %d in MP table\n", 1226 oapic, newid, oldid); 1227 IO_TO_ID(oapic) = oldid; 1228 } 1229 IO_TO_ID(apic) = newid; 1230} 1231 1232 1233static void 1234fix_id_to_io_mapping(void) 1235{ 1236 int x; 1237 1238 for (x = 0; x < NAPICID; x++) 1239 ID_TO_IO(x) = -1; 1240 1241 for (x = 0; x <= mp_naps; x++) 1242 if (CPU_TO_ID(x) < NAPICID) 1243 ID_TO_IO(CPU_TO_ID(x)) = x; 1244 1245 for (x = 0; x < mp_napics; x++) 1246 if (IO_TO_ID(x) < NAPICID) 1247 ID_TO_IO(IO_TO_ID(x)) = x; 1248} 1249 1250 1251static int 1252first_free_apic_id(void) 1253{ 1254 int freeid, x; 1255 1256 for (freeid = 0; freeid < NAPICID; freeid++) { 1257 for (x = 0; x <= mp_naps; x++) 1258 if (CPU_TO_ID(x) == freeid) 1259 break; 1260 if (x <= mp_naps) 1261 continue; 1262 for (x = 0; x < mp_napics; x++) 1263 if (IO_TO_ID(x) == freeid) 1264 break; 1265 if (x < mp_napics) 1266 continue; 1267 return freeid; 1268 } 1269 return freeid; 1270} 1271 1272 1273static int 1274io_apic_id_acceptable(int apic, int id) 1275{ 1276 int cpu; /* Logical CPU number */ 1277 int oapic; /* Logical IO APIC number for other IO APIC */ 1278 1279 if (id >= NAPICID) 1280 return 0; /* Out of range */ 1281 1282 for (cpu = 0; cpu <= mp_naps; cpu++) 1283 if (CPU_TO_ID(cpu) == id) 1284 return 0; /* Conflict with CPU */ 1285 1286 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) 1287 if (IO_TO_ID(oapic) == id) 1288 return 0; /* Conflict with other APIC */ 1289 1290 return 1; /* ID is acceptable for IO APIC */ 1291} 1292 1293 1294/* 1295 * parse an Intel MP specification table 1296 */ 1297static void 1298fix_mp_table(void) 1299{ 1300 int x; 1301 int id; 1302 int bus_0 = 0; /* Stop GCC warning */ 1303 int bus_pci = 0; /* Stop GCC warning */ 1304 int num_pci_bus; 1305 int apic; /* IO APIC unit number */ 1306 int freeid; /* Free physical APIC ID */ 1307 int physid; /* Current physical IO APIC ID */ 1308 1309 /* 1310 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1311 * did it wrong. The MP spec says that when more than 1 PCI bus 1312 * exists the BIOS must begin with bus entries for the PCI bus and use 1313 * actual PCI bus numbering. This implies that when only 1 PCI bus 1314 * exists the BIOS can choose to ignore this ordering, and indeed many 1315 * MP motherboards do ignore it. This causes a problem when the PCI 1316 * sub-system makes requests of the MP sub-system based on PCI bus 1317 * numbers. So here we look for the situation and renumber the 1318 * busses and associated INTs in an effort to "make it right". 1319 */ 1320 1321 /* find bus 0, PCI bus, count the number of PCI busses */ 1322 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1323 if (bus_data[x].bus_id == 0) { 1324 bus_0 = x; 1325 } 1326 if (bus_data[x].bus_type == PCI) { 1327 ++num_pci_bus; 1328 bus_pci = x; 1329 } 1330 } 1331 /* 1332 * bus_0 == slot of bus with ID of 0 1333 * bus_pci == slot of last PCI bus encountered 1334 */ 1335 1336 /* check the 1 PCI bus case for sanity */ 1337 /* if it is number 0 all is well */ 1338 if (num_pci_bus == 1 && 1339 bus_data[bus_pci].bus_id != 0) { 1340 1341 /* mis-numbered, swap with whichever bus uses slot 0 */ 1342 1343 /* swap the bus entry types */ 1344 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1345 bus_data[bus_0].bus_type = PCI; 1346 1347 /* swap each relavant INTerrupt entry */ 1348 id = bus_data[bus_pci].bus_id; 1349 for (x = 0; x < nintrs; ++x) { 1350 if (io_apic_ints[x].src_bus_id == id) { 1351 io_apic_ints[x].src_bus_id = 0; 1352 } 1353 else if (io_apic_ints[x].src_bus_id == 0) { 1354 io_apic_ints[x].src_bus_id = id; 1355 } 1356 } 1357 } 1358 1359 /* Assign IO APIC IDs. 1360 * 1361 * First try the existing ID. If a conflict is detected, try 1362 * the ID in the MP table. If a conflict is still detected, find 1363 * a free id. 1364 * 1365 * We cannot use the ID_TO_IO table before all conflicts has been 1366 * resolved and the table has been corrected. 1367 */ 1368 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */ 1369 1370 /* First try to use the value set by the BIOS */ 1371 physid = io_apic_get_id(apic); 1372 if (io_apic_id_acceptable(apic, physid)) { 1373 if (IO_TO_ID(apic) != physid) 1374 swap_apic_id(apic, IO_TO_ID(apic), physid); 1375 continue; 1376 } 1377 1378 /* Then check if the value in the MP table is acceptable */ 1379 if (io_apic_id_acceptable(apic, IO_TO_ID(apic))) 1380 continue; 1381 1382 /* Last resort, find a free APIC ID and use it */ 1383 freeid = first_free_apic_id(); 1384 if (freeid >= NAPICID) 1385 panic("No free physical APIC IDs found"); 1386 1387 if (io_apic_id_acceptable(apic, freeid)) { 1388 swap_apic_id(apic, IO_TO_ID(apic), freeid); 1389 continue; 1390 } 1391 panic("Free physical APIC ID not usable"); 1392 } 1393 fix_id_to_io_mapping(); 1394 1395 /* detect and fix broken Compaq MP table */ 1396 if (apic_int_type(0, 0) == -1) { 1397 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n"); 1398 io_apic_ints[nintrs].int_type = 3; /* ExtInt */ 1399 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */ 1400 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */ 1401 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0); 1402 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */ 1403 nintrs++; 1404 } 1405} 1406 1407 1408/* Assign low level interrupt handlers */ 1409static void 1410setup_apic_irq_mapping(void) 1411{ 1412 int x; 1413 int int_vector; 1414 1415 /* Clear array */ 1416 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1417 int_to_apicintpin[x].ioapic = -1; 1418 int_to_apicintpin[x].int_pin = 0; 1419 int_to_apicintpin[x].apic_address = NULL; 1420 int_to_apicintpin[x].redirindex = 0; 1421 } 1422 1423 /* First assign ISA/EISA interrupts */ 1424 for (x = 0; x < nintrs; x++) { 1425 int_vector = io_apic_ints[x].src_bus_irq; 1426 if (int_vector < APIC_INTMAPSIZE && 1427 io_apic_ints[x].int_vector == 0xff && 1428 int_to_apicintpin[int_vector].ioapic == -1 && 1429 (apic_int_is_bus_type(x, ISA) || 1430 apic_int_is_bus_type(x, EISA)) && 1431 io_apic_ints[x].int_type == 0) { 1432 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1433 io_apic_ints[x].dst_apic_int, 1434 int_vector); 1435 } 1436 } 1437 1438 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */ 1439 for (x = 0; x < nintrs; x++) { 1440 if (io_apic_ints[x].dst_apic_int == 0 && 1441 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1442 io_apic_ints[x].int_vector == 0xff && 1443 int_to_apicintpin[0].ioapic == -1 && 1444 io_apic_ints[x].int_type == 3) { 1445 assign_apic_irq(0, 0, 0); 1446 break; 1447 } 1448 } 1449 /* PCI interrupt assignment is deferred */ 1450} 1451 1452 1453static int 1454processor_entry(proc_entry_ptr entry, int cpu) 1455{ 1456 /* check for usability */ 1457 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1458 return 0; 1459 1460 if(entry->apic_id >= NAPICID) 1461 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1); 1462 /* check for BSP flag */ 1463 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1464 boot_cpu_id = entry->apic_id; 1465 CPU_TO_ID(0) = entry->apic_id; 1466 ID_TO_CPU(entry->apic_id) = 0; 1467 return 0; /* its already been counted */ 1468 } 1469 1470 /* add another AP to list, if less than max number of CPUs */ 1471 else if (cpu < MAXCPU) { 1472 CPU_TO_ID(cpu) = entry->apic_id; 1473 ID_TO_CPU(entry->apic_id) = cpu; 1474 return 1; 1475 } 1476 1477 return 0; 1478} 1479 1480 1481static int 1482bus_entry(bus_entry_ptr entry, int bus) 1483{ 1484 int x; 1485 char c, name[8]; 1486 1487 /* encode the name into an index */ 1488 for (x = 0; x < 6; ++x) { 1489 if ((c = entry->bus_type[x]) == ' ') 1490 break; 1491 name[x] = c; 1492 } 1493 name[x] = '\0'; 1494 1495 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1496 panic("unknown bus type: '%s'", name); 1497 1498 bus_data[bus].bus_id = entry->bus_id; 1499 bus_data[bus].bus_type = x; 1500 1501 return 1; 1502} 1503 1504 1505static int 1506io_apic_entry(io_apic_entry_ptr entry, int apic) 1507{ 1508 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1509 return 0; 1510 1511 IO_TO_ID(apic) = entry->apic_id; 1512 if (entry->apic_id < NAPICID) 1513 ID_TO_IO(entry->apic_id) = apic; 1514 1515 return 1; 1516} 1517 1518 1519static int 1520lookup_bus_type(char *name) 1521{ 1522 int x; 1523 1524 for (x = 0; x < MAX_BUSTYPE; ++x) 1525 if (strcmp(bus_type_table[x].name, name) == 0) 1526 return bus_type_table[x].type; 1527 1528 return UNKNOWN_BUSTYPE; 1529} 1530 1531 1532static int 1533int_entry(int_entry_ptr entry, int intr) 1534{ 1535 int apic; 1536 1537 io_apic_ints[intr].int_type = entry->int_type; 1538 io_apic_ints[intr].int_flags = entry->int_flags; 1539 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1540 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1541 if (entry->dst_apic_id == 255) { 1542 /* This signal goes to all IO APICS. Select an IO APIC 1543 with sufficient number of interrupt pins */ 1544 for (apic = 0; apic < mp_napics; apic++) 1545 if (((io_apic_read(apic, IOAPIC_VER) & 1546 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1547 entry->dst_apic_int) 1548 break; 1549 if (apic < mp_napics) 1550 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1551 else 1552 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1553 } else 1554 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1555 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1556 1557 return 1; 1558} 1559 1560 1561static int 1562apic_int_is_bus_type(int intr, int bus_type) 1563{ 1564 int bus; 1565 1566 for (bus = 0; bus < mp_nbusses; ++bus) 1567 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1568 && ((int) bus_data[bus].bus_type == bus_type)) 1569 return 1; 1570 1571 return 0; 1572} 1573 1574 1575/* 1576 * Given a traditional ISA INT mask, return an APIC mask. 1577 */ 1578u_int 1579isa_apic_mask(u_int isa_mask) 1580{ 1581 int isa_irq; 1582 int apic_pin; 1583 1584#if defined(SKIP_IRQ15_REDIRECT) 1585 if (isa_mask == (1 << 15)) { 1586 printf("skipping ISA IRQ15 redirect\n"); 1587 return isa_mask; 1588 } 1589#endif /* SKIP_IRQ15_REDIRECT */ 1590 1591 isa_irq = ffs(isa_mask); /* find its bit position */ 1592 if (isa_irq == 0) /* doesn't exist */ 1593 return 0; 1594 --isa_irq; /* make it zero based */ 1595 1596 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1597 if (apic_pin == -1) 1598 return 0; 1599 1600 return (1 << apic_pin); /* convert pin# to a mask */ 1601} 1602 1603 1604/* 1605 * Determine which APIC pin an ISA/EISA INT is attached to. 1606 */ 1607#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1608#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1609#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1610#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1611 1612#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1613int 1614isa_apic_irq(int isa_irq) 1615{ 1616 int intr; 1617 1618 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1619 if (INTTYPE(intr) == 0) { /* standard INT */ 1620 if (SRCBUSIRQ(intr) == isa_irq) { 1621 if (apic_int_is_bus_type(intr, ISA) || 1622 apic_int_is_bus_type(intr, EISA)) { 1623 if (INTIRQ(intr) == 0xff) 1624 return -1; /* unassigned */ 1625 return INTIRQ(intr); /* found */ 1626 } 1627 } 1628 } 1629 } 1630 return -1; /* NOT found */ 1631} 1632 1633 1634/* 1635 * Determine which APIC pin a PCI INT is attached to. 1636 */ 1637#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1638#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1639#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1640int 1641pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1642{ 1643 int intr; 1644 1645 --pciInt; /* zero based */ 1646 1647 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1648 if ((INTTYPE(intr) == 0) /* standard INT */ 1649 && (SRCBUSID(intr) == pciBus) 1650 && (SRCBUSDEVICE(intr) == pciDevice) 1651 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1652 if (apic_int_is_bus_type(intr, PCI)) { 1653 if (INTIRQ(intr) == 0xff) 1654 allocate_apic_irq(intr); 1655 if (INTIRQ(intr) == 0xff) 1656 return -1; /* unassigned */ 1657 return INTIRQ(intr); /* exact match */ 1658 } 1659 1660 return -1; /* NOT found */ 1661} 1662 1663int 1664next_apic_irq(int irq) 1665{ 1666 int intr, ointr; 1667 int bus, bustype; 1668 1669 bus = 0; 1670 bustype = 0; 1671 for (intr = 0; intr < nintrs; intr++) { 1672 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1673 continue; 1674 bus = SRCBUSID(intr); 1675 bustype = apic_bus_type(bus); 1676 if (bustype != ISA && 1677 bustype != EISA && 1678 bustype != PCI) 1679 continue; 1680 break; 1681 } 1682 if (intr >= nintrs) { 1683 return -1; 1684 } 1685 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1686 if (INTTYPE(ointr) != 0) 1687 continue; 1688 if (bus != SRCBUSID(ointr)) 1689 continue; 1690 if (bustype == PCI) { 1691 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1692 continue; 1693 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1694 continue; 1695 } 1696 if (bustype == ISA || bustype == EISA) { 1697 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1698 continue; 1699 } 1700 if (INTPIN(intr) == INTPIN(ointr)) 1701 continue; 1702 break; 1703 } 1704 if (ointr >= nintrs) { 1705 return -1; 1706 } 1707 return INTIRQ(ointr); 1708} 1709#undef SRCBUSLINE 1710#undef SRCBUSDEVICE 1711#undef SRCBUSID 1712#undef SRCBUSIRQ 1713 1714#undef INTPIN 1715#undef INTIRQ 1716#undef INTAPIC 1717#undef INTTYPE 1718 1719 1720/* 1721 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1722 * 1723 * XXX FIXME: 1724 * Exactly what this means is unclear at this point. It is a solution 1725 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1726 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1727 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1728 * option. 1729 */ 1730int 1731undirect_isa_irq(int rirq) 1732{ 1733#if defined(READY) 1734 if (bootverbose) 1735 printf("Freeing redirected ISA irq %d.\n", rirq); 1736 /** FIXME: tickle the MB redirector chip */ 1737 return -1; 1738#else 1739 if (bootverbose) 1740 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1741 return 0; 1742#endif /* READY */ 1743} 1744 1745 1746/* 1747 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1748 */ 1749int 1750undirect_pci_irq(int rirq) 1751{ 1752#if defined(READY) 1753 if (bootverbose) 1754 printf("Freeing redirected PCI irq %d.\n", rirq); 1755 1756 /** FIXME: tickle the MB redirector chip */ 1757 return -1; 1758#else 1759 if (bootverbose) 1760 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1761 rirq); 1762 return 0; 1763#endif /* READY */ 1764} 1765 1766 1767/* 1768 * given a bus ID, return: 1769 * the bus type if found 1770 * -1 if NOT found 1771 */ 1772int 1773apic_bus_type(int id) 1774{ 1775 int x; 1776 1777 for (x = 0; x < mp_nbusses; ++x) 1778 if (bus_data[x].bus_id == id) 1779 return bus_data[x].bus_type; 1780 1781 return -1; 1782} 1783 1784 1785/* 1786 * given a LOGICAL APIC# and pin#, return: 1787 * the associated src bus ID if found 1788 * -1 if NOT found 1789 */ 1790int 1791apic_src_bus_id(int apic, int pin) 1792{ 1793 int x; 1794 1795 /* search each of the possible INTerrupt sources */ 1796 for (x = 0; x < nintrs; ++x) 1797 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1798 (pin == io_apic_ints[x].dst_apic_int)) 1799 return (io_apic_ints[x].src_bus_id); 1800 1801 return -1; /* NOT found */ 1802} 1803 1804 1805/* 1806 * given a LOGICAL APIC# and pin#, return: 1807 * the associated src bus IRQ if found 1808 * -1 if NOT found 1809 */ 1810int 1811apic_src_bus_irq(int apic, int pin) 1812{ 1813 int x; 1814 1815 for (x = 0; x < nintrs; x++) 1816 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1817 (pin == io_apic_ints[x].dst_apic_int)) 1818 return (io_apic_ints[x].src_bus_irq); 1819 1820 return -1; /* NOT found */ 1821} 1822 1823 1824/* 1825 * given a LOGICAL APIC# and pin#, return: 1826 * the associated INTerrupt type if found 1827 * -1 if NOT found 1828 */ 1829int 1830apic_int_type(int apic, int pin) 1831{ 1832 int x; 1833 1834 /* search each of the possible INTerrupt sources */ 1835 for (x = 0; x < nintrs; ++x) 1836 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1837 (pin == io_apic_ints[x].dst_apic_int)) 1838 return (io_apic_ints[x].int_type); 1839 1840 return -1; /* NOT found */ 1841} 1842 1843int 1844apic_irq(int apic, int pin) 1845{ 1846 int x; 1847 int res; 1848 1849 for (x = 0; x < nintrs; ++x) 1850 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1851 (pin == io_apic_ints[x].dst_apic_int)) { 1852 res = io_apic_ints[x].int_vector; 1853 if (res == 0xff) 1854 return -1; 1855 if (apic != int_to_apicintpin[res].ioapic) 1856 panic("apic_irq: inconsistent table"); 1857 if (pin != int_to_apicintpin[res].int_pin) 1858 panic("apic_irq inconsistent table (2)"); 1859 return res; 1860 } 1861 return -1; 1862} 1863 1864 1865/* 1866 * given a LOGICAL APIC# and pin#, return: 1867 * the associated trigger mode if found 1868 * -1 if NOT found 1869 */ 1870int 1871apic_trigger(int apic, int pin) 1872{ 1873 int x; 1874 1875 /* search each of the possible INTerrupt sources */ 1876 for (x = 0; x < nintrs; ++x) 1877 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1878 (pin == io_apic_ints[x].dst_apic_int)) 1879 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1880 1881 return -1; /* NOT found */ 1882} 1883 1884 1885/* 1886 * given a LOGICAL APIC# and pin#, return: 1887 * the associated 'active' level if found 1888 * -1 if NOT found 1889 */ 1890int 1891apic_polarity(int apic, int pin) 1892{ 1893 int x; 1894 1895 /* search each of the possible INTerrupt sources */ 1896 for (x = 0; x < nintrs; ++x) 1897 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1898 (pin == io_apic_ints[x].dst_apic_int)) 1899 return (io_apic_ints[x].int_flags & 0x03); 1900 1901 return -1; /* NOT found */ 1902} 1903 1904 1905/* 1906 * set data according to MP defaults 1907 * FIXME: probably not complete yet... 1908 */ 1909static void 1910default_mp_table(int type) 1911{ 1912 int ap_cpu_id; 1913#if defined(APIC_IO) 1914 int io_apic_id; 1915 int pin; 1916#endif /* APIC_IO */ 1917 1918#if 0 1919 printf(" MP default config type: %d\n", type); 1920 switch (type) { 1921 case 1: 1922 printf(" bus: ISA, APIC: 82489DX\n"); 1923 break; 1924 case 2: 1925 printf(" bus: EISA, APIC: 82489DX\n"); 1926 break; 1927 case 3: 1928 printf(" bus: EISA, APIC: 82489DX\n"); 1929 break; 1930 case 4: 1931 printf(" bus: MCA, APIC: 82489DX\n"); 1932 break; 1933 case 5: 1934 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1935 break; 1936 case 6: 1937 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1938 break; 1939 case 7: 1940 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1941 break; 1942 default: 1943 printf(" future type\n"); 1944 break; 1945 /* NOTREACHED */ 1946 } 1947#endif /* 0 */ 1948 1949 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1950 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1951 1952 /* BSP */ 1953 CPU_TO_ID(0) = boot_cpu_id; 1954 ID_TO_CPU(boot_cpu_id) = 0; 1955 1956 /* one and only AP */ 1957 CPU_TO_ID(1) = ap_cpu_id; 1958 ID_TO_CPU(ap_cpu_id) = 1; 1959 1960#if defined(APIC_IO) 1961 /* one and only IO APIC */ 1962 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1963 1964 /* 1965 * sanity check, refer to MP spec section 3.6.6, last paragraph 1966 * necessary as some hardware isn't properly setting up the IO APIC 1967 */ 1968#if defined(REALLY_ANAL_IOAPICID_VALUE) 1969 if (io_apic_id != 2) { 1970#else 1971 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1972#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1973 io_apic_set_id(0, 2); 1974 io_apic_id = 2; 1975 } 1976 IO_TO_ID(0) = io_apic_id; 1977 ID_TO_IO(io_apic_id) = 0; 1978#endif /* APIC_IO */ 1979 1980 /* fill out bus entries */ 1981 switch (type) { 1982 case 1: 1983 case 2: 1984 case 3: 1985 case 4: 1986 case 5: 1987 case 6: 1988 case 7: 1989 bus_data[0].bus_id = default_data[type - 1][1]; 1990 bus_data[0].bus_type = default_data[type - 1][2]; 1991 bus_data[1].bus_id = default_data[type - 1][3]; 1992 bus_data[1].bus_type = default_data[type - 1][4]; 1993 break; 1994 1995 /* case 4: case 7: MCA NOT supported */ 1996 default: /* illegal/reserved */ 1997 panic("BAD default MP config: %d", type); 1998 /* NOTREACHED */ 1999 } 2000 2001#if defined(APIC_IO) 2002 /* general cases from MP v1.4, table 5-2 */ 2003 for (pin = 0; pin < 16; ++pin) { 2004 io_apic_ints[pin].int_type = 0; 2005 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 2006 io_apic_ints[pin].src_bus_id = 0; 2007 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 2008 io_apic_ints[pin].dst_apic_id = io_apic_id; 2009 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 2010 } 2011 2012 /* special cases from MP v1.4, table 5-2 */ 2013 if (type == 2) { 2014 io_apic_ints[2].int_type = 0xff; /* N/C */ 2015 io_apic_ints[13].int_type = 0xff; /* N/C */ 2016#if !defined(APIC_MIXED_MODE) 2017 /** FIXME: ??? */ 2018 panic("sorry, can't support type 2 default yet"); 2019#endif /* APIC_MIXED_MODE */ 2020 } 2021 else 2022 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 2023 2024 if (type == 7) 2025 io_apic_ints[0].int_type = 0xff; /* N/C */ 2026 else 2027 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 2028#endif /* APIC_IO */ 2029} 2030 2031 2032/* 2033 * start each AP in our list 2034 */ 2035static int 2036start_all_aps(u_int boot_addr) 2037{ 2038 int x, i, pg; 2039#ifndef PC98 2040 u_char mpbiosreason; 2041#endif 2042 u_long mpbioswarmvec; 2043 struct pcpu *pc; 2044 char *stack; 2045 uintptr_t kptbase; 2046 2047 POSTCODE(START_ALL_APS_POST); 2048 2049 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 2050 2051 /* initialize BSP's local APIC */ 2052 apic_initialize(); 2053 bsp_apic_ready = 1; 2054 2055 /* install the AP 1st level boot code */ 2056 install_ap_tramp(boot_addr); 2057 2058 2059 /* save the current value of the warm-start vector */ 2060 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 2061#ifndef PC98 2062 outb(CMOS_REG, BIOS_RESET); 2063 mpbiosreason = inb(CMOS_DATA); 2064#endif 2065 2066 /* set up temporary P==V mapping for AP boot */ 2067 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 2068 kptbase = (uintptr_t)(void *)KPTphys; 2069 for (x = 0; x < NKPT; x++) 2070 PTD[x] = (pd_entry_t)(PG_V | PG_RW | 2071 ((kptbase + x * PAGE_SIZE) & PG_FRAME)); 2072 invltlb(); 2073 2074 /* start each AP */ 2075 for (x = 1; x <= mp_naps; ++x) { 2076 2077 /* This is a bit verbose, it will go away soon. */ 2078 2079 /* first page of AP's private space */ 2080 pg = x * i386_btop(sizeof(struct privatespace)); 2081 2082 /* allocate a new private data page */ 2083 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 2084 2085 /* wire it into the private page table page */ 2086 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 2087 2088 /* allocate and set up an idle stack data page */ 2089 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 2090 for (i = 0; i < KSTACK_PAGES; i++) 2091 SMPpt[pg + 1 + i] = (pt_entry_t) 2092 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2093 2094 /* prime data page for it to use */ 2095 pcpu_init(pc, x, sizeof(struct pcpu)); 2096 2097 /* setup a vector to our boot code */ 2098 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 2099 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 2100#ifndef PC98 2101 outb(CMOS_REG, BIOS_RESET); 2102 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 2103#endif 2104 2105 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE]; 2106 bootAP = x; 2107 2108 /* attempt to start the Application Processor */ 2109 CHECK_INIT(99); /* setup checkpoints */ 2110 if (!start_ap(x, boot_addr)) { 2111 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 2112 CHECK_PRINT("trace"); /* show checkpoints */ 2113 /* better panic as the AP may be running loose */ 2114 printf("panic y/n? [y] "); 2115 if (cngetc() != 'n') 2116 panic("bye-bye"); 2117 } 2118 CHECK_PRINT("trace"); /* show checkpoints */ 2119 2120 /* record its version info */ 2121 cpu_apic_versions[x] = cpu_apic_versions[0]; 2122 2123 all_cpus |= (1 << x); /* record AP in CPU map */ 2124 } 2125 2126 /* build our map of 'other' CPUs */ 2127 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2128 2129 /* fill in our (BSP) APIC version */ 2130 cpu_apic_versions[0] = lapic.version; 2131 2132 /* restore the warmstart vector */ 2133 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 2134#ifndef PC98 2135 outb(CMOS_REG, BIOS_RESET); 2136 outb(CMOS_DATA, mpbiosreason); 2137#endif 2138 2139 /* 2140 * Set up the idle context for the BSP. Similar to above except 2141 * that some was done by locore, some by pmap.c and some is implicit 2142 * because the BSP is cpu#0 and the page is initially zero, and also 2143 * because we can refer to variables by name on the BSP.. 2144 */ 2145 2146 /* Allocate and setup BSP idle stack */ 2147 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 2148 for (i = 0; i < KSTACK_PAGES; i++) 2149 SMPpt[1 + i] = (pt_entry_t) 2150 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2151 2152 for (x = 0; x < NKPT; x++) 2153 PTD[x] = 0; 2154 pmap_set_opt(); 2155 2156 /* number of APs actually started */ 2157 return mp_ncpus - 1; 2158} 2159 2160 2161/* 2162 * load the 1st level AP boot code into base memory. 2163 */ 2164 2165/* targets for relocation */ 2166extern void bigJump(void); 2167extern void bootCodeSeg(void); 2168extern void bootDataSeg(void); 2169extern void MPentry(void); 2170extern u_int MP_GDT; 2171extern u_int mp_gdtbase; 2172 2173static void 2174install_ap_tramp(u_int boot_addr) 2175{ 2176 int x; 2177 int size = *(int *) ((u_long) & bootMP_size); 2178 u_char *src = (u_char *) ((u_long) bootMP); 2179 u_char *dst = (u_char *) boot_addr + KERNBASE; 2180 u_int boot_base = (u_int) bootMP; 2181 u_int8_t *dst8; 2182 u_int16_t *dst16; 2183 u_int32_t *dst32; 2184 2185 POSTCODE(INSTALL_AP_TRAMP_POST); 2186 2187 for (x = 0; x < size; ++x) 2188 *dst++ = *src++; 2189 2190 /* 2191 * modify addresses in code we just moved to basemem. unfortunately we 2192 * need fairly detailed info about mpboot.s for this to work. changes 2193 * to mpboot.s might require changes here. 2194 */ 2195 2196 /* boot code is located in KERNEL space */ 2197 dst = (u_char *) boot_addr + KERNBASE; 2198 2199 /* modify the lgdt arg */ 2200 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 2201 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 2202 2203 /* modify the ljmp target for MPentry() */ 2204 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 2205 *dst32 = ((u_int) MPentry - KERNBASE); 2206 2207 /* modify the target for boot code segment */ 2208 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 2209 dst8 = (u_int8_t *) (dst16 + 1); 2210 *dst16 = (u_int) boot_addr & 0xffff; 2211 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2212 2213 /* modify the target for boot data segment */ 2214 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 2215 dst8 = (u_int8_t *) (dst16 + 1); 2216 *dst16 = (u_int) boot_addr & 0xffff; 2217 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2218} 2219 2220 2221/* 2222 * this function starts the AP (application processor) identified 2223 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2224 * to accomplish this. This is necessary because of the nuances 2225 * of the different hardware we might encounter. It ain't pretty, 2226 * but it seems to work. 2227 */ 2228static int 2229start_ap(int logical_cpu, u_int boot_addr) 2230{ 2231 int physical_cpu; 2232 int vector; 2233 int cpus; 2234 u_long icr_lo, icr_hi; 2235 2236 POSTCODE(START_AP_POST); 2237 2238 /* get the PHYSICAL APIC ID# */ 2239 physical_cpu = CPU_TO_ID(logical_cpu); 2240 2241 /* calculate the vector */ 2242 vector = (boot_addr >> 12) & 0xff; 2243 2244 /* used as a watchpoint to signal AP startup */ 2245 cpus = mp_ncpus; 2246 2247 /* 2248 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2249 * and running the target CPU. OR this INIT IPI might be latched (P5 2250 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2251 * ignored. 2252 */ 2253 2254 /* setup the address for the target AP */ 2255 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2256 icr_hi |= (physical_cpu << 24); 2257 lapic.icr_hi = icr_hi; 2258 2259 /* do an INIT IPI: assert RESET */ 2260 icr_lo = lapic.icr_lo & 0xfff00000; 2261 lapic.icr_lo = icr_lo | 0x0000c500; 2262 2263 /* wait for pending status end */ 2264 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2265 /* spin */ ; 2266 2267 /* do an INIT IPI: deassert RESET */ 2268 lapic.icr_lo = icr_lo | 0x00008500; 2269 2270 /* wait for pending status end */ 2271 u_sleep(10000); /* wait ~10mS */ 2272 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2273 /* spin */ ; 2274 2275 /* 2276 * next we do a STARTUP IPI: the previous INIT IPI might still be 2277 * latched, (P5 bug) this 1st STARTUP would then terminate 2278 * immediately, and the previously started INIT IPI would continue. OR 2279 * the previous INIT IPI has already run. and this STARTUP IPI will 2280 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2281 * will run. 2282 */ 2283 2284 /* do a STARTUP IPI */ 2285 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2286 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2287 /* spin */ ; 2288 u_sleep(200); /* wait ~200uS */ 2289 2290 /* 2291 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2292 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2293 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2294 * recognized after hardware RESET or INIT IPI. 2295 */ 2296 2297 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2298 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2299 /* spin */ ; 2300 u_sleep(200); /* wait ~200uS */ 2301 2302 /* wait for it to start */ 2303 set_apic_timer(5000000);/* == 5 seconds */ 2304 while (read_apic_timer()) 2305 if (mp_ncpus > cpus) 2306 return 1; /* return SUCCESS */ 2307 2308 return 0; /* return FAILURE */ 2309} 2310 2311#if defined(APIC_IO) 2312 2313#ifdef COUNT_XINVLTLB_HITS 2314u_int xhits_gbl[MAXCPU]; 2315u_int xhits_pg[MAXCPU]; 2316u_int xhits_rng[MAXCPU]; 2317SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 2318SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 2319 sizeof(xhits_gbl), "IU", ""); 2320SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 2321 sizeof(xhits_pg), "IU", ""); 2322SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 2323 sizeof(xhits_rng), "IU", ""); 2324 2325u_int ipi_global; 2326u_int ipi_page; 2327u_int ipi_range; 2328u_int ipi_range_size; 2329SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 2330SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 2331SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 2332SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 2333 0, ""); 2334 2335u_int ipi_masked_global; 2336u_int ipi_masked_page; 2337u_int ipi_masked_range; 2338u_int ipi_masked_range_size; 2339SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 2340 &ipi_masked_global, 0, ""); 2341SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 2342 &ipi_masked_page, 0, ""); 2343SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 2344 &ipi_masked_range, 0, ""); 2345SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 2346 &ipi_masked_range_size, 0, ""); 2347#endif 2348 2349/* 2350 * Flush the TLB on all other CPU's 2351 */ 2352static void 2353smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2354{ 2355 u_int ncpu; 2356 register_t eflags; 2357 2358 ncpu = mp_ncpus - 1; /* does not shootdown self */ 2359 if (ncpu < 1) 2360 return; /* no other cpus */ 2361 eflags = read_eflags(); 2362 if ((eflags & PSL_I) == 0) 2363 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled"); 2364 mtx_lock_spin(&smp_tlb_mtx); 2365 smp_tlb_addr1 = addr1; 2366 smp_tlb_addr2 = addr2; 2367 atomic_store_rel_int(&smp_tlb_wait, 0); 2368 ipi_all_but_self(vector); 2369 while (smp_tlb_wait < ncpu) 2370 ia32_pause(); 2371 mtx_unlock_spin(&smp_tlb_mtx); 2372} 2373 2374/* 2375 * This is about as magic as it gets. fortune(1) has got similar code 2376 * for reversing bits in a word. Who thinks up this stuff?? 2377 * 2378 * Yes, it does appear to be consistently faster than: 2379 * while (i = ffs(m)) { 2380 * m >>= i; 2381 * bits++; 2382 * } 2383 * and 2384 * while (lsb = (m & -m)) { // This is magic too 2385 * m &= ~lsb; // or: m ^= lsb 2386 * bits++; 2387 * } 2388 * Both of these latter forms do some very strange things on gcc-3.1 with 2389 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 2390 * There is probably an SSE or MMX popcnt instruction. 2391 * 2392 * I wonder if this should be in libkern? 2393 * 2394 * XXX Stop the presses! Another one: 2395 * static __inline u_int32_t 2396 * popcnt1(u_int32_t v) 2397 * { 2398 * v -= ((v >> 1) & 0x55555555); 2399 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 2400 * v = (v + (v >> 4)) & 0x0F0F0F0F; 2401 * return (v * 0x01010101) >> 24; 2402 * } 2403 * The downside is that it has a multiply. With a pentium3 with 2404 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 2405 * an imull, and in that case it is faster. In most other cases 2406 * it appears slightly slower. 2407 */ 2408static __inline u_int32_t 2409popcnt(u_int32_t m) 2410{ 2411 2412 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 2413 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 2414 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 2415 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 2416 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 2417 return m; 2418} 2419 2420static void 2421smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2422{ 2423 int ncpu, othercpus; 2424 register_t eflags; 2425 2426 othercpus = mp_ncpus - 1; 2427 if (mask == (u_int)-1) { 2428 ncpu = othercpus; 2429 if (ncpu < 1) 2430 return; 2431 } else { 2432 /* XXX there should be a pcpu self mask */ 2433 mask &= ~(1 << PCPU_GET(cpuid)); 2434 if (mask == 0) 2435 return; 2436 ncpu = popcnt(mask); 2437 if (ncpu > othercpus) { 2438 /* XXX this should be a panic offence */ 2439 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 2440 ncpu, othercpus); 2441 ncpu = othercpus; 2442 } 2443 /* XXX should be a panic, implied by mask == 0 above */ 2444 if (ncpu < 1) 2445 return; 2446 } 2447 eflags = read_eflags(); 2448 if ((eflags & PSL_I) == 0) 2449 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled"); 2450 mtx_lock_spin(&smp_tlb_mtx); 2451 smp_tlb_addr1 = addr1; 2452 smp_tlb_addr2 = addr2; 2453 atomic_store_rel_int(&smp_tlb_wait, 0); 2454 if (mask == (u_int)-1) 2455 ipi_all_but_self(vector); 2456 else 2457 ipi_selected(mask, vector); 2458 while (smp_tlb_wait < ncpu) 2459 ia32_pause(); 2460 mtx_unlock_spin(&smp_tlb_mtx); 2461} 2462#endif 2463 2464void 2465smp_invltlb(void) 2466{ 2467#if defined(APIC_IO) 2468 if (smp_started) { 2469 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 2470#ifdef COUNT_XINVLTLB_HITS 2471 ipi_global++; 2472#endif 2473 } 2474#endif /* APIC_IO */ 2475} 2476 2477void 2478smp_invlpg(vm_offset_t addr) 2479{ 2480#if defined(APIC_IO) 2481 if (smp_started) { 2482 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 2483#ifdef COUNT_XINVLTLB_HITS 2484 ipi_page++; 2485#endif 2486 } 2487#endif /* APIC_IO */ 2488} 2489 2490void 2491smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 2492{ 2493#if defined(APIC_IO) 2494 if (smp_started) { 2495 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 2496#ifdef COUNT_XINVLTLB_HITS 2497 ipi_range++; 2498 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 2499#endif 2500 } 2501#endif /* APIC_IO */ 2502} 2503 2504void 2505smp_masked_invltlb(u_int mask) 2506{ 2507#if defined(APIC_IO) 2508 if (smp_started) { 2509 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 2510#ifdef COUNT_XINVLTLB_HITS 2511 ipi_masked_global++; 2512#endif 2513 } 2514#endif /* APIC_IO */ 2515} 2516 2517void 2518smp_masked_invlpg(u_int mask, vm_offset_t addr) 2519{ 2520#if defined(APIC_IO) 2521 if (smp_started) { 2522 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 2523#ifdef COUNT_XINVLTLB_HITS 2524 ipi_masked_page++; 2525#endif 2526 } 2527#endif /* APIC_IO */ 2528} 2529 2530void 2531smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 2532{ 2533#if defined(APIC_IO) 2534 if (smp_started) { 2535 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 2536#ifdef COUNT_XINVLTLB_HITS 2537 ipi_masked_range++; 2538 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 2539#endif 2540 } 2541#endif /* APIC_IO */ 2542} 2543 2544 2545/* 2546 * This is called once the rest of the system is up and running and we're 2547 * ready to let the AP's out of the pen. 2548 */ 2549void 2550ap_init(void) 2551{ 2552 u_int apic_id; 2553 2554 /* spin until all the AP's are ready */ 2555 while (!aps_ready) 2556 ia32_pause(); 2557 2558 /* BSP may have changed PTD while we were waiting */ 2559 invltlb(); 2560 2561#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2562 lidt(&r_idt); 2563#endif 2564 2565 /* set up CPU registers and state */ 2566 cpu_setregs(); 2567 2568 /* set up FPU state on the AP */ 2569 npxinit(__INITIAL_NPXCW__); 2570 2571 /* set up SSE registers */ 2572 enable_sse(); 2573 2574 /* A quick check from sanity claus */ 2575 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2576 if (PCPU_GET(cpuid) != apic_id) { 2577 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 2578 printf("SMP: apic_id = %d\n", apic_id); 2579 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2580 panic("cpuid mismatch! boom!!"); 2581 } 2582 2583 /* Init local apic for irq's */ 2584 apic_initialize(); 2585 2586 /* Set memory range attributes for this CPU to match the BSP */ 2587 mem_range_AP_init(); 2588 2589 mtx_lock_spin(&ap_boot_mtx); 2590 2591 smp_cpus++; 2592 2593 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 2594 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 2595 2596 /* Build our map of 'other' CPUs. */ 2597 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2598 2599 if (bootverbose) 2600 apic_dump("ap_init()"); 2601 2602 if (smp_cpus == mp_ncpus) { 2603 /* enable IPI's, tlb shootdown, freezes etc */ 2604 atomic_store_rel_int(&smp_started, 1); 2605 smp_active = 1; /* historic */ 2606 } 2607 2608 mtx_unlock_spin(&ap_boot_mtx); 2609 2610 /* wait until all the AP's are up */ 2611 while (smp_started == 0) 2612 ia32_pause(); 2613 2614 /* ok, now grab sched_lock and enter the scheduler */ 2615 mtx_lock_spin(&sched_lock); 2616 2617 binuptime(PCPU_PTR(switchtime)); 2618 PCPU_SET(switchticks, ticks); 2619 2620 cpu_throw(); /* doesn't return */ 2621 2622 panic("scheduler returned us to %s", __func__); 2623} 2624 2625/* 2626 * For statclock, we send an IPI to all CPU's to have them call this 2627 * function. 2628 * 2629 * WARNING! unpend() will call statclock() directly and skip this 2630 * routine. 2631 */ 2632void 2633forwarded_statclock(struct clockframe frame) 2634{ 2635 2636 if (profprocs != 0) 2637 profclock(&frame); 2638 if (pscnt == psdiv) 2639 statclock(&frame); 2640} 2641 2642void 2643forward_statclock(void) 2644{ 2645 int map; 2646 2647 CTR0(KTR_SMP, "forward_statclock"); 2648 2649 if (!smp_started || cold || panicstr) 2650 return; 2651 2652 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2653 if (map != 0) 2654 ipi_selected(map, IPI_STATCLOCK); 2655} 2656 2657/* 2658 * For each hardclock(), we send an IPI to all other CPU's to have them 2659 * execute this function. It would be nice to reduce contention on 2660 * sched_lock if we could simply peek at the CPU to determine the user/kernel 2661 * state and call hardclock_process() on the CPU receiving the clock interrupt 2662 * and then just use a simple IPI to handle any ast's if needed. 2663 * 2664 * WARNING! unpend() will call hardclock_process() directly and skip this 2665 * routine. 2666 */ 2667void 2668forwarded_hardclock(struct clockframe frame) 2669{ 2670 2671 hardclock_process(&frame); 2672} 2673 2674void 2675forward_hardclock(void) 2676{ 2677 u_int map; 2678 2679 CTR0(KTR_SMP, "forward_hardclock"); 2680 2681 if (!smp_started || cold || panicstr) 2682 return; 2683 2684 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2685 if (map != 0) 2686 ipi_selected(map, IPI_HARDCLOCK); 2687} 2688 2689#ifdef APIC_INTR_REORDER 2690/* 2691 * Maintain mapping from softintr vector to isr bit in local apic. 2692 */ 2693void 2694set_lapic_isrloc(int intr, int vector) 2695{ 2696 if (intr < 0 || intr > 32) 2697 panic("set_apic_isrloc: bad intr argument: %d",intr); 2698 if (vector < ICU_OFFSET || vector > 255) 2699 panic("set_apic_isrloc: bad vector argument: %d",vector); 2700 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2701 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2702} 2703#endif 2704 2705/* 2706 * send an IPI to a set of cpus. 2707 */ 2708void 2709ipi_selected(u_int32_t cpus, u_int ipi) 2710{ 2711 2712 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 2713 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED); 2714} 2715 2716/* 2717 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 2718 */ 2719void 2720ipi_all(u_int ipi) 2721{ 2722 2723 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2724 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED); 2725} 2726 2727/* 2728 * send an IPI to all CPUs EXCEPT myself 2729 */ 2730void 2731ipi_all_but_self(u_int ipi) 2732{ 2733 2734 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2735 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED); 2736} 2737 2738/* 2739 * send an IPI to myself 2740 */ 2741void 2742ipi_self(u_int ipi) 2743{ 2744 2745 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2746 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED); 2747} 2748 2749static void 2750release_aps(void *dummy __unused) 2751{ 2752 2753 if (mp_ncpus == 1) 2754 return; 2755 mtx_lock_spin(&sched_lock); 2756 atomic_store_rel_int(&aps_ready, 1); 2757 while (smp_started == 0) 2758 ia32_pause(); 2759 mtx_unlock_spin(&sched_lock); 2760} 2761 2762SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 2763