mp_machdep.c revision 110296
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/amd64/amd64/mp_machdep.c 110296 2003-02-03 17:53:15Z jake $ 26 */ 27 28#include "opt_cpu.h" 29#include "opt_kstack_pages.h" 30 31#ifdef SMP 32#include <machine/smptests.h> 33#else 34#error 35#endif 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/cons.h> /* cngetc() */ 41#include <sys/dkstat.h> 42#ifdef GPROF 43#include <sys/gmon.h> 44#endif 45#include <sys/kernel.h> 46#include <sys/ktr.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/memrange.h> 50#include <sys/mutex.h> 51#include <sys/pcpu.h> 52#include <sys/proc.h> 53#include <sys/smp.h> 54#include <sys/sysctl.h> 55#include <sys/user.h> 56 57#include <vm/vm.h> 58#include <vm/vm_param.h> 59#include <vm/pmap.h> 60#include <vm/vm_kern.h> 61#include <vm/vm_extern.h> 62#include <vm/vm_map.h> 63 64#include <machine/apic.h> 65#include <machine/atomic.h> 66#include <machine/clock.h> 67#include <machine/cpu.h> 68#include <machine/cpufunc.h> 69#include <machine/mpapic.h> 70#include <machine/psl.h> 71#include <machine/segments.h> 72#include <machine/smp.h> 73#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 74#include <machine/tss.h> 75#include <machine/specialreg.h> 76#include <machine/privatespace.h> 77 78#if defined(APIC_IO) 79#include <machine/md_var.h> /* setidt() */ 80#include <i386/isa/icu.h> /* IPIs */ 81#include <i386/isa/intr_machdep.h> /* IPIs */ 82#endif /* APIC_IO */ 83 84#if defined(TEST_DEFAULT_CONFIG) 85#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 86#else 87#define MPFPS_MPFB1 mpfps->mpfb1 88#endif /* TEST_DEFAULT_CONFIG */ 89 90#define WARMBOOT_TARGET 0 91#define WARMBOOT_OFF (KERNBASE + 0x0467) 92#define WARMBOOT_SEG (KERNBASE + 0x0469) 93 94#ifdef PC98 95#define BIOS_BASE (0xe8000) 96#define BIOS_SIZE (0x18000) 97#else 98#define BIOS_BASE (0xf0000) 99#define BIOS_SIZE (0x10000) 100#endif 101#define BIOS_COUNT (BIOS_SIZE/4) 102 103#define CMOS_REG (0x70) 104#define CMOS_DATA (0x71) 105#define BIOS_RESET (0x0f) 106#define BIOS_WARM (0x0a) 107 108#define PROCENTRY_FLAG_EN 0x01 109#define PROCENTRY_FLAG_BP 0x02 110#define IOAPICENTRY_FLAG_EN 0x01 111 112 113/* MP Floating Pointer Structure */ 114typedef struct MPFPS { 115 char signature[4]; 116 void *pap; 117 u_char length; 118 u_char spec_rev; 119 u_char checksum; 120 u_char mpfb1; 121 u_char mpfb2; 122 u_char mpfb3; 123 u_char mpfb4; 124 u_char mpfb5; 125} *mpfps_t; 126 127/* MP Configuration Table Header */ 128typedef struct MPCTH { 129 char signature[4]; 130 u_short base_table_length; 131 u_char spec_rev; 132 u_char checksum; 133 u_char oem_id[8]; 134 u_char product_id[12]; 135 void *oem_table_pointer; 136 u_short oem_table_size; 137 u_short entry_count; 138 void *apic_address; 139 u_short extended_table_length; 140 u_char extended_table_checksum; 141 u_char reserved; 142} *mpcth_t; 143 144 145typedef struct PROCENTRY { 146 u_char type; 147 u_char apic_id; 148 u_char apic_version; 149 u_char cpu_flags; 150 u_long cpu_signature; 151 u_long feature_flags; 152 u_long reserved1; 153 u_long reserved2; 154} *proc_entry_ptr; 155 156typedef struct BUSENTRY { 157 u_char type; 158 u_char bus_id; 159 char bus_type[6]; 160} *bus_entry_ptr; 161 162typedef struct IOAPICENTRY { 163 u_char type; 164 u_char apic_id; 165 u_char apic_version; 166 u_char apic_flags; 167 void *apic_address; 168} *io_apic_entry_ptr; 169 170typedef struct INTENTRY { 171 u_char type; 172 u_char int_type; 173 u_short int_flags; 174 u_char src_bus_id; 175 u_char src_bus_irq; 176 u_char dst_apic_id; 177 u_char dst_apic_int; 178} *int_entry_ptr; 179 180/* descriptions of MP basetable entries */ 181typedef struct BASETABLE_ENTRY { 182 u_char type; 183 u_char length; 184 char name[16]; 185} basetable_entry; 186 187/* 188 * this code MUST be enabled here and in mpboot.s. 189 * it follows the very early stages of AP boot by placing values in CMOS ram. 190 * it NORMALLY will never be needed and thus the primitive method for enabling. 191 * 192#define CHECK_POINTS 193 */ 194 195#if defined(CHECK_POINTS) && !defined(PC98) 196#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 197#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 198 199#define CHECK_INIT(D); \ 200 CHECK_WRITE(0x34, (D)); \ 201 CHECK_WRITE(0x35, (D)); \ 202 CHECK_WRITE(0x36, (D)); \ 203 CHECK_WRITE(0x37, (D)); \ 204 CHECK_WRITE(0x38, (D)); \ 205 CHECK_WRITE(0x39, (D)); 206 207#define CHECK_PRINT(S); \ 208 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 209 (S), \ 210 CHECK_READ(0x34), \ 211 CHECK_READ(0x35), \ 212 CHECK_READ(0x36), \ 213 CHECK_READ(0x37), \ 214 CHECK_READ(0x38), \ 215 CHECK_READ(0x39)); 216 217#else /* CHECK_POINTS */ 218 219#define CHECK_INIT(D) 220#define CHECK_PRINT(S) 221 222#endif /* CHECK_POINTS */ 223 224/* 225 * Values to send to the POST hardware. 226 */ 227#define MP_BOOTADDRESS_POST 0x10 228#define MP_PROBE_POST 0x11 229#define MPTABLE_PASS1_POST 0x12 230 231#define MP_START_POST 0x13 232#define MP_ENABLE_POST 0x14 233#define MPTABLE_PASS2_POST 0x15 234 235#define START_ALL_APS_POST 0x16 236#define INSTALL_AP_TRAMP_POST 0x17 237#define START_AP_POST 0x18 238 239#define MP_ANNOUNCE_POST 0x19 240 241static int need_hyperthreading_fixup; 242static u_int logical_cpus; 243 244/* used to hold the AP's until we are ready to release them */ 245static struct mtx ap_boot_mtx; 246 247/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 248int current_postcode; 249 250/** XXX FIXME: what system files declare these??? */ 251extern struct region_descriptor r_gdt, r_idt; 252 253int bsp_apic_ready = 0; /* flags useability of BSP apic */ 254int mp_naps; /* # of Applications processors */ 255int mp_nbusses; /* # of busses */ 256int mp_napics; /* # of IO APICs */ 257int boot_cpu_id; /* designated BSP */ 258vm_offset_t cpu_apic_address; 259vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 260extern int nkpt; 261 262u_int32_t cpu_apic_versions[MAXCPU]; 263u_int32_t *io_apic_versions; 264 265#ifdef APIC_INTR_REORDER 266struct { 267 volatile int *location; 268 int bit; 269} apic_isrbit_location[32]; 270#endif 271 272struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE]; 273 274/* 275 * APIC ID logical/physical mapping structures. 276 * We oversize these to simplify boot-time config. 277 */ 278int cpu_num_to_apic_id[NAPICID]; 279int io_num_to_apic_id[NAPICID]; 280int apic_id_to_logical[NAPICID]; 281 282 283/* AP uses this during bootstrap. Do not staticize. */ 284char *bootSTK; 285static int bootAP; 286 287/* Hotwire a 0->4MB V==P mapping */ 288extern pt_entry_t *KPTphys; 289 290/* SMP page table page */ 291extern pt_entry_t *SMPpt; 292 293struct pcb stoppcbs[MAXCPU]; 294 295#ifdef APIC_IO 296/* Variables needed for SMP tlb shootdown. */ 297vm_offset_t smp_tlb_addr1; 298vm_offset_t smp_tlb_addr2; 299volatile int smp_tlb_wait; 300static struct mtx smp_tlb_mtx; 301#endif 302 303/* 304 * Local data and functions. 305 */ 306 307/* Set to 1 once we're ready to let the APs out of the pen. */ 308static volatile int aps_ready = 0; 309 310static int mp_capable; 311static u_int boot_address; 312static u_int base_memory; 313 314static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 315static mpfps_t mpfps; 316static int search_for_sig(u_int32_t target, int count); 317static void mp_enable(u_int boot_addr); 318 319static void mptable_hyperthread_fixup(u_int id_mask); 320static void mptable_pass1(void); 321static int mptable_pass2(void); 322static void default_mp_table(int type); 323static void fix_mp_table(void); 324static void setup_apic_irq_mapping(void); 325static void init_locks(void); 326static int start_all_aps(u_int boot_addr); 327static void install_ap_tramp(u_int boot_addr); 328static int start_ap(int logicalCpu, u_int boot_addr); 329void ap_init(void); 330static int apic_int_is_bus_type(int intr, int bus_type); 331static void release_aps(void *dummy); 332 333/* 334 * initialize all the SMP locks 335 */ 336 337/* lock region used by kernel profiling */ 338int mcount_lock; 339 340#ifdef USE_COMLOCK 341/* locks com (tty) data/hardware accesses: a FASTINTR() */ 342struct mtx com_mtx; 343#endif /* USE_COMLOCK */ 344 345static void 346init_locks(void) 347{ 348 349#ifdef USE_COMLOCK 350 mtx_init(&com_mtx, "com", NULL, MTX_SPIN); 351#endif /* USE_COMLOCK */ 352#ifdef APIC_IO 353 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN); 354#endif 355} 356 357/* 358 * Calculate usable address in base memory for AP trampoline code. 359 */ 360u_int 361mp_bootaddress(u_int basemem) 362{ 363 POSTCODE(MP_BOOTADDRESS_POST); 364 365 base_memory = basemem * 1024; /* convert to bytes */ 366 367 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 368 if ((base_memory - boot_address) < bootMP_size) 369 boot_address -= 4096; /* not enough, lower by 4k */ 370 371 return boot_address; 372} 373 374 375/* 376 * Look for an Intel MP spec table (ie, SMP capable hardware). 377 */ 378void 379i386_mp_probe(void) 380{ 381 int x; 382 u_long segment; 383 u_int32_t target; 384 385 POSTCODE(MP_PROBE_POST); 386 387 /* see if EBDA exists */ 388 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 389 /* search first 1K of EBDA */ 390 target = (u_int32_t) (segment << 4); 391 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 392 goto found; 393 } else { 394 /* last 1K of base memory, effective 'top of base' passed in */ 395 target = (u_int32_t) (base_memory - 0x400); 396 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 397 goto found; 398 } 399 400 /* search the BIOS */ 401 target = (u_int32_t) BIOS_BASE; 402 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 403 goto found; 404 405 /* nothing found */ 406 mpfps = (mpfps_t)0; 407 mp_capable = 0; 408 return; 409 410found: 411 /* calculate needed resources */ 412 mpfps = (mpfps_t)x; 413 mptable_pass1(); 414 415 /* flag fact that we are running multiple processors */ 416 mp_capable = 1; 417} 418 419int 420cpu_mp_probe(void) 421{ 422 /* 423 * Record BSP in CPU map 424 * This is done here so that MBUF init code works correctly. 425 */ 426 all_cpus = 1; 427 428 return (mp_capable); 429} 430 431/* 432 * Initialize the SMP hardware and the APIC and start up the AP's. 433 */ 434void 435cpu_mp_start(void) 436{ 437 POSTCODE(MP_START_POST); 438 439 /* look for MP capable motherboard */ 440 if (mp_capable) 441 mp_enable(boot_address); 442 else 443 panic("MP hardware not found!"); 444 445 cpu_setregs(); 446} 447 448 449/* 450 * Print various information about the SMP system hardware and setup. 451 */ 452void 453cpu_mp_announce(void) 454{ 455 int x; 456 457 POSTCODE(MP_ANNOUNCE_POST); 458 459 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 460 printf(", version: 0x%08x", cpu_apic_versions[0]); 461 printf(", at 0x%08x\n", cpu_apic_address); 462 for (x = 1; x <= mp_naps; ++x) { 463 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 464 printf(", version: 0x%08x", cpu_apic_versions[x]); 465 printf(", at 0x%08x\n", cpu_apic_address); 466 } 467 468#if defined(APIC_IO) 469 for (x = 0; x < mp_napics; ++x) { 470 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 471 printf(", version: 0x%08x", io_apic_versions[x]); 472 printf(", at 0x%08x\n", io_apic_address[x]); 473 } 474#else 475 printf(" Warning: APIC I/O disabled\n"); 476#endif /* APIC_IO */ 477} 478 479/* 480 * AP cpu's call this to sync up protected mode. 481 */ 482void 483init_secondary(void) 484{ 485 int gsel_tss; 486 int x, myid = bootAP; 487 u_int cr0; 488 489 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid]; 490 gdt_segs[GPROC0_SEL].ssd_base = 491 (int) &SMP_prvspace[myid].pcpu.pc_common_tss; 492 SMP_prvspace[myid].pcpu.pc_prvspace = 493 &SMP_prvspace[myid].pcpu; 494 495 for (x = 0; x < NGDT; x++) { 496 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 497 } 498 499 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 500 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 501 lgdt(&r_gdt); /* does magic intra-segment return */ 502 503 lidt(&r_idt); 504 505 lldt(_default_ldt); 506 PCPU_SET(currentldt, _default_ldt); 507 508 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 509 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 510 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 511 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 512 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 513 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 514 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 515 ltr(gsel_tss); 516 517 /* 518 * Set to a known state: 519 * Set by mpboot.s: CR0_PG, CR0_PE 520 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 521 */ 522 cr0 = rcr0(); 523 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 524 load_cr0(cr0); 525 526 pmap_set_opt(); 527} 528 529 530#if defined(APIC_IO) 531/* 532 * Final configuration of the BSP's local APIC: 533 * - disable 'pic mode'. 534 * - disable 'virtual wire mode'. 535 * - enable NMI. 536 */ 537void 538bsp_apic_configure(void) 539{ 540 u_char byte; 541 u_int32_t temp; 542 543 /* leave 'pic mode' if necessary */ 544 if (picmode) { 545 outb(0x22, 0x70); /* select IMCR */ 546 byte = inb(0x23); /* current contents */ 547 byte |= 0x01; /* mask external INTR */ 548 outb(0x23, byte); /* disconnect 8259s/NMI */ 549 } 550 551 /* mask lint0 (the 8259 'virtual wire' connection) */ 552 temp = lapic.lvt_lint0; 553 temp |= APIC_LVT_M; /* set the mask */ 554 lapic.lvt_lint0 = temp; 555 556 /* setup lint1 to handle NMI */ 557 temp = lapic.lvt_lint1; 558 temp &= ~APIC_LVT_M; /* clear the mask */ 559 lapic.lvt_lint1 = temp; 560 561 if (bootverbose) 562 apic_dump("bsp_apic_configure()"); 563} 564#endif /* APIC_IO */ 565 566 567/******************************************************************* 568 * local functions and data 569 */ 570 571/* 572 * start the SMP system 573 */ 574static void 575mp_enable(u_int boot_addr) 576{ 577 int x; 578#if defined(APIC_IO) 579 int apic; 580 u_int ux; 581#endif /* APIC_IO */ 582 583 POSTCODE(MP_ENABLE_POST); 584 585 /* turn on 4MB of V == P addressing so we can get to MP table */ 586 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME); 587 invltlb(); 588 589 /* examine the MP table for needed info, uses physical addresses */ 590 x = mptable_pass2(); 591 592 *(int *)PTD = 0; 593 invltlb(); 594 595 /* can't process default configs till the CPU APIC is pmapped */ 596 if (x) 597 default_mp_table(x); 598 599 /* post scan cleanup */ 600 fix_mp_table(); 601 setup_apic_irq_mapping(); 602 603#if defined(APIC_IO) 604 605 /* fill the LOGICAL io_apic_versions table */ 606 for (apic = 0; apic < mp_napics; ++apic) { 607 ux = io_apic_read(apic, IOAPIC_VER); 608 io_apic_versions[apic] = ux; 609 io_apic_set_id(apic, IO_TO_ID(apic)); 610 } 611 612 /* program each IO APIC in the system */ 613 for (apic = 0; apic < mp_napics; ++apic) 614 if (io_apic_setup(apic) < 0) 615 panic("IO APIC setup failure"); 616 617 /* install a 'Spurious INTerrupt' vector */ 618 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 619 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 620 621 /* install an inter-CPU IPI for TLB invalidation */ 622 setidt(XINVLTLB_OFFSET, Xinvltlb, 623 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 624 setidt(XINVLPG_OFFSET, Xinvlpg, 625 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 626 setidt(XINVLRNG_OFFSET, Xinvlrng, 627 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 628 629 /* install an inter-CPU IPI for forwarding hardclock() */ 630 setidt(XHARDCLOCK_OFFSET, Xhardclock, 631 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 632 633 /* install an inter-CPU IPI for forwarding statclock() */ 634 setidt(XSTATCLOCK_OFFSET, Xstatclock, 635 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 636 637 /* install an inter-CPU IPI for all-CPU rendezvous */ 638 setidt(XRENDEZVOUS_OFFSET, Xrendezvous, 639 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 640 641 /* install an inter-CPU IPI for forcing an additional software trap */ 642 setidt(XCPUAST_OFFSET, Xcpuast, 643 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 644 645 /* install an inter-CPU IPI for CPU stop/restart */ 646 setidt(XCPUSTOP_OFFSET, Xcpustop, 647 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 648 649#if defined(TEST_TEST1) 650 /* install a "fake hardware INTerrupt" vector */ 651 setidt(XTEST1_OFFSET, Xtest1, 652 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 653#endif /** TEST_TEST1 */ 654 655#endif /* APIC_IO */ 656 657 /* initialize all SMP locks */ 658 init_locks(); 659 660 /* start each Application Processor */ 661 start_all_aps(boot_addr); 662} 663 664 665/* 666 * look for the MP spec signature 667 */ 668 669/* string defined by the Intel MP Spec as identifying the MP table */ 670#define MP_SIG 0x5f504d5f /* _MP_ */ 671#define NEXT(X) ((X) += 4) 672static int 673search_for_sig(u_int32_t target, int count) 674{ 675 int x; 676 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 677 678 for (x = 0; x < count; NEXT(x)) 679 if (addr[x] == MP_SIG) 680 /* make array index a byte index */ 681 return (target + (x * sizeof(u_int32_t))); 682 683 return -1; 684} 685 686 687static basetable_entry basetable_entry_types[] = 688{ 689 {0, 20, "Processor"}, 690 {1, 8, "Bus"}, 691 {2, 8, "I/O APIC"}, 692 {3, 8, "I/O INT"}, 693 {4, 8, "Local INT"} 694}; 695 696typedef struct BUSDATA { 697 u_char bus_id; 698 enum busTypes bus_type; 699} bus_datum; 700 701typedef struct INTDATA { 702 u_char int_type; 703 u_short int_flags; 704 u_char src_bus_id; 705 u_char src_bus_irq; 706 u_char dst_apic_id; 707 u_char dst_apic_int; 708 u_char int_vector; 709} io_int, local_int; 710 711typedef struct BUSTYPENAME { 712 u_char type; 713 char name[7]; 714} bus_type_name; 715 716static bus_type_name bus_type_table[] = 717{ 718 {CBUS, "CBUS"}, 719 {CBUSII, "CBUSII"}, 720 {EISA, "EISA"}, 721 {MCA, "MCA"}, 722 {UNKNOWN_BUSTYPE, "---"}, 723 {ISA, "ISA"}, 724 {MCA, "MCA"}, 725 {UNKNOWN_BUSTYPE, "---"}, 726 {UNKNOWN_BUSTYPE, "---"}, 727 {UNKNOWN_BUSTYPE, "---"}, 728 {UNKNOWN_BUSTYPE, "---"}, 729 {UNKNOWN_BUSTYPE, "---"}, 730 {PCI, "PCI"}, 731 {UNKNOWN_BUSTYPE, "---"}, 732 {UNKNOWN_BUSTYPE, "---"}, 733 {UNKNOWN_BUSTYPE, "---"}, 734 {UNKNOWN_BUSTYPE, "---"}, 735 {XPRESS, "XPRESS"}, 736 {UNKNOWN_BUSTYPE, "---"} 737}; 738/* from MP spec v1.4, table 5-1 */ 739static int default_data[7][5] = 740{ 741/* nbus, id0, type0, id1, type1 */ 742 {1, 0, ISA, 255, 255}, 743 {1, 0, EISA, 255, 255}, 744 {1, 0, EISA, 255, 255}, 745 {1, 0, MCA, 255, 255}, 746 {2, 0, ISA, 1, PCI}, 747 {2, 0, EISA, 1, PCI}, 748 {2, 0, MCA, 1, PCI} 749}; 750 751 752/* the bus data */ 753static bus_datum *bus_data; 754 755/* the IO INT data, one entry per possible APIC INTerrupt */ 756static io_int *io_apic_ints; 757 758static int nintrs; 759 760static int processor_entry(proc_entry_ptr entry, int cpu); 761static int bus_entry(bus_entry_ptr entry, int bus); 762static int io_apic_entry(io_apic_entry_ptr entry, int apic); 763static int int_entry(int_entry_ptr entry, int intr); 764static int lookup_bus_type(char *name); 765 766 767/* 768 * 1st pass on motherboard's Intel MP specification table. 769 * 770 * initializes: 771 * mp_ncpus = 1 772 * 773 * determines: 774 * cpu_apic_address (common to all CPUs) 775 * io_apic_address[N] 776 * mp_naps 777 * mp_nbusses 778 * mp_napics 779 * nintrs 780 */ 781static void 782mptable_pass1(void) 783{ 784 int x; 785 mpcth_t cth; 786 int totalSize; 787 void* position; 788 int count; 789 int type; 790 u_int id_mask; 791 792 POSTCODE(MPTABLE_PASS1_POST); 793 794 /* clear various tables */ 795 for (x = 0; x < NAPICID; ++x) { 796 io_apic_address[x] = ~0; /* IO APIC address table */ 797 } 798 799 /* init everything to empty */ 800 mp_naps = 0; 801 mp_nbusses = 0; 802 mp_napics = 0; 803 nintrs = 0; 804 id_mask = 0; 805 806 /* check for use of 'default' configuration */ 807 if (MPFPS_MPFB1 != 0) { 808 /* use default addresses */ 809 cpu_apic_address = DEFAULT_APIC_BASE; 810 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 811 812 /* fill in with defaults */ 813 mp_naps = 2; /* includes BSP */ 814 mp_maxid = 1; 815 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 816#if defined(APIC_IO) 817 mp_napics = 1; 818 nintrs = 16; 819#endif /* APIC_IO */ 820 } 821 else { 822 if ((cth = mpfps->pap) == 0) 823 panic("MP Configuration Table Header MISSING!"); 824 825 cpu_apic_address = (vm_offset_t) cth->apic_address; 826 827 /* walk the table, recording info of interest */ 828 totalSize = cth->base_table_length - sizeof(struct MPCTH); 829 position = (u_char *) cth + sizeof(struct MPCTH); 830 count = cth->entry_count; 831 832 while (count--) { 833 switch (type = *(u_char *) position) { 834 case 0: /* processor_entry */ 835 if (((proc_entry_ptr)position)->cpu_flags 836 & PROCENTRY_FLAG_EN) { 837 ++mp_naps; 838 mp_maxid++; 839 id_mask |= 1 << 840 ((proc_entry_ptr)position)->apic_id; 841 } 842 break; 843 case 1: /* bus_entry */ 844 ++mp_nbusses; 845 break; 846 case 2: /* io_apic_entry */ 847 if (((io_apic_entry_ptr)position)->apic_flags 848 & IOAPICENTRY_FLAG_EN) 849 io_apic_address[mp_napics++] = 850 (vm_offset_t)((io_apic_entry_ptr) 851 position)->apic_address; 852 break; 853 case 3: /* int_entry */ 854 ++nintrs; 855 break; 856 case 4: /* int_entry */ 857 break; 858 default: 859 panic("mpfps Base Table HOSED!"); 860 /* NOTREACHED */ 861 } 862 863 totalSize -= basetable_entry_types[type].length; 864 (u_char*)position += basetable_entry_types[type].length; 865 } 866 } 867 868 /* qualify the numbers */ 869 if (mp_naps > MAXCPU) { 870 printf("Warning: only using %d of %d available CPUs!\n", 871 MAXCPU, mp_naps); 872 mp_naps = MAXCPU; 873 } 874 875 /* See if we need to fixup HT logical CPUs. */ 876 mptable_hyperthread_fixup(id_mask); 877 878 /* 879 * Count the BSP. 880 * This is also used as a counter while starting the APs. 881 */ 882 mp_ncpus = 1; 883 884 --mp_naps; /* subtract the BSP */ 885} 886 887 888/* 889 * 2nd pass on motherboard's Intel MP specification table. 890 * 891 * sets: 892 * boot_cpu_id 893 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 894 * CPU_TO_ID(N), logical CPU to APIC ID table 895 * IO_TO_ID(N), logical IO to APIC ID table 896 * bus_data[N] 897 * io_apic_ints[N] 898 */ 899static int 900mptable_pass2(void) 901{ 902 struct PROCENTRY proc; 903 int x; 904 mpcth_t cth; 905 int totalSize; 906 void* position; 907 int count; 908 int type; 909 int apic, bus, cpu, intr; 910 int i, j; 911 int pgeflag; 912 913 POSTCODE(MPTABLE_PASS2_POST); 914 915 /* Initialize fake proc entry for use with HT fixup. */ 916 bzero(&proc, sizeof(proc)); 917 proc.type = 0; 918 proc.cpu_flags = PROCENTRY_FLAG_EN; 919 920 pgeflag = 0; /* XXX - Not used under SMP yet. */ 921 922 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics, 923 M_DEVBUF, 0); 924 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics, 925 M_DEVBUF, 0); 926 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1), 927 M_DEVBUF, 0); 928 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses, 929 M_DEVBUF, 0); 930 931 bzero(ioapic, sizeof(ioapic_t *) * mp_napics); 932 933 for (i = 0; i < mp_napics; i++) { 934 for (j = 0; j < mp_napics; j++) { 935 /* same page frame as a previous IO apic? */ 936 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 937 (io_apic_address[i] & PG_FRAME)) { 938 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 939 + (NPTEPG-2-j) * PAGE_SIZE 940 + (io_apic_address[i] & PAGE_MASK)); 941 break; 942 } 943 /* use this slot if available */ 944 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) { 945 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW | 946 pgeflag | (io_apic_address[i] & PG_FRAME)); 947 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace 948 + (NPTEPG-2-j) * PAGE_SIZE 949 + (io_apic_address[i] & PAGE_MASK)); 950 break; 951 } 952 } 953 } 954 955 /* clear various tables */ 956 for (x = 0; x < NAPICID; ++x) { 957 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 958 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 959 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 960 } 961 962 /* clear bus data table */ 963 for (x = 0; x < mp_nbusses; ++x) 964 bus_data[x].bus_id = 0xff; 965 966 /* clear IO APIC INT table */ 967 for (x = 0; x < (nintrs + 1); ++x) { 968 io_apic_ints[x].int_type = 0xff; 969 io_apic_ints[x].int_vector = 0xff; 970 } 971 972 /* setup the cpu/apic mapping arrays */ 973 boot_cpu_id = -1; 974 975 /* record whether PIC or virtual-wire mode */ 976 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 977 978 /* check for use of 'default' configuration */ 979 if (MPFPS_MPFB1 != 0) 980 return MPFPS_MPFB1; /* return default configuration type */ 981 982 if ((cth = mpfps->pap) == 0) 983 panic("MP Configuration Table Header MISSING!"); 984 985 /* walk the table, recording info of interest */ 986 totalSize = cth->base_table_length - sizeof(struct MPCTH); 987 position = (u_char *) cth + sizeof(struct MPCTH); 988 count = cth->entry_count; 989 apic = bus = intr = 0; 990 cpu = 1; /* pre-count the BSP */ 991 992 while (count--) { 993 switch (type = *(u_char *) position) { 994 case 0: 995 if (processor_entry(position, cpu)) 996 ++cpu; 997 998 if (need_hyperthreading_fixup) { 999 /* 1000 * Create fake mptable processor entries 1001 * and feed them to processor_entry() to 1002 * enumerate the logical CPUs. 1003 */ 1004 proc.apic_id = ((proc_entry_ptr)position)->apic_id; 1005 for (i = 1; i < logical_cpus; i++) { 1006 proc.apic_id++; 1007 (void)processor_entry(&proc, cpu); 1008 cpu++; 1009 } 1010 } 1011 break; 1012 case 1: 1013 if (bus_entry(position, bus)) 1014 ++bus; 1015 break; 1016 case 2: 1017 if (io_apic_entry(position, apic)) 1018 ++apic; 1019 break; 1020 case 3: 1021 if (int_entry(position, intr)) 1022 ++intr; 1023 break; 1024 case 4: 1025 /* int_entry(position); */ 1026 break; 1027 default: 1028 panic("mpfps Base Table HOSED!"); 1029 /* NOTREACHED */ 1030 } 1031 1032 totalSize -= basetable_entry_types[type].length; 1033 (u_char *) position += basetable_entry_types[type].length; 1034 } 1035 1036 if (boot_cpu_id == -1) 1037 panic("NO BSP found!"); 1038 1039 /* report fact that its NOT a default configuration */ 1040 return 0; 1041} 1042 1043/* 1044 * Check if we should perform a hyperthreading "fix-up" to 1045 * enumerate any logical CPU's that aren't already listed 1046 * in the table. 1047 * 1048 * XXX: We assume that all of the physical CPUs in the 1049 * system have the same number of logical CPUs. 1050 * 1051 * XXX: We assume that APIC ID's are allocated such that 1052 * the APIC ID's for a physical processor are aligned 1053 * with the number of logical CPU's in the processor. 1054 */ 1055static void 1056mptable_hyperthread_fixup(u_int id_mask) 1057{ 1058 u_int i, id; 1059 1060 /* Nothing to do if there is no HTT support. */ 1061 if ((cpu_feature & CPUID_HTT) == 0) 1062 return; 1063 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 1064 if (logical_cpus <= 1) 1065 return; 1066 1067 /* 1068 * For each APIC ID of a CPU that is set in the mask, 1069 * scan the other candidate APIC ID's for this 1070 * physical processor. If any of those ID's are 1071 * already in the table, then kill the fixup. 1072 */ 1073 for (id = 0; id <= MAXCPU; id++) { 1074 if ((id_mask & 1 << id) == 0) 1075 continue; 1076 /* First, make sure we are on a logical_cpus boundary. */ 1077 if (id % logical_cpus != 0) 1078 return; 1079 for (i = id + 1; i < id + logical_cpus; i++) 1080 if ((id_mask & 1 << i) != 0) 1081 return; 1082 } 1083 1084 /* 1085 * Ok, the ID's checked out, so enable the fixup. We have to fixup 1086 * mp_naps and mp_maxid right now. 1087 */ 1088 need_hyperthreading_fixup = 1; 1089 mp_maxid *= logical_cpus; 1090 mp_naps *= logical_cpus; 1091} 1092 1093void 1094assign_apic_irq(int apic, int intpin, int irq) 1095{ 1096 int x; 1097 1098 if (int_to_apicintpin[irq].ioapic != -1) 1099 panic("assign_apic_irq: inconsistent table"); 1100 1101 int_to_apicintpin[irq].ioapic = apic; 1102 int_to_apicintpin[irq].int_pin = intpin; 1103 int_to_apicintpin[irq].apic_address = ioapic[apic]; 1104 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin; 1105 1106 for (x = 0; x < nintrs; x++) { 1107 if ((io_apic_ints[x].int_type == 0 || 1108 io_apic_ints[x].int_type == 3) && 1109 io_apic_ints[x].int_vector == 0xff && 1110 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) && 1111 io_apic_ints[x].dst_apic_int == intpin) 1112 io_apic_ints[x].int_vector = irq; 1113 } 1114} 1115 1116void 1117revoke_apic_irq(int irq) 1118{ 1119 int x; 1120 int oldapic; 1121 int oldintpin; 1122 1123 if (int_to_apicintpin[irq].ioapic == -1) 1124 panic("revoke_apic_irq: inconsistent table"); 1125 1126 oldapic = int_to_apicintpin[irq].ioapic; 1127 oldintpin = int_to_apicintpin[irq].int_pin; 1128 1129 int_to_apicintpin[irq].ioapic = -1; 1130 int_to_apicintpin[irq].int_pin = 0; 1131 int_to_apicintpin[irq].apic_address = NULL; 1132 int_to_apicintpin[irq].redirindex = 0; 1133 1134 for (x = 0; x < nintrs; x++) { 1135 if ((io_apic_ints[x].int_type == 0 || 1136 io_apic_ints[x].int_type == 3) && 1137 io_apic_ints[x].int_vector != 0xff && 1138 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) && 1139 io_apic_ints[x].dst_apic_int == oldintpin) 1140 io_apic_ints[x].int_vector = 0xff; 1141 } 1142} 1143 1144 1145static void 1146allocate_apic_irq(int intr) 1147{ 1148 int apic; 1149 int intpin; 1150 int irq; 1151 1152 if (io_apic_ints[intr].int_vector != 0xff) 1153 return; /* Interrupt handler already assigned */ 1154 1155 if (io_apic_ints[intr].int_type != 0 && 1156 (io_apic_ints[intr].int_type != 3 || 1157 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) && 1158 io_apic_ints[intr].dst_apic_int == 0))) 1159 return; /* Not INT or ExtInt on != (0, 0) */ 1160 1161 irq = 0; 1162 while (irq < APIC_INTMAPSIZE && 1163 int_to_apicintpin[irq].ioapic != -1) 1164 irq++; 1165 1166 if (irq >= APIC_INTMAPSIZE) 1167 return; /* No free interrupt handlers */ 1168 1169 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id); 1170 intpin = io_apic_ints[intr].dst_apic_int; 1171 1172 assign_apic_irq(apic, intpin, irq); 1173 io_apic_setup_intpin(apic, intpin); 1174} 1175 1176 1177static void 1178swap_apic_id(int apic, int oldid, int newid) 1179{ 1180 int x; 1181 int oapic; 1182 1183 1184 if (oldid == newid) 1185 return; /* Nothing to do */ 1186 1187 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n", 1188 apic, oldid, newid); 1189 1190 /* Swap physical APIC IDs in interrupt entries */ 1191 for (x = 0; x < nintrs; x++) { 1192 if (io_apic_ints[x].dst_apic_id == oldid) 1193 io_apic_ints[x].dst_apic_id = newid; 1194 else if (io_apic_ints[x].dst_apic_id == newid) 1195 io_apic_ints[x].dst_apic_id = oldid; 1196 } 1197 1198 /* Swap physical APIC IDs in IO_TO_ID mappings */ 1199 for (oapic = 0; oapic < mp_napics; oapic++) 1200 if (IO_TO_ID(oapic) == newid) 1201 break; 1202 1203 if (oapic < mp_napics) { 1204 printf("Changing APIC ID for IO APIC #%d from " 1205 "%d to %d in MP table\n", 1206 oapic, newid, oldid); 1207 IO_TO_ID(oapic) = oldid; 1208 } 1209 IO_TO_ID(apic) = newid; 1210} 1211 1212 1213static void 1214fix_id_to_io_mapping(void) 1215{ 1216 int x; 1217 1218 for (x = 0; x < NAPICID; x++) 1219 ID_TO_IO(x) = -1; 1220 1221 for (x = 0; x <= mp_naps; x++) 1222 if (CPU_TO_ID(x) < NAPICID) 1223 ID_TO_IO(CPU_TO_ID(x)) = x; 1224 1225 for (x = 0; x < mp_napics; x++) 1226 if (IO_TO_ID(x) < NAPICID) 1227 ID_TO_IO(IO_TO_ID(x)) = x; 1228} 1229 1230 1231static int 1232first_free_apic_id(void) 1233{ 1234 int freeid, x; 1235 1236 for (freeid = 0; freeid < NAPICID; freeid++) { 1237 for (x = 0; x <= mp_naps; x++) 1238 if (CPU_TO_ID(x) == freeid) 1239 break; 1240 if (x <= mp_naps) 1241 continue; 1242 for (x = 0; x < mp_napics; x++) 1243 if (IO_TO_ID(x) == freeid) 1244 break; 1245 if (x < mp_napics) 1246 continue; 1247 return freeid; 1248 } 1249 return freeid; 1250} 1251 1252 1253static int 1254io_apic_id_acceptable(int apic, int id) 1255{ 1256 int cpu; /* Logical CPU number */ 1257 int oapic; /* Logical IO APIC number for other IO APIC */ 1258 1259 if (id >= NAPICID) 1260 return 0; /* Out of range */ 1261 1262 for (cpu = 0; cpu <= mp_naps; cpu++) 1263 if (CPU_TO_ID(cpu) == id) 1264 return 0; /* Conflict with CPU */ 1265 1266 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) 1267 if (IO_TO_ID(oapic) == id) 1268 return 0; /* Conflict with other APIC */ 1269 1270 return 1; /* ID is acceptable for IO APIC */ 1271} 1272 1273 1274/* 1275 * parse an Intel MP specification table 1276 */ 1277static void 1278fix_mp_table(void) 1279{ 1280 int x; 1281 int id; 1282 int bus_0 = 0; /* Stop GCC warning */ 1283 int bus_pci = 0; /* Stop GCC warning */ 1284 int num_pci_bus; 1285 int apic; /* IO APIC unit number */ 1286 int freeid; /* Free physical APIC ID */ 1287 int physid; /* Current physical IO APIC ID */ 1288 1289 /* 1290 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 1291 * did it wrong. The MP spec says that when more than 1 PCI bus 1292 * exists the BIOS must begin with bus entries for the PCI bus and use 1293 * actual PCI bus numbering. This implies that when only 1 PCI bus 1294 * exists the BIOS can choose to ignore this ordering, and indeed many 1295 * MP motherboards do ignore it. This causes a problem when the PCI 1296 * sub-system makes requests of the MP sub-system based on PCI bus 1297 * numbers. So here we look for the situation and renumber the 1298 * busses and associated INTs in an effort to "make it right". 1299 */ 1300 1301 /* find bus 0, PCI bus, count the number of PCI busses */ 1302 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 1303 if (bus_data[x].bus_id == 0) { 1304 bus_0 = x; 1305 } 1306 if (bus_data[x].bus_type == PCI) { 1307 ++num_pci_bus; 1308 bus_pci = x; 1309 } 1310 } 1311 /* 1312 * bus_0 == slot of bus with ID of 0 1313 * bus_pci == slot of last PCI bus encountered 1314 */ 1315 1316 /* check the 1 PCI bus case for sanity */ 1317 /* if it is number 0 all is well */ 1318 if (num_pci_bus == 1 && 1319 bus_data[bus_pci].bus_id != 0) { 1320 1321 /* mis-numbered, swap with whichever bus uses slot 0 */ 1322 1323 /* swap the bus entry types */ 1324 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 1325 bus_data[bus_0].bus_type = PCI; 1326 1327 /* swap each relavant INTerrupt entry */ 1328 id = bus_data[bus_pci].bus_id; 1329 for (x = 0; x < nintrs; ++x) { 1330 if (io_apic_ints[x].src_bus_id == id) { 1331 io_apic_ints[x].src_bus_id = 0; 1332 } 1333 else if (io_apic_ints[x].src_bus_id == 0) { 1334 io_apic_ints[x].src_bus_id = id; 1335 } 1336 } 1337 } 1338 1339 /* Assign IO APIC IDs. 1340 * 1341 * First try the existing ID. If a conflict is detected, try 1342 * the ID in the MP table. If a conflict is still detected, find 1343 * a free id. 1344 * 1345 * We cannot use the ID_TO_IO table before all conflicts has been 1346 * resolved and the table has been corrected. 1347 */ 1348 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */ 1349 1350 /* First try to use the value set by the BIOS */ 1351 physid = io_apic_get_id(apic); 1352 if (io_apic_id_acceptable(apic, physid)) { 1353 if (IO_TO_ID(apic) != physid) 1354 swap_apic_id(apic, IO_TO_ID(apic), physid); 1355 continue; 1356 } 1357 1358 /* Then check if the value in the MP table is acceptable */ 1359 if (io_apic_id_acceptable(apic, IO_TO_ID(apic))) 1360 continue; 1361 1362 /* Last resort, find a free APIC ID and use it */ 1363 freeid = first_free_apic_id(); 1364 if (freeid >= NAPICID) 1365 panic("No free physical APIC IDs found"); 1366 1367 if (io_apic_id_acceptable(apic, freeid)) { 1368 swap_apic_id(apic, IO_TO_ID(apic), freeid); 1369 continue; 1370 } 1371 panic("Free physical APIC ID not usable"); 1372 } 1373 fix_id_to_io_mapping(); 1374 1375 /* detect and fix broken Compaq MP table */ 1376 if (apic_int_type(0, 0) == -1) { 1377 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n"); 1378 io_apic_ints[nintrs].int_type = 3; /* ExtInt */ 1379 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */ 1380 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */ 1381 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0); 1382 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */ 1383 nintrs++; 1384 } 1385} 1386 1387 1388/* Assign low level interrupt handlers */ 1389static void 1390setup_apic_irq_mapping(void) 1391{ 1392 int x; 1393 int int_vector; 1394 1395 /* Clear array */ 1396 for (x = 0; x < APIC_INTMAPSIZE; x++) { 1397 int_to_apicintpin[x].ioapic = -1; 1398 int_to_apicintpin[x].int_pin = 0; 1399 int_to_apicintpin[x].apic_address = NULL; 1400 int_to_apicintpin[x].redirindex = 0; 1401 } 1402 1403 /* First assign ISA/EISA interrupts */ 1404 for (x = 0; x < nintrs; x++) { 1405 int_vector = io_apic_ints[x].src_bus_irq; 1406 if (int_vector < APIC_INTMAPSIZE && 1407 io_apic_ints[x].int_vector == 0xff && 1408 int_to_apicintpin[int_vector].ioapic == -1 && 1409 (apic_int_is_bus_type(x, ISA) || 1410 apic_int_is_bus_type(x, EISA)) && 1411 io_apic_ints[x].int_type == 0) { 1412 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id), 1413 io_apic_ints[x].dst_apic_int, 1414 int_vector); 1415 } 1416 } 1417 1418 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */ 1419 for (x = 0; x < nintrs; x++) { 1420 if (io_apic_ints[x].dst_apic_int == 0 && 1421 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) && 1422 io_apic_ints[x].int_vector == 0xff && 1423 int_to_apicintpin[0].ioapic == -1 && 1424 io_apic_ints[x].int_type == 3) { 1425 assign_apic_irq(0, 0, 0); 1426 break; 1427 } 1428 } 1429 /* PCI interrupt assignment is deferred */ 1430} 1431 1432 1433static int 1434processor_entry(proc_entry_ptr entry, int cpu) 1435{ 1436 /* check for usability */ 1437 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 1438 return 0; 1439 1440 if(entry->apic_id >= NAPICID) 1441 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1); 1442 /* check for BSP flag */ 1443 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 1444 boot_cpu_id = entry->apic_id; 1445 CPU_TO_ID(0) = entry->apic_id; 1446 ID_TO_CPU(entry->apic_id) = 0; 1447 return 0; /* its already been counted */ 1448 } 1449 1450 /* add another AP to list, if less than max number of CPUs */ 1451 else if (cpu < MAXCPU) { 1452 CPU_TO_ID(cpu) = entry->apic_id; 1453 ID_TO_CPU(entry->apic_id) = cpu; 1454 return 1; 1455 } 1456 1457 return 0; 1458} 1459 1460 1461static int 1462bus_entry(bus_entry_ptr entry, int bus) 1463{ 1464 int x; 1465 char c, name[8]; 1466 1467 /* encode the name into an index */ 1468 for (x = 0; x < 6; ++x) { 1469 if ((c = entry->bus_type[x]) == ' ') 1470 break; 1471 name[x] = c; 1472 } 1473 name[x] = '\0'; 1474 1475 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1476 panic("unknown bus type: '%s'", name); 1477 1478 bus_data[bus].bus_id = entry->bus_id; 1479 bus_data[bus].bus_type = x; 1480 1481 return 1; 1482} 1483 1484 1485static int 1486io_apic_entry(io_apic_entry_ptr entry, int apic) 1487{ 1488 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1489 return 0; 1490 1491 IO_TO_ID(apic) = entry->apic_id; 1492 if (entry->apic_id < NAPICID) 1493 ID_TO_IO(entry->apic_id) = apic; 1494 1495 return 1; 1496} 1497 1498 1499static int 1500lookup_bus_type(char *name) 1501{ 1502 int x; 1503 1504 for (x = 0; x < MAX_BUSTYPE; ++x) 1505 if (strcmp(bus_type_table[x].name, name) == 0) 1506 return bus_type_table[x].type; 1507 1508 return UNKNOWN_BUSTYPE; 1509} 1510 1511 1512static int 1513int_entry(int_entry_ptr entry, int intr) 1514{ 1515 int apic; 1516 1517 io_apic_ints[intr].int_type = entry->int_type; 1518 io_apic_ints[intr].int_flags = entry->int_flags; 1519 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1520 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1521 if (entry->dst_apic_id == 255) { 1522 /* This signal goes to all IO APICS. Select an IO APIC 1523 with sufficient number of interrupt pins */ 1524 for (apic = 0; apic < mp_napics; apic++) 1525 if (((io_apic_read(apic, IOAPIC_VER) & 1526 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 1527 entry->dst_apic_int) 1528 break; 1529 if (apic < mp_napics) 1530 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic); 1531 else 1532 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1533 } else 1534 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1535 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1536 1537 return 1; 1538} 1539 1540 1541static int 1542apic_int_is_bus_type(int intr, int bus_type) 1543{ 1544 int bus; 1545 1546 for (bus = 0; bus < mp_nbusses; ++bus) 1547 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1548 && ((int) bus_data[bus].bus_type == bus_type)) 1549 return 1; 1550 1551 return 0; 1552} 1553 1554 1555/* 1556 * Given a traditional ISA INT mask, return an APIC mask. 1557 */ 1558u_int 1559isa_apic_mask(u_int isa_mask) 1560{ 1561 int isa_irq; 1562 int apic_pin; 1563 1564#if defined(SKIP_IRQ15_REDIRECT) 1565 if (isa_mask == (1 << 15)) { 1566 printf("skipping ISA IRQ15 redirect\n"); 1567 return isa_mask; 1568 } 1569#endif /* SKIP_IRQ15_REDIRECT */ 1570 1571 isa_irq = ffs(isa_mask); /* find its bit position */ 1572 if (isa_irq == 0) /* doesn't exist */ 1573 return 0; 1574 --isa_irq; /* make it zero based */ 1575 1576 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */ 1577 if (apic_pin == -1) 1578 return 0; 1579 1580 return (1 << apic_pin); /* convert pin# to a mask */ 1581} 1582 1583 1584/* 1585 * Determine which APIC pin an ISA/EISA INT is attached to. 1586 */ 1587#define INTTYPE(I) (io_apic_ints[(I)].int_type) 1588#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1589#define INTIRQ(I) (io_apic_ints[(I)].int_vector) 1590#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id)) 1591 1592#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1593int 1594isa_apic_irq(int isa_irq) 1595{ 1596 int intr; 1597 1598 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1599 if (INTTYPE(intr) == 0) { /* standard INT */ 1600 if (SRCBUSIRQ(intr) == isa_irq) { 1601 if (apic_int_is_bus_type(intr, ISA) || 1602 apic_int_is_bus_type(intr, EISA)) { 1603 if (INTIRQ(intr) == 0xff) 1604 return -1; /* unassigned */ 1605 return INTIRQ(intr); /* found */ 1606 } 1607 } 1608 } 1609 } 1610 return -1; /* NOT found */ 1611} 1612 1613 1614/* 1615 * Determine which APIC pin a PCI INT is attached to. 1616 */ 1617#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1618#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1619#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1620int 1621pci_apic_irq(int pciBus, int pciDevice, int pciInt) 1622{ 1623 int intr; 1624 1625 --pciInt; /* zero based */ 1626 1627 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1628 if ((INTTYPE(intr) == 0) /* standard INT */ 1629 && (SRCBUSID(intr) == pciBus) 1630 && (SRCBUSDEVICE(intr) == pciDevice) 1631 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1632 if (apic_int_is_bus_type(intr, PCI)) { 1633 if (INTIRQ(intr) == 0xff) 1634 allocate_apic_irq(intr); 1635 if (INTIRQ(intr) == 0xff) 1636 return -1; /* unassigned */ 1637 return INTIRQ(intr); /* exact match */ 1638 } 1639 1640 return -1; /* NOT found */ 1641} 1642 1643int 1644next_apic_irq(int irq) 1645{ 1646 int intr, ointr; 1647 int bus, bustype; 1648 1649 bus = 0; 1650 bustype = 0; 1651 for (intr = 0; intr < nintrs; intr++) { 1652 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0) 1653 continue; 1654 bus = SRCBUSID(intr); 1655 bustype = apic_bus_type(bus); 1656 if (bustype != ISA && 1657 bustype != EISA && 1658 bustype != PCI) 1659 continue; 1660 break; 1661 } 1662 if (intr >= nintrs) { 1663 return -1; 1664 } 1665 for (ointr = intr + 1; ointr < nintrs; ointr++) { 1666 if (INTTYPE(ointr) != 0) 1667 continue; 1668 if (bus != SRCBUSID(ointr)) 1669 continue; 1670 if (bustype == PCI) { 1671 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr)) 1672 continue; 1673 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr)) 1674 continue; 1675 } 1676 if (bustype == ISA || bustype == EISA) { 1677 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr)) 1678 continue; 1679 } 1680 if (INTPIN(intr) == INTPIN(ointr)) 1681 continue; 1682 break; 1683 } 1684 if (ointr >= nintrs) { 1685 return -1; 1686 } 1687 return INTIRQ(ointr); 1688} 1689#undef SRCBUSLINE 1690#undef SRCBUSDEVICE 1691#undef SRCBUSID 1692#undef SRCBUSIRQ 1693 1694#undef INTPIN 1695#undef INTIRQ 1696#undef INTAPIC 1697#undef INTTYPE 1698 1699 1700/* 1701 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1702 * 1703 * XXX FIXME: 1704 * Exactly what this means is unclear at this point. It is a solution 1705 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1706 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1707 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1708 * option. 1709 */ 1710int 1711undirect_isa_irq(int rirq) 1712{ 1713#if defined(READY) 1714 if (bootverbose) 1715 printf("Freeing redirected ISA irq %d.\n", rirq); 1716 /** FIXME: tickle the MB redirector chip */ 1717 return -1; 1718#else 1719 if (bootverbose) 1720 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1721 return 0; 1722#endif /* READY */ 1723} 1724 1725 1726/* 1727 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1728 */ 1729int 1730undirect_pci_irq(int rirq) 1731{ 1732#if defined(READY) 1733 if (bootverbose) 1734 printf("Freeing redirected PCI irq %d.\n", rirq); 1735 1736 /** FIXME: tickle the MB redirector chip */ 1737 return -1; 1738#else 1739 if (bootverbose) 1740 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1741 rirq); 1742 return 0; 1743#endif /* READY */ 1744} 1745 1746 1747/* 1748 * given a bus ID, return: 1749 * the bus type if found 1750 * -1 if NOT found 1751 */ 1752int 1753apic_bus_type(int id) 1754{ 1755 int x; 1756 1757 for (x = 0; x < mp_nbusses; ++x) 1758 if (bus_data[x].bus_id == id) 1759 return bus_data[x].bus_type; 1760 1761 return -1; 1762} 1763 1764 1765/* 1766 * given a LOGICAL APIC# and pin#, return: 1767 * the associated src bus ID if found 1768 * -1 if NOT found 1769 */ 1770int 1771apic_src_bus_id(int apic, int pin) 1772{ 1773 int x; 1774 1775 /* search each of the possible INTerrupt sources */ 1776 for (x = 0; x < nintrs; ++x) 1777 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1778 (pin == io_apic_ints[x].dst_apic_int)) 1779 return (io_apic_ints[x].src_bus_id); 1780 1781 return -1; /* NOT found */ 1782} 1783 1784 1785/* 1786 * given a LOGICAL APIC# and pin#, return: 1787 * the associated src bus IRQ if found 1788 * -1 if NOT found 1789 */ 1790int 1791apic_src_bus_irq(int apic, int pin) 1792{ 1793 int x; 1794 1795 for (x = 0; x < nintrs; x++) 1796 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1797 (pin == io_apic_ints[x].dst_apic_int)) 1798 return (io_apic_ints[x].src_bus_irq); 1799 1800 return -1; /* NOT found */ 1801} 1802 1803 1804/* 1805 * given a LOGICAL APIC# and pin#, return: 1806 * the associated INTerrupt type if found 1807 * -1 if NOT found 1808 */ 1809int 1810apic_int_type(int apic, int pin) 1811{ 1812 int x; 1813 1814 /* search each of the possible INTerrupt sources */ 1815 for (x = 0; x < nintrs; ++x) 1816 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1817 (pin == io_apic_ints[x].dst_apic_int)) 1818 return (io_apic_ints[x].int_type); 1819 1820 return -1; /* NOT found */ 1821} 1822 1823int 1824apic_irq(int apic, int pin) 1825{ 1826 int x; 1827 int res; 1828 1829 for (x = 0; x < nintrs; ++x) 1830 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1831 (pin == io_apic_ints[x].dst_apic_int)) { 1832 res = io_apic_ints[x].int_vector; 1833 if (res == 0xff) 1834 return -1; 1835 if (apic != int_to_apicintpin[res].ioapic) 1836 panic("apic_irq: inconsistent table"); 1837 if (pin != int_to_apicintpin[res].int_pin) 1838 panic("apic_irq inconsistent table (2)"); 1839 return res; 1840 } 1841 return -1; 1842} 1843 1844 1845/* 1846 * given a LOGICAL APIC# and pin#, return: 1847 * the associated trigger mode if found 1848 * -1 if NOT found 1849 */ 1850int 1851apic_trigger(int apic, int pin) 1852{ 1853 int x; 1854 1855 /* search each of the possible INTerrupt sources */ 1856 for (x = 0; x < nintrs; ++x) 1857 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1858 (pin == io_apic_ints[x].dst_apic_int)) 1859 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1860 1861 return -1; /* NOT found */ 1862} 1863 1864 1865/* 1866 * given a LOGICAL APIC# and pin#, return: 1867 * the associated 'active' level if found 1868 * -1 if NOT found 1869 */ 1870int 1871apic_polarity(int apic, int pin) 1872{ 1873 int x; 1874 1875 /* search each of the possible INTerrupt sources */ 1876 for (x = 0; x < nintrs; ++x) 1877 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1878 (pin == io_apic_ints[x].dst_apic_int)) 1879 return (io_apic_ints[x].int_flags & 0x03); 1880 1881 return -1; /* NOT found */ 1882} 1883 1884 1885/* 1886 * set data according to MP defaults 1887 * FIXME: probably not complete yet... 1888 */ 1889static void 1890default_mp_table(int type) 1891{ 1892 int ap_cpu_id; 1893#if defined(APIC_IO) 1894 int io_apic_id; 1895 int pin; 1896#endif /* APIC_IO */ 1897 1898#if 0 1899 printf(" MP default config type: %d\n", type); 1900 switch (type) { 1901 case 1: 1902 printf(" bus: ISA, APIC: 82489DX\n"); 1903 break; 1904 case 2: 1905 printf(" bus: EISA, APIC: 82489DX\n"); 1906 break; 1907 case 3: 1908 printf(" bus: EISA, APIC: 82489DX\n"); 1909 break; 1910 case 4: 1911 printf(" bus: MCA, APIC: 82489DX\n"); 1912 break; 1913 case 5: 1914 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1915 break; 1916 case 6: 1917 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1918 break; 1919 case 7: 1920 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1921 break; 1922 default: 1923 printf(" future type\n"); 1924 break; 1925 /* NOTREACHED */ 1926 } 1927#endif /* 0 */ 1928 1929 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1930 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1931 1932 /* BSP */ 1933 CPU_TO_ID(0) = boot_cpu_id; 1934 ID_TO_CPU(boot_cpu_id) = 0; 1935 1936 /* one and only AP */ 1937 CPU_TO_ID(1) = ap_cpu_id; 1938 ID_TO_CPU(ap_cpu_id) = 1; 1939 1940#if defined(APIC_IO) 1941 /* one and only IO APIC */ 1942 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1943 1944 /* 1945 * sanity check, refer to MP spec section 3.6.6, last paragraph 1946 * necessary as some hardware isn't properly setting up the IO APIC 1947 */ 1948#if defined(REALLY_ANAL_IOAPICID_VALUE) 1949 if (io_apic_id != 2) { 1950#else 1951 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1952#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1953 io_apic_set_id(0, 2); 1954 io_apic_id = 2; 1955 } 1956 IO_TO_ID(0) = io_apic_id; 1957 ID_TO_IO(io_apic_id) = 0; 1958#endif /* APIC_IO */ 1959 1960 /* fill out bus entries */ 1961 switch (type) { 1962 case 1: 1963 case 2: 1964 case 3: 1965 case 4: 1966 case 5: 1967 case 6: 1968 case 7: 1969 bus_data[0].bus_id = default_data[type - 1][1]; 1970 bus_data[0].bus_type = default_data[type - 1][2]; 1971 bus_data[1].bus_id = default_data[type - 1][3]; 1972 bus_data[1].bus_type = default_data[type - 1][4]; 1973 break; 1974 1975 /* case 4: case 7: MCA NOT supported */ 1976 default: /* illegal/reserved */ 1977 panic("BAD default MP config: %d", type); 1978 /* NOTREACHED */ 1979 } 1980 1981#if defined(APIC_IO) 1982 /* general cases from MP v1.4, table 5-2 */ 1983 for (pin = 0; pin < 16; ++pin) { 1984 io_apic_ints[pin].int_type = 0; 1985 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1986 io_apic_ints[pin].src_bus_id = 0; 1987 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1988 io_apic_ints[pin].dst_apic_id = io_apic_id; 1989 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1990 } 1991 1992 /* special cases from MP v1.4, table 5-2 */ 1993 if (type == 2) { 1994 io_apic_ints[2].int_type = 0xff; /* N/C */ 1995 io_apic_ints[13].int_type = 0xff; /* N/C */ 1996#if !defined(APIC_MIXED_MODE) 1997 /** FIXME: ??? */ 1998 panic("sorry, can't support type 2 default yet"); 1999#endif /* APIC_MIXED_MODE */ 2000 } 2001 else 2002 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 2003 2004 if (type == 7) 2005 io_apic_ints[0].int_type = 0xff; /* N/C */ 2006 else 2007 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 2008#endif /* APIC_IO */ 2009} 2010 2011 2012/* 2013 * start each AP in our list 2014 */ 2015static int 2016start_all_aps(u_int boot_addr) 2017{ 2018 int x, i, pg; 2019 u_char mpbiosreason; 2020 u_long mpbioswarmvec; 2021 struct pcpu *pc; 2022 char *stack; 2023 uintptr_t kptbase; 2024 2025 POSTCODE(START_ALL_APS_POST); 2026 2027 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 2028 2029 /* initialize BSP's local APIC */ 2030 apic_initialize(); 2031 bsp_apic_ready = 1; 2032 2033 /* install the AP 1st level boot code */ 2034 install_ap_tramp(boot_addr); 2035 2036 2037 /* save the current value of the warm-start vector */ 2038 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 2039#ifndef PC98 2040 outb(CMOS_REG, BIOS_RESET); 2041 mpbiosreason = inb(CMOS_DATA); 2042#endif 2043 2044 /* set up temporary P==V mapping for AP boot */ 2045 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 2046 kptbase = (uintptr_t)(void *)KPTphys; 2047 for (x = 0; x < NKPT; x++) 2048 PTD[x] = (pd_entry_t)(PG_V | PG_RW | 2049 ((kptbase + x * PAGE_SIZE) & PG_FRAME)); 2050 invltlb(); 2051 2052 /* start each AP */ 2053 for (x = 1; x <= mp_naps; ++x) { 2054 2055 /* This is a bit verbose, it will go away soon. */ 2056 2057 /* first page of AP's private space */ 2058 pg = x * i386_btop(sizeof(struct privatespace)); 2059 2060 /* allocate a new private data page */ 2061 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE); 2062 2063 /* wire it into the private page table page */ 2064 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc)); 2065 2066 /* allocate and set up an idle stack data page */ 2067 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */ 2068 for (i = 0; i < KSTACK_PAGES; i++) 2069 SMPpt[pg + 1 + i] = (pt_entry_t) 2070 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2071 2072 /* prime data page for it to use */ 2073 pcpu_init(pc, x, sizeof(struct pcpu)); 2074 2075 /* setup a vector to our boot code */ 2076 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 2077 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 2078#ifndef PC98 2079 outb(CMOS_REG, BIOS_RESET); 2080 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 2081#endif 2082 2083 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE]; 2084 bootAP = x; 2085 2086 /* attempt to start the Application Processor */ 2087 CHECK_INIT(99); /* setup checkpoints */ 2088 if (!start_ap(x, boot_addr)) { 2089 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 2090 CHECK_PRINT("trace"); /* show checkpoints */ 2091 /* better panic as the AP may be running loose */ 2092 printf("panic y/n? [y] "); 2093 if (cngetc() != 'n') 2094 panic("bye-bye"); 2095 } 2096 CHECK_PRINT("trace"); /* show checkpoints */ 2097 2098 /* record its version info */ 2099 cpu_apic_versions[x] = cpu_apic_versions[0]; 2100 2101 all_cpus |= (1 << x); /* record AP in CPU map */ 2102 } 2103 2104 /* build our map of 'other' CPUs */ 2105 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2106 2107 /* fill in our (BSP) APIC version */ 2108 cpu_apic_versions[0] = lapic.version; 2109 2110 /* restore the warmstart vector */ 2111 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 2112#ifndef PC98 2113 outb(CMOS_REG, BIOS_RESET); 2114 outb(CMOS_DATA, mpbiosreason); 2115#endif 2116 2117 /* 2118 * Set up the idle context for the BSP. Similar to above except 2119 * that some was done by locore, some by pmap.c and some is implicit 2120 * because the BSP is cpu#0 and the page is initially zero, and also 2121 * because we can refer to variables by name on the BSP.. 2122 */ 2123 2124 /* Allocate and setup BSP idle stack */ 2125 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 2126 for (i = 0; i < KSTACK_PAGES; i++) 2127 SMPpt[1 + i] = (pt_entry_t) 2128 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 2129 2130 for (x = 0; x < NKPT; x++) 2131 PTD[x] = 0; 2132 pmap_set_opt(); 2133 2134 /* number of APs actually started */ 2135 return mp_ncpus - 1; 2136} 2137 2138 2139/* 2140 * load the 1st level AP boot code into base memory. 2141 */ 2142 2143/* targets for relocation */ 2144extern void bigJump(void); 2145extern void bootCodeSeg(void); 2146extern void bootDataSeg(void); 2147extern void MPentry(void); 2148extern u_int MP_GDT; 2149extern u_int mp_gdtbase; 2150 2151static void 2152install_ap_tramp(u_int boot_addr) 2153{ 2154 int x; 2155 int size = *(int *) ((u_long) & bootMP_size); 2156 u_char *src = (u_char *) ((u_long) bootMP); 2157 u_char *dst = (u_char *) boot_addr + KERNBASE; 2158 u_int boot_base = (u_int) bootMP; 2159 u_int8_t *dst8; 2160 u_int16_t *dst16; 2161 u_int32_t *dst32; 2162 2163 POSTCODE(INSTALL_AP_TRAMP_POST); 2164 2165 for (x = 0; x < size; ++x) 2166 *dst++ = *src++; 2167 2168 /* 2169 * modify addresses in code we just moved to basemem. unfortunately we 2170 * need fairly detailed info about mpboot.s for this to work. changes 2171 * to mpboot.s might require changes here. 2172 */ 2173 2174 /* boot code is located in KERNEL space */ 2175 dst = (u_char *) boot_addr + KERNBASE; 2176 2177 /* modify the lgdt arg */ 2178 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 2179 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 2180 2181 /* modify the ljmp target for MPentry() */ 2182 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 2183 *dst32 = ((u_int) MPentry - KERNBASE); 2184 2185 /* modify the target for boot code segment */ 2186 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 2187 dst8 = (u_int8_t *) (dst16 + 1); 2188 *dst16 = (u_int) boot_addr & 0xffff; 2189 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2190 2191 /* modify the target for boot data segment */ 2192 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 2193 dst8 = (u_int8_t *) (dst16 + 1); 2194 *dst16 = (u_int) boot_addr & 0xffff; 2195 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 2196} 2197 2198 2199/* 2200 * this function starts the AP (application processor) identified 2201 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 2202 * to accomplish this. This is necessary because of the nuances 2203 * of the different hardware we might encounter. It ain't pretty, 2204 * but it seems to work. 2205 */ 2206static int 2207start_ap(int logical_cpu, u_int boot_addr) 2208{ 2209 int physical_cpu; 2210 int vector; 2211 int cpus; 2212 u_long icr_lo, icr_hi; 2213 2214 POSTCODE(START_AP_POST); 2215 2216 /* get the PHYSICAL APIC ID# */ 2217 physical_cpu = CPU_TO_ID(logical_cpu); 2218 2219 /* calculate the vector */ 2220 vector = (boot_addr >> 12) & 0xff; 2221 2222 /* used as a watchpoint to signal AP startup */ 2223 cpus = mp_ncpus; 2224 2225 /* 2226 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 2227 * and running the target CPU. OR this INIT IPI might be latched (P5 2228 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 2229 * ignored. 2230 */ 2231 2232 /* setup the address for the target AP */ 2233 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 2234 icr_hi |= (physical_cpu << 24); 2235 lapic.icr_hi = icr_hi; 2236 2237 /* do an INIT IPI: assert RESET */ 2238 icr_lo = lapic.icr_lo & 0xfff00000; 2239 lapic.icr_lo = icr_lo | 0x0000c500; 2240 2241 /* wait for pending status end */ 2242 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2243 /* spin */ ; 2244 2245 /* do an INIT IPI: deassert RESET */ 2246 lapic.icr_lo = icr_lo | 0x00008500; 2247 2248 /* wait for pending status end */ 2249 u_sleep(10000); /* wait ~10mS */ 2250 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2251 /* spin */ ; 2252 2253 /* 2254 * next we do a STARTUP IPI: the previous INIT IPI might still be 2255 * latched, (P5 bug) this 1st STARTUP would then terminate 2256 * immediately, and the previously started INIT IPI would continue. OR 2257 * the previous INIT IPI has already run. and this STARTUP IPI will 2258 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 2259 * will run. 2260 */ 2261 2262 /* do a STARTUP IPI */ 2263 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2264 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2265 /* spin */ ; 2266 u_sleep(200); /* wait ~200uS */ 2267 2268 /* 2269 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 2270 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 2271 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 2272 * recognized after hardware RESET or INIT IPI. 2273 */ 2274 2275 lapic.icr_lo = icr_lo | 0x00000600 | vector; 2276 while (lapic.icr_lo & APIC_DELSTAT_MASK) 2277 /* spin */ ; 2278 u_sleep(200); /* wait ~200uS */ 2279 2280 /* wait for it to start */ 2281 set_apic_timer(5000000);/* == 5 seconds */ 2282 while (read_apic_timer()) 2283 if (mp_ncpus > cpus) 2284 return 1; /* return SUCCESS */ 2285 2286 return 0; /* return FAILURE */ 2287} 2288 2289#if defined(APIC_IO) 2290 2291#ifdef COUNT_XINVLTLB_HITS 2292u_int xhits_gbl[MAXCPU]; 2293u_int xhits_pg[MAXCPU]; 2294u_int xhits_rng[MAXCPU]; 2295SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 2296SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 2297 sizeof(xhits_gbl), "IU", ""); 2298SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 2299 sizeof(xhits_pg), "IU", ""); 2300SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 2301 sizeof(xhits_rng), "IU", ""); 2302 2303u_int ipi_global; 2304u_int ipi_page; 2305u_int ipi_range; 2306u_int ipi_range_size; 2307SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 2308SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 2309SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 2310SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 2311 0, ""); 2312 2313u_int ipi_masked_global; 2314u_int ipi_masked_page; 2315u_int ipi_masked_range; 2316u_int ipi_masked_range_size; 2317SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 2318 &ipi_masked_global, 0, ""); 2319SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 2320 &ipi_masked_page, 0, ""); 2321SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 2322 &ipi_masked_range, 0, ""); 2323SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 2324 &ipi_masked_range_size, 0, ""); 2325#endif 2326 2327/* 2328 * Flush the TLB on all other CPU's 2329 */ 2330static void 2331smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2332{ 2333 u_int ncpu; 2334 register_t eflags; 2335 2336 ncpu = mp_ncpus - 1; /* does not shootdown self */ 2337 if (ncpu < 1) 2338 return; /* no other cpus */ 2339 eflags = read_eflags(); 2340 if ((eflags & PSL_I) == 0) 2341 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled"); 2342 mtx_lock_spin(&smp_tlb_mtx); 2343 smp_tlb_addr1 = addr1; 2344 smp_tlb_addr2 = addr2; 2345 atomic_store_rel_int(&smp_tlb_wait, 0); 2346 ipi_all_but_self(vector); 2347 while (smp_tlb_wait < ncpu) 2348 ia32_pause(); 2349 mtx_unlock_spin(&smp_tlb_mtx); 2350} 2351 2352/* 2353 * This is about as magic as it gets. fortune(1) has got similar code 2354 * for reversing bits in a word. Who thinks up this stuff?? 2355 * 2356 * Yes, it does appear to be consistently faster than: 2357 * while (i = ffs(m)) { 2358 * m >>= i; 2359 * bits++; 2360 * } 2361 * and 2362 * while (lsb = (m & -m)) { // This is magic too 2363 * m &= ~lsb; // or: m ^= lsb 2364 * bits++; 2365 * } 2366 * Both of these latter forms do some very strange things on gcc-3.1 with 2367 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2. 2368 * There is probably an SSE or MMX popcnt instruction. 2369 * 2370 * I wonder if this should be in libkern? 2371 * 2372 * XXX Stop the presses! Another one: 2373 * static __inline u_int32_t 2374 * popcnt1(u_int32_t v) 2375 * { 2376 * v -= ((v >> 1) & 0x55555555); 2377 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333); 2378 * v = (v + (v >> 4)) & 0x0F0F0F0F; 2379 * return (v * 0x01010101) >> 24; 2380 * } 2381 * The downside is that it has a multiply. With a pentium3 with 2382 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use 2383 * an imull, and in that case it is faster. In most other cases 2384 * it appears slightly slower. 2385 */ 2386static __inline u_int32_t 2387popcnt(u_int32_t m) 2388{ 2389 2390 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1); 2391 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2); 2392 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4); 2393 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8); 2394 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16); 2395 return m; 2396} 2397 2398static void 2399smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 2400{ 2401 int ncpu, othercpus; 2402 register_t eflags; 2403 2404 othercpus = mp_ncpus - 1; 2405 if (mask == (u_int)-1) { 2406 ncpu = othercpus; 2407 if (ncpu < 1) 2408 return; 2409 } else { 2410 /* XXX there should be a pcpu self mask */ 2411 mask &= ~(1 << PCPU_GET(cpuid)); 2412 if (mask == 0) 2413 return; 2414 ncpu = popcnt(mask); 2415 if (ncpu > othercpus) { 2416 /* XXX this should be a panic offence */ 2417 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 2418 ncpu, othercpus); 2419 ncpu = othercpus; 2420 } 2421 /* XXX should be a panic, implied by mask == 0 above */ 2422 if (ncpu < 1) 2423 return; 2424 } 2425 eflags = read_eflags(); 2426 if ((eflags & PSL_I) == 0) 2427 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled"); 2428 mtx_lock_spin(&smp_tlb_mtx); 2429 smp_tlb_addr1 = addr1; 2430 smp_tlb_addr2 = addr2; 2431 atomic_store_rel_int(&smp_tlb_wait, 0); 2432 if (mask == (u_int)-1) 2433 ipi_all_but_self(vector); 2434 else 2435 ipi_selected(mask, vector); 2436 while (smp_tlb_wait < ncpu) 2437 ia32_pause(); 2438 mtx_unlock_spin(&smp_tlb_mtx); 2439} 2440#endif 2441 2442void 2443smp_invltlb(void) 2444{ 2445#if defined(APIC_IO) 2446 if (smp_started) { 2447 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 2448#ifdef COUNT_XINVLTLB_HITS 2449 ipi_global++; 2450#endif 2451 } 2452#endif /* APIC_IO */ 2453} 2454 2455void 2456smp_invlpg(vm_offset_t addr) 2457{ 2458#if defined(APIC_IO) 2459 if (smp_started) { 2460 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 2461#ifdef COUNT_XINVLTLB_HITS 2462 ipi_page++; 2463#endif 2464 } 2465#endif /* APIC_IO */ 2466} 2467 2468void 2469smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 2470{ 2471#if defined(APIC_IO) 2472 if (smp_started) { 2473 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 2474#ifdef COUNT_XINVLTLB_HITS 2475 ipi_range++; 2476 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 2477#endif 2478 } 2479#endif /* APIC_IO */ 2480} 2481 2482void 2483smp_masked_invltlb(u_int mask) 2484{ 2485#if defined(APIC_IO) 2486 if (smp_started) { 2487 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 2488#ifdef COUNT_XINVLTLB_HITS 2489 ipi_masked_global++; 2490#endif 2491 } 2492#endif /* APIC_IO */ 2493} 2494 2495void 2496smp_masked_invlpg(u_int mask, vm_offset_t addr) 2497{ 2498#if defined(APIC_IO) 2499 if (smp_started) { 2500 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 2501#ifdef COUNT_XINVLTLB_HITS 2502 ipi_masked_page++; 2503#endif 2504 } 2505#endif /* APIC_IO */ 2506} 2507 2508void 2509smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2) 2510{ 2511#if defined(APIC_IO) 2512 if (smp_started) { 2513 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 2514#ifdef COUNT_XINVLTLB_HITS 2515 ipi_masked_range++; 2516 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 2517#endif 2518 } 2519#endif /* APIC_IO */ 2520} 2521 2522 2523/* 2524 * This is called once the rest of the system is up and running and we're 2525 * ready to let the AP's out of the pen. 2526 */ 2527void 2528ap_init(void) 2529{ 2530 u_int apic_id; 2531 2532 /* spin until all the AP's are ready */ 2533 while (!aps_ready) 2534 ia32_pause(); 2535 2536 /* BSP may have changed PTD while we were waiting */ 2537 invltlb(); 2538 2539#if defined(I586_CPU) && !defined(NO_F00F_HACK) 2540 lidt(&r_idt); 2541#endif 2542 2543 /* set up CPU registers and state */ 2544 cpu_setregs(); 2545 2546 /* set up FPU state on the AP */ 2547 npxinit(__INITIAL_NPXCW__); 2548 2549 /* set up SSE registers */ 2550 enable_sse(); 2551 2552 /* A quick check from sanity claus */ 2553 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 2554 if (PCPU_GET(cpuid) != apic_id) { 2555 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 2556 printf("SMP: apic_id = %d\n", apic_id); 2557 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 2558 panic("cpuid mismatch! boom!!"); 2559 } 2560 2561 /* Init local apic for irq's */ 2562 apic_initialize(); 2563 2564 /* Set memory range attributes for this CPU to match the BSP */ 2565 mem_range_AP_init(); 2566 2567 mtx_lock_spin(&ap_boot_mtx); 2568 2569 smp_cpus++; 2570 2571 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 2572 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 2573 2574 /* Build our map of 'other' CPUs. */ 2575 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 2576 2577 if (bootverbose) 2578 apic_dump("ap_init()"); 2579 2580 if (smp_cpus == mp_ncpus) { 2581 /* enable IPI's, tlb shootdown, freezes etc */ 2582 atomic_store_rel_int(&smp_started, 1); 2583 smp_active = 1; /* historic */ 2584 } 2585 2586 mtx_unlock_spin(&ap_boot_mtx); 2587 2588 /* wait until all the AP's are up */ 2589 while (smp_started == 0) 2590 ia32_pause(); 2591 2592 /* ok, now grab sched_lock and enter the scheduler */ 2593 mtx_lock_spin(&sched_lock); 2594 2595 binuptime(PCPU_PTR(switchtime)); 2596 PCPU_SET(switchticks, ticks); 2597 2598 cpu_throw(); /* doesn't return */ 2599 2600 panic("scheduler returned us to %s", __func__); 2601} 2602 2603/* 2604 * For statclock, we send an IPI to all CPU's to have them call this 2605 * function. 2606 * 2607 * WARNING! unpend() will call statclock() directly and skip this 2608 * routine. 2609 */ 2610void 2611forwarded_statclock(struct clockframe frame) 2612{ 2613 2614 if (profprocs != 0) 2615 profclock(&frame); 2616 if (pscnt == psdiv) 2617 statclock(&frame); 2618} 2619 2620void 2621forward_statclock(void) 2622{ 2623 int map; 2624 2625 CTR0(KTR_SMP, "forward_statclock"); 2626 2627 if (!smp_started || cold || panicstr) 2628 return; 2629 2630 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2631 if (map != 0) 2632 ipi_selected(map, IPI_STATCLOCK); 2633} 2634 2635/* 2636 * For each hardclock(), we send an IPI to all other CPU's to have them 2637 * execute this function. It would be nice to reduce contention on 2638 * sched_lock if we could simply peek at the CPU to determine the user/kernel 2639 * state and call hardclock_process() on the CPU receiving the clock interrupt 2640 * and then just use a simple IPI to handle any ast's if needed. 2641 * 2642 * WARNING! unpend() will call hardclock_process() directly and skip this 2643 * routine. 2644 */ 2645void 2646forwarded_hardclock(struct clockframe frame) 2647{ 2648 2649 hardclock_process(&frame); 2650} 2651 2652void 2653forward_hardclock(void) 2654{ 2655 u_int map; 2656 2657 CTR0(KTR_SMP, "forward_hardclock"); 2658 2659 if (!smp_started || cold || panicstr) 2660 return; 2661 2662 map = PCPU_GET(other_cpus) & ~stopped_cpus ; 2663 if (map != 0) 2664 ipi_selected(map, IPI_HARDCLOCK); 2665} 2666 2667#ifdef APIC_INTR_REORDER 2668/* 2669 * Maintain mapping from softintr vector to isr bit in local apic. 2670 */ 2671void 2672set_lapic_isrloc(int intr, int vector) 2673{ 2674 if (intr < 0 || intr > 32) 2675 panic("set_apic_isrloc: bad intr argument: %d",intr); 2676 if (vector < ICU_OFFSET || vector > 255) 2677 panic("set_apic_isrloc: bad vector argument: %d",vector); 2678 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2); 2679 apic_isrbit_location[intr].bit = (1<<(vector & 31)); 2680} 2681#endif 2682 2683/* 2684 * send an IPI to a set of cpus. 2685 */ 2686void 2687ipi_selected(u_int32_t cpus, u_int ipi) 2688{ 2689 2690 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 2691 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED); 2692} 2693 2694/* 2695 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself 2696 */ 2697void 2698ipi_all(u_int ipi) 2699{ 2700 2701 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2702 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED); 2703} 2704 2705/* 2706 * send an IPI to all CPUs EXCEPT myself 2707 */ 2708void 2709ipi_all_but_self(u_int ipi) 2710{ 2711 2712 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2713 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED); 2714} 2715 2716/* 2717 * send an IPI to myself 2718 */ 2719void 2720ipi_self(u_int ipi) 2721{ 2722 2723 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 2724 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED); 2725} 2726 2727static void 2728release_aps(void *dummy __unused) 2729{ 2730 2731 mtx_lock_spin(&sched_lock); 2732 atomic_store_rel_int(&aps_ready, 1); 2733 while (smp_started == 0) 2734 ia32_pause(); 2735 mtx_unlock_spin(&sched_lock); 2736} 2737 2738SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 2739