machdep.c revision 263140
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 263140 2014-03-14 02:58:48Z glebius $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_isa.h" 51#include "opt_kstack_pages.h" 52#include "opt_maxmem.h" 53#include "opt_mp_watchdog.h" 54#include "opt_perfmon.h" 55#include "opt_platform.h" 56#include "opt_sched.h" 57 58#include <sys/param.h> 59#include <sys/proc.h> 60#include <sys/systm.h> 61#include <sys/bio.h> 62#include <sys/buf.h> 63#include <sys/bus.h> 64#include <sys/callout.h> 65#include <sys/cons.h> 66#include <sys/cpu.h> 67#include <sys/eventhandler.h> 68#include <sys/exec.h> 69#include <sys/imgact.h> 70#include <sys/kdb.h> 71#include <sys/kernel.h> 72#include <sys/ktr.h> 73#include <sys/linker.h> 74#include <sys/lock.h> 75#include <sys/malloc.h> 76#include <sys/memrange.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/rwlock.h> 83#include <sys/sched.h> 84#include <sys/signalvar.h> 85#ifdef SMP 86#include <sys/smp.h> 87#endif 88#include <sys/syscallsubr.h> 89#include <sys/sysctl.h> 90#include <sys/sysent.h> 91#include <sys/sysproto.h> 92#include <sys/ucontext.h> 93#include <sys/vmmeter.h> 94 95#include <vm/vm.h> 96#include <vm/vm_extern.h> 97#include <vm/vm_kern.h> 98#include <vm/vm_page.h> 99#include <vm/vm_map.h> 100#include <vm/vm_object.h> 101#include <vm/vm_pager.h> 102#include <vm/vm_param.h> 103 104#ifdef DDB 105#ifndef KDB 106#error KDB must be enabled in order for DDB to work! 107#endif 108#include <ddb/ddb.h> 109#include <ddb/db_sym.h> 110#endif 111 112#include <net/netisr.h> 113 114#include <machine/clock.h> 115#include <machine/cpu.h> 116#include <machine/cputypes.h> 117#include <machine/intr_machdep.h> 118#include <x86/mca.h> 119#include <machine/md_var.h> 120#include <machine/metadata.h> 121#include <machine/mp_watchdog.h> 122#include <machine/pc/bios.h> 123#include <machine/pcb.h> 124#include <machine/proc.h> 125#include <machine/reg.h> 126#include <machine/sigframe.h> 127#include <machine/specialreg.h> 128#ifdef PERFMON 129#include <machine/perfmon.h> 130#endif 131#include <machine/tss.h> 132#ifdef SMP 133#include <machine/smp.h> 134#endif 135#ifdef FDT 136#include <x86/fdt.h> 137#endif 138 139#ifdef DEV_ATPIC 140#include <x86/isa/icu.h> 141#else 142#include <x86/apicvar.h> 143#endif 144 145#include <isa/isareg.h> 146#include <isa/rtc.h> 147#include <x86/init.h> 148 149/* Sanity check for __curthread() */ 150CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 151 152extern u_int64_t hammer_time(u_int64_t, u_int64_t); 153 154extern void printcpuinfo(void); /* XXX header file */ 155extern void identify_cpu(void); 156extern void panicifcpuunsupported(void); 157 158#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 159#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 160 161static void cpu_startup(void *); 162static void get_fpcontext(struct thread *td, mcontext_t *mcp, 163 char *xfpusave, size_t xfpusave_len); 164static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 165 char *xfpustate, size_t xfpustate_len); 166SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 167 168/* Preload data parse function */ 169static caddr_t native_parse_preload_data(u_int64_t); 170 171/* Native function to fetch and parse the e820 map */ 172static void native_parse_memmap(caddr_t, vm_paddr_t *, int *); 173 174/* Default init_ops implementation. */ 175struct init_ops init_ops = { 176 .parse_preload_data = native_parse_preload_data, 177 .early_clock_source_init = i8254_init, 178 .early_delay = i8254_delay, 179 .parse_memmap = native_parse_memmap, 180#ifdef SMP 181 .mp_bootaddress = mp_bootaddress, 182 .start_all_aps = native_start_all_aps, 183#endif 184}; 185 186/* 187 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 188 * the physical address at which the kernel is loaded. 189 */ 190extern char kernphys[]; 191#ifdef DDB 192extern vm_offset_t ksym_start, ksym_end; 193#endif 194 195struct msgbuf *msgbufp; 196 197/* Intel ICH registers */ 198#define ICH_PMBASE 0x400 199#define ICH_SMI_EN ICH_PMBASE + 0x30 200 201int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 202 203int cold = 1; 204 205long Maxmem = 0; 206long realmem = 0; 207 208/* 209 * The number of PHYSMAP entries must be one less than the number of 210 * PHYSSEG entries because the PHYSMAP entry that spans the largest 211 * physical address that is accessible by ISA DMA is split into two 212 * PHYSSEG entries. 213 */ 214#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 215 216vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 217vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 218 219/* must be 2 less so 0 0 can signal end of chunks */ 220#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 221#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 222 223struct kva_md_info kmi; 224 225static struct trapframe proc0_tf; 226struct region_descriptor r_gdt, r_idt; 227 228struct pcpu __pcpu[MAXCPU]; 229 230struct mtx icu_lock; 231 232struct mem_range_softc mem_range_softc; 233 234struct mtx dt_lock; /* lock for GDT and LDT */ 235 236void (*vmm_resume_p)(void); 237 238static void 239cpu_startup(dummy) 240 void *dummy; 241{ 242 uintmax_t memsize; 243 char *sysenv; 244 245 /* 246 * On MacBooks, we need to disallow the legacy USB circuit to 247 * generate an SMI# because this can cause several problems, 248 * namely: incorrect CPU frequency detection and failure to 249 * start the APs. 250 * We do this by disabling a bit in the SMI_EN (SMI Control and 251 * Enable register) of the Intel ICH LPC Interface Bridge. 252 */ 253 sysenv = getenv("smbios.system.product"); 254 if (sysenv != NULL) { 255 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 256 strncmp(sysenv, "MacBook3,1", 10) == 0 || 257 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 258 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 259 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 260 strncmp(sysenv, "Macmini1,1", 10) == 0) { 261 if (bootverbose) 262 printf("Disabling LEGACY_USB_EN bit on " 263 "Intel ICH.\n"); 264 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 265 } 266 freeenv(sysenv); 267 } 268 269 /* 270 * Good {morning,afternoon,evening,night}. 271 */ 272 startrtclock(); 273 printcpuinfo(); 274 panicifcpuunsupported(); 275#ifdef PERFMON 276 perfmon_init(); 277#endif 278 279 /* 280 * Display physical memory if SMBIOS reports reasonable amount. 281 */ 282 memsize = 0; 283 sysenv = getenv("smbios.memory.enabled"); 284 if (sysenv != NULL) { 285 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 286 freeenv(sysenv); 287 } 288 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 289 memsize = ptoa((uintmax_t)Maxmem); 290 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 291 realmem = atop(memsize); 292 293 /* 294 * Display any holes after the first chunk of extended memory. 295 */ 296 if (bootverbose) { 297 int indx; 298 299 printf("Physical memory chunk(s):\n"); 300 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 301 vm_paddr_t size; 302 303 size = phys_avail[indx + 1] - phys_avail[indx]; 304 printf( 305 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 306 (uintmax_t)phys_avail[indx], 307 (uintmax_t)phys_avail[indx + 1] - 1, 308 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 309 } 310 } 311 312 vm_ksubmap_init(&kmi); 313 314 printf("avail memory = %ju (%ju MB)\n", 315 ptoa((uintmax_t)cnt.v_free_count), 316 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 317 318 /* 319 * Set up buffers, so they can be used to read disk labels. 320 */ 321 bufinit(); 322 vm_pager_bufferinit(); 323 324 cpu_setregs(); 325} 326 327/* 328 * Send an interrupt to process. 329 * 330 * Stack is set up to allow sigcode stored 331 * at top to call routine, followed by call 332 * to sigreturn routine below. After sigreturn 333 * resets the signal mask, the stack, and the 334 * frame pointer, it returns to the user 335 * specified pc, psl. 336 */ 337void 338sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 339{ 340 struct sigframe sf, *sfp; 341 struct pcb *pcb; 342 struct proc *p; 343 struct thread *td; 344 struct sigacts *psp; 345 char *sp; 346 struct trapframe *regs; 347 char *xfpusave; 348 size_t xfpusave_len; 349 int sig; 350 int oonstack; 351 352 td = curthread; 353 pcb = td->td_pcb; 354 p = td->td_proc; 355 PROC_LOCK_ASSERT(p, MA_OWNED); 356 sig = ksi->ksi_signo; 357 psp = p->p_sigacts; 358 mtx_assert(&psp->ps_mtx, MA_OWNED); 359 regs = td->td_frame; 360 oonstack = sigonstack(regs->tf_rsp); 361 362 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 363 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 364 xfpusave = __builtin_alloca(xfpusave_len); 365 } else { 366 xfpusave_len = 0; 367 xfpusave = NULL; 368 } 369 370 /* Save user context. */ 371 bzero(&sf, sizeof(sf)); 372 sf.sf_uc.uc_sigmask = *mask; 373 sf.sf_uc.uc_stack = td->td_sigstk; 374 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 375 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 376 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 377 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 378 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 379 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 380 fpstate_drop(td); 381 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 382 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 383 bzero(sf.sf_uc.uc_mcontext.mc_spare, 384 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 385 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 386 387 /* Allocate space for the signal handler context. */ 388 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 389 SIGISMEMBER(psp->ps_sigonstack, sig)) { 390 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 391#if defined(COMPAT_43) 392 td->td_sigstk.ss_flags |= SS_ONSTACK; 393#endif 394 } else 395 sp = (char *)regs->tf_rsp - 128; 396 if (xfpusave != NULL) { 397 sp -= xfpusave_len; 398 sp = (char *)((unsigned long)sp & ~0x3Ful); 399 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 400 } 401 sp -= sizeof(struct sigframe); 402 /* Align to 16 bytes. */ 403 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 404 405 /* Translate the signal if appropriate. */ 406 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 407 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 408 409 /* Build the argument list for the signal handler. */ 410 regs->tf_rdi = sig; /* arg 1 in %rdi */ 411 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 412 bzero(&sf.sf_si, sizeof(sf.sf_si)); 413 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 414 /* Signal handler installed with SA_SIGINFO. */ 415 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 416 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 417 418 /* Fill in POSIX parts */ 419 sf.sf_si = ksi->ksi_info; 420 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 421 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 422 } else { 423 /* Old FreeBSD-style arguments. */ 424 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 425 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 426 sf.sf_ahu.sf_handler = catcher; 427 } 428 mtx_unlock(&psp->ps_mtx); 429 PROC_UNLOCK(p); 430 431 /* 432 * Copy the sigframe out to the user's stack. 433 */ 434 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 435 (xfpusave != NULL && copyout(xfpusave, 436 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 437 != 0)) { 438#ifdef DEBUG 439 printf("process %ld has trashed its stack\n", (long)p->p_pid); 440#endif 441 PROC_LOCK(p); 442 sigexit(td, SIGILL); 443 } 444 445 regs->tf_rsp = (long)sfp; 446 regs->tf_rip = p->p_sysent->sv_sigcode_base; 447 regs->tf_rflags &= ~(PSL_T | PSL_D); 448 regs->tf_cs = _ucodesel; 449 regs->tf_ds = _udatasel; 450 regs->tf_es = _udatasel; 451 regs->tf_fs = _ufssel; 452 regs->tf_gs = _ugssel; 453 regs->tf_flags = TF_HASSEGS; 454 set_pcb_flags(pcb, PCB_FULL_IRET); 455 PROC_LOCK(p); 456 mtx_lock(&psp->ps_mtx); 457} 458 459/* 460 * System call to cleanup state after a signal 461 * has been taken. Reset signal mask and 462 * stack state from context left by sendsig (above). 463 * Return to previous pc and psl as specified by 464 * context left by sendsig. Check carefully to 465 * make sure that the user has not modified the 466 * state to gain improper privileges. 467 * 468 * MPSAFE 469 */ 470int 471sys_sigreturn(td, uap) 472 struct thread *td; 473 struct sigreturn_args /* { 474 const struct __ucontext *sigcntxp; 475 } */ *uap; 476{ 477 ucontext_t uc; 478 struct pcb *pcb; 479 struct proc *p; 480 struct trapframe *regs; 481 ucontext_t *ucp; 482 char *xfpustate; 483 size_t xfpustate_len; 484 long rflags; 485 int cs, error, ret; 486 ksiginfo_t ksi; 487 488 pcb = td->td_pcb; 489 p = td->td_proc; 490 491 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 492 if (error != 0) { 493 uprintf("pid %d (%s): sigreturn copyin failed\n", 494 p->p_pid, td->td_name); 495 return (error); 496 } 497 ucp = &uc; 498 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 499 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 500 td->td_name, ucp->uc_mcontext.mc_flags); 501 return (EINVAL); 502 } 503 regs = td->td_frame; 504 rflags = ucp->uc_mcontext.mc_rflags; 505 /* 506 * Don't allow users to change privileged or reserved flags. 507 */ 508 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 509 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 510 td->td_name, rflags); 511 return (EINVAL); 512 } 513 514 /* 515 * Don't allow users to load a valid privileged %cs. Let the 516 * hardware check for invalid selectors, excess privilege in 517 * other selectors, invalid %eip's and invalid %esp's. 518 */ 519 cs = ucp->uc_mcontext.mc_cs; 520 if (!CS_SECURE(cs)) { 521 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 522 td->td_name, cs); 523 ksiginfo_init_trap(&ksi); 524 ksi.ksi_signo = SIGBUS; 525 ksi.ksi_code = BUS_OBJERR; 526 ksi.ksi_trapno = T_PROTFLT; 527 ksi.ksi_addr = (void *)regs->tf_rip; 528 trapsignal(td, &ksi); 529 return (EINVAL); 530 } 531 532 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 533 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 534 if (xfpustate_len > cpu_max_ext_state_size - 535 sizeof(struct savefpu)) { 536 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 537 p->p_pid, td->td_name, xfpustate_len); 538 return (EINVAL); 539 } 540 xfpustate = __builtin_alloca(xfpustate_len); 541 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 542 xfpustate, xfpustate_len); 543 if (error != 0) { 544 uprintf( 545 "pid %d (%s): sigreturn copying xfpustate failed\n", 546 p->p_pid, td->td_name); 547 return (error); 548 } 549 } else { 550 xfpustate = NULL; 551 xfpustate_len = 0; 552 } 553 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 554 if (ret != 0) { 555 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 556 p->p_pid, td->td_name, ret); 557 return (ret); 558 } 559 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 560 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 561 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 562 563#if defined(COMPAT_43) 564 if (ucp->uc_mcontext.mc_onstack & 1) 565 td->td_sigstk.ss_flags |= SS_ONSTACK; 566 else 567 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 568#endif 569 570 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 571 set_pcb_flags(pcb, PCB_FULL_IRET); 572 return (EJUSTRETURN); 573} 574 575#ifdef COMPAT_FREEBSD4 576int 577freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 578{ 579 580 return sys_sigreturn(td, (struct sigreturn_args *)uap); 581} 582#endif 583 584 585/* 586 * Machine dependent boot() routine 587 * 588 * I haven't seen anything to put here yet 589 * Possibly some stuff might be grafted back here from boot() 590 */ 591void 592cpu_boot(int howto) 593{ 594} 595 596/* 597 * Flush the D-cache for non-DMA I/O so that the I-cache can 598 * be made coherent later. 599 */ 600void 601cpu_flush_dcache(void *ptr, size_t len) 602{ 603 /* Not applicable */ 604} 605 606/* Get current clock frequency for the given cpu id. */ 607int 608cpu_est_clockrate(int cpu_id, uint64_t *rate) 609{ 610 uint64_t tsc1, tsc2; 611 uint64_t acnt, mcnt, perf; 612 register_t reg; 613 614 if (pcpu_find(cpu_id) == NULL || rate == NULL) 615 return (EINVAL); 616 617 /* 618 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 619 * DELAY(9) based logic fails. 620 */ 621 if (tsc_is_invariant && !tsc_perf_stat) 622 return (EOPNOTSUPP); 623 624#ifdef SMP 625 if (smp_cpus > 1) { 626 /* Schedule ourselves on the indicated cpu. */ 627 thread_lock(curthread); 628 sched_bind(curthread, cpu_id); 629 thread_unlock(curthread); 630 } 631#endif 632 633 /* Calibrate by measuring a short delay. */ 634 reg = intr_disable(); 635 if (tsc_is_invariant) { 636 wrmsr(MSR_MPERF, 0); 637 wrmsr(MSR_APERF, 0); 638 tsc1 = rdtsc(); 639 DELAY(1000); 640 mcnt = rdmsr(MSR_MPERF); 641 acnt = rdmsr(MSR_APERF); 642 tsc2 = rdtsc(); 643 intr_restore(reg); 644 perf = 1000 * acnt / mcnt; 645 *rate = (tsc2 - tsc1) * perf; 646 } else { 647 tsc1 = rdtsc(); 648 DELAY(1000); 649 tsc2 = rdtsc(); 650 intr_restore(reg); 651 *rate = (tsc2 - tsc1) * 1000; 652 } 653 654#ifdef SMP 655 if (smp_cpus > 1) { 656 thread_lock(curthread); 657 sched_unbind(curthread); 658 thread_unlock(curthread); 659 } 660#endif 661 662 return (0); 663} 664 665/* 666 * Shutdown the CPU as much as possible 667 */ 668void 669cpu_halt(void) 670{ 671 for (;;) 672 halt(); 673} 674 675void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 676static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 677static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 678TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 679SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 680 0, "Use MONITOR/MWAIT for short idle"); 681 682#define STATE_RUNNING 0x0 683#define STATE_MWAIT 0x1 684#define STATE_SLEEPING 0x2 685 686static void 687cpu_idle_acpi(sbintime_t sbt) 688{ 689 int *state; 690 691 state = (int *)PCPU_PTR(monitorbuf); 692 *state = STATE_SLEEPING; 693 694 /* See comments in cpu_idle_hlt(). */ 695 disable_intr(); 696 if (sched_runnable()) 697 enable_intr(); 698 else if (cpu_idle_hook) 699 cpu_idle_hook(sbt); 700 else 701 __asm __volatile("sti; hlt"); 702 *state = STATE_RUNNING; 703} 704 705static void 706cpu_idle_hlt(sbintime_t sbt) 707{ 708 int *state; 709 710 state = (int *)PCPU_PTR(monitorbuf); 711 *state = STATE_SLEEPING; 712 713 /* 714 * Since we may be in a critical section from cpu_idle(), if 715 * an interrupt fires during that critical section we may have 716 * a pending preemption. If the CPU halts, then that thread 717 * may not execute until a later interrupt awakens the CPU. 718 * To handle this race, check for a runnable thread after 719 * disabling interrupts and immediately return if one is 720 * found. Also, we must absolutely guarentee that hlt is 721 * the next instruction after sti. This ensures that any 722 * interrupt that fires after the call to disable_intr() will 723 * immediately awaken the CPU from hlt. Finally, please note 724 * that on x86 this works fine because of interrupts enabled only 725 * after the instruction following sti takes place, while IF is set 726 * to 1 immediately, allowing hlt instruction to acknowledge the 727 * interrupt. 728 */ 729 disable_intr(); 730 if (sched_runnable()) 731 enable_intr(); 732 else 733 __asm __volatile("sti; hlt"); 734 *state = STATE_RUNNING; 735} 736 737/* 738 * MWAIT cpu power states. Lower 4 bits are sub-states. 739 */ 740#define MWAIT_C0 0xf0 741#define MWAIT_C1 0x00 742#define MWAIT_C2 0x10 743#define MWAIT_C3 0x20 744#define MWAIT_C4 0x30 745 746static void 747cpu_idle_mwait(sbintime_t sbt) 748{ 749 int *state; 750 751 state = (int *)PCPU_PTR(monitorbuf); 752 *state = STATE_MWAIT; 753 754 /* See comments in cpu_idle_hlt(). */ 755 disable_intr(); 756 if (sched_runnable()) { 757 enable_intr(); 758 *state = STATE_RUNNING; 759 return; 760 } 761 cpu_monitor(state, 0, 0); 762 if (*state == STATE_MWAIT) 763 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 764 else 765 enable_intr(); 766 *state = STATE_RUNNING; 767} 768 769static void 770cpu_idle_spin(sbintime_t sbt) 771{ 772 int *state; 773 int i; 774 775 state = (int *)PCPU_PTR(monitorbuf); 776 *state = STATE_RUNNING; 777 778 /* 779 * The sched_runnable() call is racy but as long as there is 780 * a loop missing it one time will have just a little impact if any 781 * (and it is much better than missing the check at all). 782 */ 783 for (i = 0; i < 1000; i++) { 784 if (sched_runnable()) 785 return; 786 cpu_spinwait(); 787 } 788} 789 790/* 791 * C1E renders the local APIC timer dead, so we disable it by 792 * reading the Interrupt Pending Message register and clearing 793 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 794 * 795 * Reference: 796 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 797 * #32559 revision 3.00+ 798 */ 799#define MSR_AMDK8_IPM 0xc0010055 800#define AMDK8_SMIONCMPHALT (1ULL << 27) 801#define AMDK8_C1EONCMPHALT (1ULL << 28) 802#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 803 804static void 805cpu_probe_amdc1e(void) 806{ 807 808 /* 809 * Detect the presence of C1E capability mostly on latest 810 * dual-cores (or future) k8 family. 811 */ 812 if (cpu_vendor_id == CPU_VENDOR_AMD && 813 (cpu_id & 0x00000f00) == 0x00000f00 && 814 (cpu_id & 0x0fff0000) >= 0x00040000) { 815 cpu_ident_amdc1e = 1; 816 } 817} 818 819void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 820 821void 822cpu_idle(int busy) 823{ 824 uint64_t msr; 825 sbintime_t sbt = -1; 826 827 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 828 busy, curcpu); 829#ifdef MP_WATCHDOG 830 ap_watchdog(PCPU_GET(cpuid)); 831#endif 832 /* If we are busy - try to use fast methods. */ 833 if (busy) { 834 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 835 cpu_idle_mwait(busy); 836 goto out; 837 } 838 } 839 840 /* If we have time - switch timers into idle mode. */ 841 if (!busy) { 842 critical_enter(); 843 sbt = cpu_idleclock(); 844 } 845 846 /* Apply AMD APIC timer C1E workaround. */ 847 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 848 msr = rdmsr(MSR_AMDK8_IPM); 849 if (msr & AMDK8_CMPHALT) 850 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 851 } 852 853 /* Call main idle method. */ 854 cpu_idle_fn(sbt); 855 856 /* Switch timers back into active mode. */ 857 if (!busy) { 858 cpu_activeclock(); 859 critical_exit(); 860 } 861out: 862 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 863 busy, curcpu); 864} 865 866int 867cpu_idle_wakeup(int cpu) 868{ 869 struct pcpu *pcpu; 870 int *state; 871 872 pcpu = pcpu_find(cpu); 873 state = (int *)pcpu->pc_monitorbuf; 874 /* 875 * This doesn't need to be atomic since missing the race will 876 * simply result in unnecessary IPIs. 877 */ 878 if (*state == STATE_SLEEPING) 879 return (0); 880 if (*state == STATE_MWAIT) 881 *state = STATE_RUNNING; 882 return (1); 883} 884 885/* 886 * Ordered by speed/power consumption. 887 */ 888struct { 889 void *id_fn; 890 char *id_name; 891} idle_tbl[] = { 892 { cpu_idle_spin, "spin" }, 893 { cpu_idle_mwait, "mwait" }, 894 { cpu_idle_hlt, "hlt" }, 895 { cpu_idle_acpi, "acpi" }, 896 { NULL, NULL } 897}; 898 899static int 900idle_sysctl_available(SYSCTL_HANDLER_ARGS) 901{ 902 char *avail, *p; 903 int error; 904 int i; 905 906 avail = malloc(256, M_TEMP, M_WAITOK); 907 p = avail; 908 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 909 if (strstr(idle_tbl[i].id_name, "mwait") && 910 (cpu_feature2 & CPUID2_MON) == 0) 911 continue; 912 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 913 cpu_idle_hook == NULL) 914 continue; 915 p += sprintf(p, "%s%s", p != avail ? ", " : "", 916 idle_tbl[i].id_name); 917 } 918 error = sysctl_handle_string(oidp, avail, 0, req); 919 free(avail, M_TEMP); 920 return (error); 921} 922 923SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 924 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 925 926static int 927idle_sysctl(SYSCTL_HANDLER_ARGS) 928{ 929 char buf[16]; 930 int error; 931 char *p; 932 int i; 933 934 p = "unknown"; 935 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 936 if (idle_tbl[i].id_fn == cpu_idle_fn) { 937 p = idle_tbl[i].id_name; 938 break; 939 } 940 } 941 strncpy(buf, p, sizeof(buf)); 942 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 943 if (error != 0 || req->newptr == NULL) 944 return (error); 945 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 946 if (strstr(idle_tbl[i].id_name, "mwait") && 947 (cpu_feature2 & CPUID2_MON) == 0) 948 continue; 949 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 950 cpu_idle_hook == NULL) 951 continue; 952 if (strcmp(idle_tbl[i].id_name, buf)) 953 continue; 954 cpu_idle_fn = idle_tbl[i].id_fn; 955 return (0); 956 } 957 return (EINVAL); 958} 959 960SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 961 idle_sysctl, "A", "currently selected idle function"); 962 963/* 964 * Reset registers to default values on exec. 965 */ 966void 967exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 968{ 969 struct trapframe *regs = td->td_frame; 970 struct pcb *pcb = td->td_pcb; 971 972 mtx_lock(&dt_lock); 973 if (td->td_proc->p_md.md_ldt != NULL) 974 user_ldt_free(td); 975 else 976 mtx_unlock(&dt_lock); 977 978 pcb->pcb_fsbase = 0; 979 pcb->pcb_gsbase = 0; 980 clear_pcb_flags(pcb, PCB_32BIT); 981 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 982 set_pcb_flags(pcb, PCB_FULL_IRET); 983 984 bzero((char *)regs, sizeof(struct trapframe)); 985 regs->tf_rip = imgp->entry_addr; 986 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 987 regs->tf_rdi = stack; /* argv */ 988 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 989 regs->tf_ss = _udatasel; 990 regs->tf_cs = _ucodesel; 991 regs->tf_ds = _udatasel; 992 regs->tf_es = _udatasel; 993 regs->tf_fs = _ufssel; 994 regs->tf_gs = _ugssel; 995 regs->tf_flags = TF_HASSEGS; 996 td->td_retval[1] = 0; 997 998 /* 999 * Reset the hardware debug registers if they were in use. 1000 * They won't have any meaning for the newly exec'd process. 1001 */ 1002 if (pcb->pcb_flags & PCB_DBREGS) { 1003 pcb->pcb_dr0 = 0; 1004 pcb->pcb_dr1 = 0; 1005 pcb->pcb_dr2 = 0; 1006 pcb->pcb_dr3 = 0; 1007 pcb->pcb_dr6 = 0; 1008 pcb->pcb_dr7 = 0; 1009 if (pcb == curpcb) { 1010 /* 1011 * Clear the debug registers on the running 1012 * CPU, otherwise they will end up affecting 1013 * the next process we switch to. 1014 */ 1015 reset_dbregs(); 1016 } 1017 clear_pcb_flags(pcb, PCB_DBREGS); 1018 } 1019 1020 /* 1021 * Drop the FP state if we hold it, so that the process gets a 1022 * clean FP state if it uses the FPU again. 1023 */ 1024 fpstate_drop(td); 1025} 1026 1027void 1028cpu_setregs(void) 1029{ 1030 register_t cr0; 1031 1032 cr0 = rcr0(); 1033 /* 1034 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1035 * BSP. See the comments there about why we set them. 1036 */ 1037 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1038 load_cr0(cr0); 1039} 1040 1041/* 1042 * Initialize amd64 and configure to run kernel 1043 */ 1044 1045/* 1046 * Initialize segments & interrupt table 1047 */ 1048 1049struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1050static struct gate_descriptor idt0[NIDT]; 1051struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1052 1053static char dblfault_stack[PAGE_SIZE] __aligned(16); 1054 1055static char nmi0_stack[PAGE_SIZE] __aligned(16); 1056CTASSERT(sizeof(struct nmi_pcpu) == 16); 1057 1058struct amd64tss common_tss[MAXCPU]; 1059 1060/* 1061 * Software prototypes -- in more palatable form. 1062 * 1063 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1064 * slots as corresponding segments for i386 kernel. 1065 */ 1066struct soft_segment_descriptor gdt_segs[] = { 1067/* GNULL_SEL 0 Null Descriptor */ 1068{ .ssd_base = 0x0, 1069 .ssd_limit = 0x0, 1070 .ssd_type = 0, 1071 .ssd_dpl = 0, 1072 .ssd_p = 0, 1073 .ssd_long = 0, 1074 .ssd_def32 = 0, 1075 .ssd_gran = 0 }, 1076/* GNULL2_SEL 1 Null Descriptor */ 1077{ .ssd_base = 0x0, 1078 .ssd_limit = 0x0, 1079 .ssd_type = 0, 1080 .ssd_dpl = 0, 1081 .ssd_p = 0, 1082 .ssd_long = 0, 1083 .ssd_def32 = 0, 1084 .ssd_gran = 0 }, 1085/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1086{ .ssd_base = 0x0, 1087 .ssd_limit = 0xfffff, 1088 .ssd_type = SDT_MEMRWA, 1089 .ssd_dpl = SEL_UPL, 1090 .ssd_p = 1, 1091 .ssd_long = 0, 1092 .ssd_def32 = 1, 1093 .ssd_gran = 1 }, 1094/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1095{ .ssd_base = 0x0, 1096 .ssd_limit = 0xfffff, 1097 .ssd_type = SDT_MEMRWA, 1098 .ssd_dpl = SEL_UPL, 1099 .ssd_p = 1, 1100 .ssd_long = 0, 1101 .ssd_def32 = 1, 1102 .ssd_gran = 1 }, 1103/* GCODE_SEL 4 Code Descriptor for kernel */ 1104{ .ssd_base = 0x0, 1105 .ssd_limit = 0xfffff, 1106 .ssd_type = SDT_MEMERA, 1107 .ssd_dpl = SEL_KPL, 1108 .ssd_p = 1, 1109 .ssd_long = 1, 1110 .ssd_def32 = 0, 1111 .ssd_gran = 1 }, 1112/* GDATA_SEL 5 Data Descriptor for kernel */ 1113{ .ssd_base = 0x0, 1114 .ssd_limit = 0xfffff, 1115 .ssd_type = SDT_MEMRWA, 1116 .ssd_dpl = SEL_KPL, 1117 .ssd_p = 1, 1118 .ssd_long = 1, 1119 .ssd_def32 = 0, 1120 .ssd_gran = 1 }, 1121/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1122{ .ssd_base = 0x0, 1123 .ssd_limit = 0xfffff, 1124 .ssd_type = SDT_MEMERA, 1125 .ssd_dpl = SEL_UPL, 1126 .ssd_p = 1, 1127 .ssd_long = 0, 1128 .ssd_def32 = 1, 1129 .ssd_gran = 1 }, 1130/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1131{ .ssd_base = 0x0, 1132 .ssd_limit = 0xfffff, 1133 .ssd_type = SDT_MEMRWA, 1134 .ssd_dpl = SEL_UPL, 1135 .ssd_p = 1, 1136 .ssd_long = 0, 1137 .ssd_def32 = 1, 1138 .ssd_gran = 1 }, 1139/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1140{ .ssd_base = 0x0, 1141 .ssd_limit = 0xfffff, 1142 .ssd_type = SDT_MEMERA, 1143 .ssd_dpl = SEL_UPL, 1144 .ssd_p = 1, 1145 .ssd_long = 1, 1146 .ssd_def32 = 0, 1147 .ssd_gran = 1 }, 1148/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1149{ .ssd_base = 0x0, 1150 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1151 .ssd_type = SDT_SYSTSS, 1152 .ssd_dpl = SEL_KPL, 1153 .ssd_p = 1, 1154 .ssd_long = 0, 1155 .ssd_def32 = 0, 1156 .ssd_gran = 0 }, 1157/* Actually, the TSS is a system descriptor which is double size */ 1158{ .ssd_base = 0x0, 1159 .ssd_limit = 0x0, 1160 .ssd_type = 0, 1161 .ssd_dpl = 0, 1162 .ssd_p = 0, 1163 .ssd_long = 0, 1164 .ssd_def32 = 0, 1165 .ssd_gran = 0 }, 1166/* GUSERLDT_SEL 11 LDT Descriptor */ 1167{ .ssd_base = 0x0, 1168 .ssd_limit = 0x0, 1169 .ssd_type = 0, 1170 .ssd_dpl = 0, 1171 .ssd_p = 0, 1172 .ssd_long = 0, 1173 .ssd_def32 = 0, 1174 .ssd_gran = 0 }, 1175/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1176{ .ssd_base = 0x0, 1177 .ssd_limit = 0x0, 1178 .ssd_type = 0, 1179 .ssd_dpl = 0, 1180 .ssd_p = 0, 1181 .ssd_long = 0, 1182 .ssd_def32 = 0, 1183 .ssd_gran = 0 }, 1184}; 1185 1186void 1187setidt(idx, func, typ, dpl, ist) 1188 int idx; 1189 inthand_t *func; 1190 int typ; 1191 int dpl; 1192 int ist; 1193{ 1194 struct gate_descriptor *ip; 1195 1196 ip = idt + idx; 1197 ip->gd_looffset = (uintptr_t)func; 1198 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1199 ip->gd_ist = ist; 1200 ip->gd_xx = 0; 1201 ip->gd_type = typ; 1202 ip->gd_dpl = dpl; 1203 ip->gd_p = 1; 1204 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1205} 1206 1207extern inthand_t 1208 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1209 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1210 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1211 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1212 IDTVEC(xmm), IDTVEC(dblfault), 1213#ifdef KDTRACE_HOOKS 1214 IDTVEC(dtrace_ret), 1215#endif 1216#ifdef XENHVM 1217 IDTVEC(xen_intr_upcall), 1218#endif 1219 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1220 1221#ifdef DDB 1222/* 1223 * Display the index and function name of any IDT entries that don't use 1224 * the default 'rsvd' entry point. 1225 */ 1226DB_SHOW_COMMAND(idt, db_show_idt) 1227{ 1228 struct gate_descriptor *ip; 1229 int idx; 1230 uintptr_t func; 1231 1232 ip = idt; 1233 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1234 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1235 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1236 db_printf("%3d\t", idx); 1237 db_printsym(func, DB_STGY_PROC); 1238 db_printf("\n"); 1239 } 1240 ip++; 1241 } 1242} 1243 1244/* Show privileged registers. */ 1245DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1246{ 1247 struct { 1248 uint16_t limit; 1249 uint64_t base; 1250 } __packed idtr, gdtr; 1251 uint16_t ldt, tr; 1252 1253 __asm __volatile("sidt %0" : "=m" (idtr)); 1254 db_printf("idtr\t0x%016lx/%04x\n", 1255 (u_long)idtr.base, (u_int)idtr.limit); 1256 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1257 db_printf("gdtr\t0x%016lx/%04x\n", 1258 (u_long)gdtr.base, (u_int)gdtr.limit); 1259 __asm __volatile("sldt %0" : "=r" (ldt)); 1260 db_printf("ldtr\t0x%04x\n", ldt); 1261 __asm __volatile("str %0" : "=r" (tr)); 1262 db_printf("tr\t0x%04x\n", tr); 1263 db_printf("cr0\t0x%016lx\n", rcr0()); 1264 db_printf("cr2\t0x%016lx\n", rcr2()); 1265 db_printf("cr3\t0x%016lx\n", rcr3()); 1266 db_printf("cr4\t0x%016lx\n", rcr4()); 1267 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1268 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1269 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1270 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1271 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1272} 1273#endif 1274 1275void 1276sdtossd(sd, ssd) 1277 struct user_segment_descriptor *sd; 1278 struct soft_segment_descriptor *ssd; 1279{ 1280 1281 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1282 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1283 ssd->ssd_type = sd->sd_type; 1284 ssd->ssd_dpl = sd->sd_dpl; 1285 ssd->ssd_p = sd->sd_p; 1286 ssd->ssd_long = sd->sd_long; 1287 ssd->ssd_def32 = sd->sd_def32; 1288 ssd->ssd_gran = sd->sd_gran; 1289} 1290 1291void 1292ssdtosd(ssd, sd) 1293 struct soft_segment_descriptor *ssd; 1294 struct user_segment_descriptor *sd; 1295{ 1296 1297 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1298 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1299 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1300 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1301 sd->sd_type = ssd->ssd_type; 1302 sd->sd_dpl = ssd->ssd_dpl; 1303 sd->sd_p = ssd->ssd_p; 1304 sd->sd_long = ssd->ssd_long; 1305 sd->sd_def32 = ssd->ssd_def32; 1306 sd->sd_gran = ssd->ssd_gran; 1307} 1308 1309void 1310ssdtosyssd(ssd, sd) 1311 struct soft_segment_descriptor *ssd; 1312 struct system_segment_descriptor *sd; 1313{ 1314 1315 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1316 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1317 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1318 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1319 sd->sd_type = ssd->ssd_type; 1320 sd->sd_dpl = ssd->ssd_dpl; 1321 sd->sd_p = ssd->ssd_p; 1322 sd->sd_gran = ssd->ssd_gran; 1323} 1324 1325#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1326#include <isa/isavar.h> 1327#include <isa/isareg.h> 1328/* 1329 * Return a bitmap of the current interrupt requests. This is 8259-specific 1330 * and is only suitable for use at probe time. 1331 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1332 * It shouldn't be here. There should probably be an APIC centric 1333 * implementation in the apic driver code, if at all. 1334 */ 1335intrmask_t 1336isa_irq_pending(void) 1337{ 1338 u_char irr1; 1339 u_char irr2; 1340 1341 irr1 = inb(IO_ICU1); 1342 irr2 = inb(IO_ICU2); 1343 return ((irr2 << 8) | irr1); 1344} 1345#endif 1346 1347u_int basemem; 1348 1349static int 1350add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap, 1351 int *physmap_idxp) 1352{ 1353 int i, insert_idx, physmap_idx; 1354 1355 physmap_idx = *physmap_idxp; 1356 1357 if (length == 0) 1358 return (1); 1359 1360 /* 1361 * Find insertion point while checking for overlap. Start off by 1362 * assuming the new entry will be added to the end. 1363 */ 1364 insert_idx = physmap_idx + 2; 1365 for (i = 0; i <= physmap_idx; i += 2) { 1366 if (base < physmap[i + 1]) { 1367 if (base + length <= physmap[i]) { 1368 insert_idx = i; 1369 break; 1370 } 1371 if (boothowto & RB_VERBOSE) 1372 printf( 1373 "Overlapping memory regions, ignoring second region\n"); 1374 return (1); 1375 } 1376 } 1377 1378 /* See if we can prepend to the next entry. */ 1379 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) { 1380 physmap[insert_idx] = base; 1381 return (1); 1382 } 1383 1384 /* See if we can append to the previous entry. */ 1385 if (insert_idx > 0 && base == physmap[insert_idx - 1]) { 1386 physmap[insert_idx - 1] += length; 1387 return (1); 1388 } 1389 1390 physmap_idx += 2; 1391 *physmap_idxp = physmap_idx; 1392 if (physmap_idx == PHYSMAP_SIZE) { 1393 printf( 1394 "Too many segments in the physical address map, giving up\n"); 1395 return (0); 1396 } 1397 1398 /* 1399 * Move the last 'N' entries down to make room for the new 1400 * entry if needed. 1401 */ 1402 for (i = physmap_idx; i > insert_idx; i -= 2) { 1403 physmap[i] = physmap[i - 2]; 1404 physmap[i + 1] = physmap[i - 1]; 1405 } 1406 1407 /* Insert the new entry. */ 1408 physmap[insert_idx] = base; 1409 physmap[insert_idx + 1] = base + length; 1410 return (1); 1411} 1412 1413void 1414bios_add_smap_entries(struct bios_smap *smapbase, u_int32_t smapsize, 1415 vm_paddr_t *physmap, int *physmap_idx) 1416{ 1417 struct bios_smap *smap, *smapend; 1418 1419 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1420 1421 for (smap = smapbase; smap < smapend; smap++) { 1422 if (boothowto & RB_VERBOSE) 1423 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1424 smap->type, smap->base, smap->length); 1425 1426 if (smap->type != SMAP_TYPE_MEMORY) 1427 continue; 1428 1429 if (!add_physmap_entry(smap->base, smap->length, physmap, 1430 physmap_idx)) 1431 break; 1432 } 1433} 1434 1435static void 1436native_parse_memmap(caddr_t kmdp, vm_paddr_t *physmap, int *physmap_idx) 1437{ 1438 struct bios_smap *smap; 1439 u_int32_t size; 1440 1441 /* 1442 * Memory map from INT 15:E820. 1443 * 1444 * subr_module.c says: 1445 * "Consumer may safely assume that size value precedes data." 1446 * ie: an int32_t immediately precedes smap. 1447 */ 1448 1449 smap = (struct bios_smap *)preload_search_info(kmdp, 1450 MODINFO_METADATA | MODINFOMD_SMAP); 1451 if (smap == NULL) 1452 panic("No BIOS smap info from loader!"); 1453 size = *((u_int32_t *)smap - 1); 1454 1455 bios_add_smap_entries(smap, size, physmap, physmap_idx); 1456} 1457 1458/* 1459 * Populate the (physmap) array with base/bound pairs describing the 1460 * available physical memory in the system, then test this memory and 1461 * build the phys_avail array describing the actually-available memory. 1462 * 1463 * Total memory size may be set by the kernel environment variable 1464 * hw.physmem or the compile-time define MAXMEM. 1465 * 1466 * XXX first should be vm_paddr_t. 1467 */ 1468static void 1469getmemsize(caddr_t kmdp, u_int64_t first) 1470{ 1471 int i, physmap_idx, pa_indx, da_indx; 1472 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1473 u_long physmem_start, physmem_tunable, memtest; 1474 pt_entry_t *pte; 1475 quad_t dcons_addr, dcons_size; 1476 1477 bzero(physmap, sizeof(physmap)); 1478 basemem = 0; 1479 physmap_idx = 0; 1480 1481 init_ops.parse_memmap(kmdp, physmap, &physmap_idx); 1482 1483 /* 1484 * Find the 'base memory' segment for SMP 1485 */ 1486 basemem = 0; 1487 for (i = 0; i <= physmap_idx; i += 2) { 1488 if (physmap[i] == 0x00000000) { 1489 basemem = physmap[i + 1] / 1024; 1490 break; 1491 } 1492 } 1493 if (basemem == 0) 1494 panic("BIOS smap did not include a basemem segment!"); 1495 1496 /* 1497 * Make hole for "AP -> long mode" bootstrap code. The 1498 * mp_bootaddress vector is only available when the kernel 1499 * is configured to support APs and APs for the system start 1500 * in 32bit mode (e.g. SMP bare metal). 1501 */ 1502 if (init_ops.mp_bootaddress) 1503 physmap[1] = init_ops.mp_bootaddress(physmap[1] / 1024); 1504 1505 /* 1506 * Maxmem isn't the "maximum memory", it's one larger than the 1507 * highest page of the physical address space. It should be 1508 * called something like "Maxphyspage". We may adjust this 1509 * based on ``hw.physmem'' and the results of the memory test. 1510 */ 1511 Maxmem = atop(physmap[physmap_idx + 1]); 1512 1513#ifdef MAXMEM 1514 Maxmem = MAXMEM / 4; 1515#endif 1516 1517 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1518 Maxmem = atop(physmem_tunable); 1519 1520 /* 1521 * The boot memory test is disabled by default, as it takes a 1522 * significant amount of time on large-memory systems, and is 1523 * unfriendly to virtual machines as it unnecessarily touches all 1524 * pages. 1525 * 1526 * A general name is used as the code may be extended to support 1527 * additional tests beyond the current "page present" test. 1528 */ 1529 memtest = 0; 1530 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1531 1532 /* 1533 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1534 * in the system. 1535 */ 1536 if (Maxmem > atop(physmap[physmap_idx + 1])) 1537 Maxmem = atop(physmap[physmap_idx + 1]); 1538 1539 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1540 (boothowto & RB_VERBOSE)) 1541 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1542 1543 /* call pmap initialization to make new kernel address space */ 1544 pmap_bootstrap(&first); 1545 1546 /* 1547 * Size up each available chunk of physical memory. 1548 * 1549 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1550 * By default, mask off the first 16 pages unless we appear to be 1551 * running in a VM. 1552 */ 1553 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1554 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1555 if (physmem_start < PAGE_SIZE) 1556 physmap[0] = PAGE_SIZE; 1557 else if (physmem_start >= physmap[1]) 1558 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1559 else 1560 physmap[0] = round_page(physmem_start); 1561 pa_indx = 0; 1562 da_indx = 1; 1563 phys_avail[pa_indx++] = physmap[0]; 1564 phys_avail[pa_indx] = physmap[0]; 1565 dump_avail[da_indx] = physmap[0]; 1566 pte = CMAP1; 1567 1568 /* 1569 * Get dcons buffer address 1570 */ 1571 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1572 getenv_quad("dcons.size", &dcons_size) == 0) 1573 dcons_addr = 0; 1574 1575 /* 1576 * physmap is in bytes, so when converting to page boundaries, 1577 * round up the start address and round down the end address. 1578 */ 1579 for (i = 0; i <= physmap_idx; i += 2) { 1580 vm_paddr_t end; 1581 1582 end = ptoa((vm_paddr_t)Maxmem); 1583 if (physmap[i + 1] < end) 1584 end = trunc_page(physmap[i + 1]); 1585 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1586 int tmp, page_bad, full; 1587 int *ptr = (int *)CADDR1; 1588 1589 full = FALSE; 1590 /* 1591 * block out kernel memory as not available. 1592 */ 1593 if (pa >= (vm_paddr_t)kernphys && pa < first) 1594 goto do_dump_avail; 1595 1596 /* 1597 * block out dcons buffer 1598 */ 1599 if (dcons_addr > 0 1600 && pa >= trunc_page(dcons_addr) 1601 && pa < dcons_addr + dcons_size) 1602 goto do_dump_avail; 1603 1604 page_bad = FALSE; 1605 if (memtest == 0) 1606 goto skip_memtest; 1607 1608 /* 1609 * map page into kernel: valid, read/write,non-cacheable 1610 */ 1611 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1612 invltlb(); 1613 1614 tmp = *(int *)ptr; 1615 /* 1616 * Test for alternating 1's and 0's 1617 */ 1618 *(volatile int *)ptr = 0xaaaaaaaa; 1619 if (*(volatile int *)ptr != 0xaaaaaaaa) 1620 page_bad = TRUE; 1621 /* 1622 * Test for alternating 0's and 1's 1623 */ 1624 *(volatile int *)ptr = 0x55555555; 1625 if (*(volatile int *)ptr != 0x55555555) 1626 page_bad = TRUE; 1627 /* 1628 * Test for all 1's 1629 */ 1630 *(volatile int *)ptr = 0xffffffff; 1631 if (*(volatile int *)ptr != 0xffffffff) 1632 page_bad = TRUE; 1633 /* 1634 * Test for all 0's 1635 */ 1636 *(volatile int *)ptr = 0x0; 1637 if (*(volatile int *)ptr != 0x0) 1638 page_bad = TRUE; 1639 /* 1640 * Restore original value. 1641 */ 1642 *(int *)ptr = tmp; 1643 1644skip_memtest: 1645 /* 1646 * Adjust array of valid/good pages. 1647 */ 1648 if (page_bad == TRUE) 1649 continue; 1650 /* 1651 * If this good page is a continuation of the 1652 * previous set of good pages, then just increase 1653 * the end pointer. Otherwise start a new chunk. 1654 * Note that "end" points one higher than end, 1655 * making the range >= start and < end. 1656 * If we're also doing a speculative memory 1657 * test and we at or past the end, bump up Maxmem 1658 * so that we keep going. The first bad page 1659 * will terminate the loop. 1660 */ 1661 if (phys_avail[pa_indx] == pa) { 1662 phys_avail[pa_indx] += PAGE_SIZE; 1663 } else { 1664 pa_indx++; 1665 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1666 printf( 1667 "Too many holes in the physical address space, giving up\n"); 1668 pa_indx--; 1669 full = TRUE; 1670 goto do_dump_avail; 1671 } 1672 phys_avail[pa_indx++] = pa; /* start */ 1673 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1674 } 1675 physmem++; 1676do_dump_avail: 1677 if (dump_avail[da_indx] == pa) { 1678 dump_avail[da_indx] += PAGE_SIZE; 1679 } else { 1680 da_indx++; 1681 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1682 da_indx--; 1683 goto do_next; 1684 } 1685 dump_avail[da_indx++] = pa; /* start */ 1686 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1687 } 1688do_next: 1689 if (full) 1690 break; 1691 } 1692 } 1693 *pte = 0; 1694 invltlb(); 1695 1696 /* 1697 * XXX 1698 * The last chunk must contain at least one page plus the message 1699 * buffer to avoid complicating other code (message buffer address 1700 * calculation, etc.). 1701 */ 1702 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1703 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1704 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1705 phys_avail[pa_indx--] = 0; 1706 phys_avail[pa_indx--] = 0; 1707 } 1708 1709 Maxmem = atop(phys_avail[pa_indx]); 1710 1711 /* Trim off space for the message buffer. */ 1712 phys_avail[pa_indx] -= round_page(msgbufsize); 1713 1714 /* Map the message buffer. */ 1715 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1716} 1717 1718static caddr_t 1719native_parse_preload_data(u_int64_t modulep) 1720{ 1721 caddr_t kmdp; 1722 1723 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1724 preload_bootstrap_relocate(KERNBASE); 1725 kmdp = preload_search_by_type("elf kernel"); 1726 if (kmdp == NULL) 1727 kmdp = preload_search_by_type("elf64 kernel"); 1728 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1729 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1730#ifdef DDB 1731 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1732 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1733#endif 1734 1735 return (kmdp); 1736} 1737 1738u_int64_t 1739hammer_time(u_int64_t modulep, u_int64_t physfree) 1740{ 1741 caddr_t kmdp; 1742 int gsel_tss, x; 1743 struct pcpu *pc; 1744 struct nmi_pcpu *np; 1745 struct xstate_hdr *xhdr; 1746 u_int64_t msr; 1747 char *env; 1748 size_t kstack0_sz; 1749 1750 thread0.td_kstack = physfree + KERNBASE; 1751 thread0.td_kstack_pages = KSTACK_PAGES; 1752 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1753 bzero((void *)thread0.td_kstack, kstack0_sz); 1754 physfree += kstack0_sz; 1755 1756 /* 1757 * This may be done better later if it gets more high level 1758 * components in it. If so just link td->td_proc here. 1759 */ 1760 proc_linkup0(&proc0, &thread0); 1761 1762 kmdp = init_ops.parse_preload_data(modulep); 1763 1764 /* Init basic tunables, hz etc */ 1765 init_param1(); 1766 1767 /* 1768 * make gdt memory segments 1769 */ 1770 for (x = 0; x < NGDT; x++) { 1771 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1772 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1773 ssdtosd(&gdt_segs[x], &gdt[x]); 1774 } 1775 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1776 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1777 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1778 1779 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1780 r_gdt.rd_base = (long) gdt; 1781 lgdt(&r_gdt); 1782 pc = &__pcpu[0]; 1783 1784 wrmsr(MSR_FSBASE, 0); /* User value */ 1785 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1786 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1787 1788 pcpu_init(pc, 0, sizeof(struct pcpu)); 1789 dpcpu_init((void *)(physfree + KERNBASE), 0); 1790 physfree += DPCPU_SIZE; 1791 PCPU_SET(prvspace, pc); 1792 PCPU_SET(curthread, &thread0); 1793 PCPU_SET(tssp, &common_tss[0]); 1794 PCPU_SET(commontssp, &common_tss[0]); 1795 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1796 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1797 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1798 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1799 1800 /* 1801 * Initialize mutexes. 1802 * 1803 * icu_lock: in order to allow an interrupt to occur in a critical 1804 * section, to set pcpu->ipending (etc...) properly, we 1805 * must be able to get the icu lock, so it can't be 1806 * under witness. 1807 */ 1808 mutex_init(); 1809 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1810 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1811 1812 /* exceptions */ 1813 for (x = 0; x < NIDT; x++) 1814 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1815 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1816 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1817 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1818 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1819 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1820 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1821 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1822 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1823 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1824 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1825 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1826 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1827 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1828 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1829 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1830 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1831 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1832 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1833 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1834#ifdef KDTRACE_HOOKS 1835 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1836#endif 1837#ifdef XENHVM 1838 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1839#endif 1840 1841 r_idt.rd_limit = sizeof(idt0) - 1; 1842 r_idt.rd_base = (long) idt; 1843 lidt(&r_idt); 1844 1845 /* 1846 * Initialize the clock before the console so that console 1847 * initialization can use DELAY(). 1848 */ 1849 clock_init(); 1850 1851 /* 1852 * Initialize the console before we print anything out. 1853 */ 1854 cninit(); 1855 1856#ifdef DEV_ISA 1857#ifdef DEV_ATPIC 1858 elcr_probe(); 1859 atpic_startup(); 1860#else 1861 /* Reset and mask the atpics and leave them shut down. */ 1862 atpic_reset(); 1863 1864 /* 1865 * Point the ICU spurious interrupt vectors at the APIC spurious 1866 * interrupt handler. 1867 */ 1868 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1869 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1870#endif 1871#else 1872#error "have you forgotten the isa device?"; 1873#endif 1874 1875 kdb_init(); 1876 1877#ifdef KDB 1878 if (boothowto & RB_KDB) 1879 kdb_enter(KDB_WHY_BOOTFLAGS, 1880 "Boot flags requested debugger"); 1881#endif 1882 1883 identify_cpu(); /* Final stage of CPU initialization */ 1884 initializecpu(); /* Initialize CPU registers */ 1885 initializecpucache(); 1886 1887 /* doublefault stack space, runs on ist1 */ 1888 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1889 1890 /* 1891 * NMI stack, runs on ist2. The pcpu pointer is stored just 1892 * above the start of the ist2 stack. 1893 */ 1894 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1895 np->np_pcpu = (register_t) pc; 1896 common_tss[0].tss_ist2 = (long) np; 1897 1898 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1899 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1900 IOPAGES * PAGE_SIZE; 1901 1902 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1903 ltr(gsel_tss); 1904 1905 /* Set up the fast syscall stuff */ 1906 msr = rdmsr(MSR_EFER) | EFER_SCE; 1907 wrmsr(MSR_EFER, msr); 1908 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1909 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1910 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1911 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1912 wrmsr(MSR_STAR, msr); 1913 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1914 1915 getmemsize(kmdp, physfree); 1916 init_param2(physmem); 1917 1918 /* now running on new page tables, configured,and u/iom is accessible */ 1919 1920 msgbufinit(msgbufp, msgbufsize); 1921 fpuinit(); 1922 1923 /* 1924 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1925 * area size. Zero out the extended state header in fpu save 1926 * area. 1927 */ 1928 thread0.td_pcb = get_pcb_td(&thread0); 1929 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1930 if (use_xsave) { 1931 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1932 1); 1933 xhdr->xstate_bv = xsave_mask; 1934 } 1935 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1936 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1937 /* Ensure the stack is aligned to 16 bytes */ 1938 common_tss[0].tss_rsp0 &= ~0xFul; 1939 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1940 PCPU_SET(curpcb, thread0.td_pcb); 1941 1942 /* transfer to user mode */ 1943 1944 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1945 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1946 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1947 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1948 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1949 1950 load_ds(_udatasel); 1951 load_es(_udatasel); 1952 load_fs(_ufssel); 1953 1954 /* setup proc 0's pcb */ 1955 thread0.td_pcb->pcb_flags = 0; 1956 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 1957 thread0.td_frame = &proc0_tf; 1958 1959 env = getenv("kernelname"); 1960 if (env != NULL) 1961 strlcpy(kernelname, env, sizeof(kernelname)); 1962 1963 cpu_probe_amdc1e(); 1964 1965#ifdef FDT 1966 x86_init_fdt(); 1967#endif 1968 1969 /* Location of kernel stack for locore */ 1970 return ((u_int64_t)thread0.td_pcb); 1971} 1972 1973void 1974cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1975{ 1976 1977 pcpu->pc_acpi_id = 0xffffffff; 1978} 1979 1980void 1981spinlock_enter(void) 1982{ 1983 struct thread *td; 1984 register_t flags; 1985 1986 td = curthread; 1987 if (td->td_md.md_spinlock_count == 0) { 1988 flags = intr_disable(); 1989 td->td_md.md_spinlock_count = 1; 1990 td->td_md.md_saved_flags = flags; 1991 } else 1992 td->td_md.md_spinlock_count++; 1993 critical_enter(); 1994} 1995 1996void 1997spinlock_exit(void) 1998{ 1999 struct thread *td; 2000 register_t flags; 2001 2002 td = curthread; 2003 critical_exit(); 2004 flags = td->td_md.md_saved_flags; 2005 td->td_md.md_spinlock_count--; 2006 if (td->td_md.md_spinlock_count == 0) 2007 intr_restore(flags); 2008} 2009 2010/* 2011 * Construct a PCB from a trapframe. This is called from kdb_trap() where 2012 * we want to start a backtrace from the function that caused us to enter 2013 * the debugger. We have the context in the trapframe, but base the trace 2014 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 2015 * enough for a backtrace. 2016 */ 2017void 2018makectx(struct trapframe *tf, struct pcb *pcb) 2019{ 2020 2021 pcb->pcb_r12 = tf->tf_r12; 2022 pcb->pcb_r13 = tf->tf_r13; 2023 pcb->pcb_r14 = tf->tf_r14; 2024 pcb->pcb_r15 = tf->tf_r15; 2025 pcb->pcb_rbp = tf->tf_rbp; 2026 pcb->pcb_rbx = tf->tf_rbx; 2027 pcb->pcb_rip = tf->tf_rip; 2028 pcb->pcb_rsp = tf->tf_rsp; 2029} 2030 2031int 2032ptrace_set_pc(struct thread *td, unsigned long addr) 2033{ 2034 td->td_frame->tf_rip = addr; 2035 return (0); 2036} 2037 2038int 2039ptrace_single_step(struct thread *td) 2040{ 2041 td->td_frame->tf_rflags |= PSL_T; 2042 return (0); 2043} 2044 2045int 2046ptrace_clear_single_step(struct thread *td) 2047{ 2048 td->td_frame->tf_rflags &= ~PSL_T; 2049 return (0); 2050} 2051 2052int 2053fill_regs(struct thread *td, struct reg *regs) 2054{ 2055 struct trapframe *tp; 2056 2057 tp = td->td_frame; 2058 return (fill_frame_regs(tp, regs)); 2059} 2060 2061int 2062fill_frame_regs(struct trapframe *tp, struct reg *regs) 2063{ 2064 regs->r_r15 = tp->tf_r15; 2065 regs->r_r14 = tp->tf_r14; 2066 regs->r_r13 = tp->tf_r13; 2067 regs->r_r12 = tp->tf_r12; 2068 regs->r_r11 = tp->tf_r11; 2069 regs->r_r10 = tp->tf_r10; 2070 regs->r_r9 = tp->tf_r9; 2071 regs->r_r8 = tp->tf_r8; 2072 regs->r_rdi = tp->tf_rdi; 2073 regs->r_rsi = tp->tf_rsi; 2074 regs->r_rbp = tp->tf_rbp; 2075 regs->r_rbx = tp->tf_rbx; 2076 regs->r_rdx = tp->tf_rdx; 2077 regs->r_rcx = tp->tf_rcx; 2078 regs->r_rax = tp->tf_rax; 2079 regs->r_rip = tp->tf_rip; 2080 regs->r_cs = tp->tf_cs; 2081 regs->r_rflags = tp->tf_rflags; 2082 regs->r_rsp = tp->tf_rsp; 2083 regs->r_ss = tp->tf_ss; 2084 if (tp->tf_flags & TF_HASSEGS) { 2085 regs->r_ds = tp->tf_ds; 2086 regs->r_es = tp->tf_es; 2087 regs->r_fs = tp->tf_fs; 2088 regs->r_gs = tp->tf_gs; 2089 } else { 2090 regs->r_ds = 0; 2091 regs->r_es = 0; 2092 regs->r_fs = 0; 2093 regs->r_gs = 0; 2094 } 2095 return (0); 2096} 2097 2098int 2099set_regs(struct thread *td, struct reg *regs) 2100{ 2101 struct trapframe *tp; 2102 register_t rflags; 2103 2104 tp = td->td_frame; 2105 rflags = regs->r_rflags & 0xffffffff; 2106 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2107 return (EINVAL); 2108 tp->tf_r15 = regs->r_r15; 2109 tp->tf_r14 = regs->r_r14; 2110 tp->tf_r13 = regs->r_r13; 2111 tp->tf_r12 = regs->r_r12; 2112 tp->tf_r11 = regs->r_r11; 2113 tp->tf_r10 = regs->r_r10; 2114 tp->tf_r9 = regs->r_r9; 2115 tp->tf_r8 = regs->r_r8; 2116 tp->tf_rdi = regs->r_rdi; 2117 tp->tf_rsi = regs->r_rsi; 2118 tp->tf_rbp = regs->r_rbp; 2119 tp->tf_rbx = regs->r_rbx; 2120 tp->tf_rdx = regs->r_rdx; 2121 tp->tf_rcx = regs->r_rcx; 2122 tp->tf_rax = regs->r_rax; 2123 tp->tf_rip = regs->r_rip; 2124 tp->tf_cs = regs->r_cs; 2125 tp->tf_rflags = rflags; 2126 tp->tf_rsp = regs->r_rsp; 2127 tp->tf_ss = regs->r_ss; 2128 if (0) { /* XXXKIB */ 2129 tp->tf_ds = regs->r_ds; 2130 tp->tf_es = regs->r_es; 2131 tp->tf_fs = regs->r_fs; 2132 tp->tf_gs = regs->r_gs; 2133 tp->tf_flags = TF_HASSEGS; 2134 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2135 } 2136 return (0); 2137} 2138 2139/* XXX check all this stuff! */ 2140/* externalize from sv_xmm */ 2141static void 2142fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2143{ 2144 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2145 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2146 int i; 2147 2148 /* pcb -> fpregs */ 2149 bzero(fpregs, sizeof(*fpregs)); 2150 2151 /* FPU control/status */ 2152 penv_fpreg->en_cw = penv_xmm->en_cw; 2153 penv_fpreg->en_sw = penv_xmm->en_sw; 2154 penv_fpreg->en_tw = penv_xmm->en_tw; 2155 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2156 penv_fpreg->en_rip = penv_xmm->en_rip; 2157 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2158 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2159 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2160 2161 /* FPU registers */ 2162 for (i = 0; i < 8; ++i) 2163 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2164 2165 /* SSE registers */ 2166 for (i = 0; i < 16; ++i) 2167 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2168} 2169 2170/* internalize from fpregs into sv_xmm */ 2171static void 2172set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2173{ 2174 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2175 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2176 int i; 2177 2178 /* fpregs -> pcb */ 2179 /* FPU control/status */ 2180 penv_xmm->en_cw = penv_fpreg->en_cw; 2181 penv_xmm->en_sw = penv_fpreg->en_sw; 2182 penv_xmm->en_tw = penv_fpreg->en_tw; 2183 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2184 penv_xmm->en_rip = penv_fpreg->en_rip; 2185 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2186 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2187 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2188 2189 /* FPU registers */ 2190 for (i = 0; i < 8; ++i) 2191 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2192 2193 /* SSE registers */ 2194 for (i = 0; i < 16; ++i) 2195 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2196} 2197 2198/* externalize from td->pcb */ 2199int 2200fill_fpregs(struct thread *td, struct fpreg *fpregs) 2201{ 2202 2203 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2204 P_SHOULDSTOP(td->td_proc), 2205 ("not suspended thread %p", td)); 2206 fpugetregs(td); 2207 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2208 return (0); 2209} 2210 2211/* internalize to td->pcb */ 2212int 2213set_fpregs(struct thread *td, struct fpreg *fpregs) 2214{ 2215 2216 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2217 fpuuserinited(td); 2218 return (0); 2219} 2220 2221/* 2222 * Get machine context. 2223 */ 2224int 2225get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2226{ 2227 struct pcb *pcb; 2228 struct trapframe *tp; 2229 2230 pcb = td->td_pcb; 2231 tp = td->td_frame; 2232 PROC_LOCK(curthread->td_proc); 2233 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2234 PROC_UNLOCK(curthread->td_proc); 2235 mcp->mc_r15 = tp->tf_r15; 2236 mcp->mc_r14 = tp->tf_r14; 2237 mcp->mc_r13 = tp->tf_r13; 2238 mcp->mc_r12 = tp->tf_r12; 2239 mcp->mc_r11 = tp->tf_r11; 2240 mcp->mc_r10 = tp->tf_r10; 2241 mcp->mc_r9 = tp->tf_r9; 2242 mcp->mc_r8 = tp->tf_r8; 2243 mcp->mc_rdi = tp->tf_rdi; 2244 mcp->mc_rsi = tp->tf_rsi; 2245 mcp->mc_rbp = tp->tf_rbp; 2246 mcp->mc_rbx = tp->tf_rbx; 2247 mcp->mc_rcx = tp->tf_rcx; 2248 mcp->mc_rflags = tp->tf_rflags; 2249 if (flags & GET_MC_CLEAR_RET) { 2250 mcp->mc_rax = 0; 2251 mcp->mc_rdx = 0; 2252 mcp->mc_rflags &= ~PSL_C; 2253 } else { 2254 mcp->mc_rax = tp->tf_rax; 2255 mcp->mc_rdx = tp->tf_rdx; 2256 } 2257 mcp->mc_rip = tp->tf_rip; 2258 mcp->mc_cs = tp->tf_cs; 2259 mcp->mc_rsp = tp->tf_rsp; 2260 mcp->mc_ss = tp->tf_ss; 2261 mcp->mc_ds = tp->tf_ds; 2262 mcp->mc_es = tp->tf_es; 2263 mcp->mc_fs = tp->tf_fs; 2264 mcp->mc_gs = tp->tf_gs; 2265 mcp->mc_flags = tp->tf_flags; 2266 mcp->mc_len = sizeof(*mcp); 2267 get_fpcontext(td, mcp, NULL, 0); 2268 mcp->mc_fsbase = pcb->pcb_fsbase; 2269 mcp->mc_gsbase = pcb->pcb_gsbase; 2270 mcp->mc_xfpustate = 0; 2271 mcp->mc_xfpustate_len = 0; 2272 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2273 return (0); 2274} 2275 2276/* 2277 * Set machine context. 2278 * 2279 * However, we don't set any but the user modifiable flags, and we won't 2280 * touch the cs selector. 2281 */ 2282int 2283set_mcontext(struct thread *td, const mcontext_t *mcp) 2284{ 2285 struct pcb *pcb; 2286 struct trapframe *tp; 2287 char *xfpustate; 2288 long rflags; 2289 int ret; 2290 2291 pcb = td->td_pcb; 2292 tp = td->td_frame; 2293 if (mcp->mc_len != sizeof(*mcp) || 2294 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2295 return (EINVAL); 2296 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2297 (tp->tf_rflags & ~PSL_USERCHANGE); 2298 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2299 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2300 sizeof(struct savefpu)) 2301 return (EINVAL); 2302 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2303 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2304 mcp->mc_xfpustate_len); 2305 if (ret != 0) 2306 return (ret); 2307 } else 2308 xfpustate = NULL; 2309 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2310 if (ret != 0) 2311 return (ret); 2312 tp->tf_r15 = mcp->mc_r15; 2313 tp->tf_r14 = mcp->mc_r14; 2314 tp->tf_r13 = mcp->mc_r13; 2315 tp->tf_r12 = mcp->mc_r12; 2316 tp->tf_r11 = mcp->mc_r11; 2317 tp->tf_r10 = mcp->mc_r10; 2318 tp->tf_r9 = mcp->mc_r9; 2319 tp->tf_r8 = mcp->mc_r8; 2320 tp->tf_rdi = mcp->mc_rdi; 2321 tp->tf_rsi = mcp->mc_rsi; 2322 tp->tf_rbp = mcp->mc_rbp; 2323 tp->tf_rbx = mcp->mc_rbx; 2324 tp->tf_rdx = mcp->mc_rdx; 2325 tp->tf_rcx = mcp->mc_rcx; 2326 tp->tf_rax = mcp->mc_rax; 2327 tp->tf_rip = mcp->mc_rip; 2328 tp->tf_rflags = rflags; 2329 tp->tf_rsp = mcp->mc_rsp; 2330 tp->tf_ss = mcp->mc_ss; 2331 tp->tf_flags = mcp->mc_flags; 2332 if (tp->tf_flags & TF_HASSEGS) { 2333 tp->tf_ds = mcp->mc_ds; 2334 tp->tf_es = mcp->mc_es; 2335 tp->tf_fs = mcp->mc_fs; 2336 tp->tf_gs = mcp->mc_gs; 2337 } 2338 if (mcp->mc_flags & _MC_HASBASES) { 2339 pcb->pcb_fsbase = mcp->mc_fsbase; 2340 pcb->pcb_gsbase = mcp->mc_gsbase; 2341 } 2342 set_pcb_flags(pcb, PCB_FULL_IRET); 2343 return (0); 2344} 2345 2346static void 2347get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2348 size_t xfpusave_len) 2349{ 2350 size_t max_len, len; 2351 2352 mcp->mc_ownedfp = fpugetregs(td); 2353 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2354 sizeof(mcp->mc_fpstate)); 2355 mcp->mc_fpformat = fpuformat(); 2356 if (!use_xsave || xfpusave_len == 0) 2357 return; 2358 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2359 len = xfpusave_len; 2360 if (len > max_len) { 2361 len = max_len; 2362 bzero(xfpusave + max_len, len - max_len); 2363 } 2364 mcp->mc_flags |= _MC_HASFPXSTATE; 2365 mcp->mc_xfpustate_len = len; 2366 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2367} 2368 2369static int 2370set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2371 size_t xfpustate_len) 2372{ 2373 struct savefpu *fpstate; 2374 int error; 2375 2376 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2377 return (0); 2378 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2379 return (EINVAL); 2380 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2381 /* We don't care what state is left in the FPU or PCB. */ 2382 fpstate_drop(td); 2383 error = 0; 2384 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2385 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2386 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2387 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2388 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2389 } else 2390 return (EINVAL); 2391 return (error); 2392} 2393 2394void 2395fpstate_drop(struct thread *td) 2396{ 2397 2398 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2399 critical_enter(); 2400 if (PCPU_GET(fpcurthread) == td) 2401 fpudrop(); 2402 /* 2403 * XXX force a full drop of the fpu. The above only drops it if we 2404 * owned it. 2405 * 2406 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2407 * drop. Dropping only to the pcb matches fnsave's behaviour. 2408 * We only need to drop to !PCB_INITDONE in sendsig(). But 2409 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2410 * have too many layers. 2411 */ 2412 clear_pcb_flags(curthread->td_pcb, 2413 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2414 critical_exit(); 2415} 2416 2417int 2418fill_dbregs(struct thread *td, struct dbreg *dbregs) 2419{ 2420 struct pcb *pcb; 2421 2422 if (td == NULL) { 2423 dbregs->dr[0] = rdr0(); 2424 dbregs->dr[1] = rdr1(); 2425 dbregs->dr[2] = rdr2(); 2426 dbregs->dr[3] = rdr3(); 2427 dbregs->dr[6] = rdr6(); 2428 dbregs->dr[7] = rdr7(); 2429 } else { 2430 pcb = td->td_pcb; 2431 dbregs->dr[0] = pcb->pcb_dr0; 2432 dbregs->dr[1] = pcb->pcb_dr1; 2433 dbregs->dr[2] = pcb->pcb_dr2; 2434 dbregs->dr[3] = pcb->pcb_dr3; 2435 dbregs->dr[6] = pcb->pcb_dr6; 2436 dbregs->dr[7] = pcb->pcb_dr7; 2437 } 2438 dbregs->dr[4] = 0; 2439 dbregs->dr[5] = 0; 2440 dbregs->dr[8] = 0; 2441 dbregs->dr[9] = 0; 2442 dbregs->dr[10] = 0; 2443 dbregs->dr[11] = 0; 2444 dbregs->dr[12] = 0; 2445 dbregs->dr[13] = 0; 2446 dbregs->dr[14] = 0; 2447 dbregs->dr[15] = 0; 2448 return (0); 2449} 2450 2451int 2452set_dbregs(struct thread *td, struct dbreg *dbregs) 2453{ 2454 struct pcb *pcb; 2455 int i; 2456 2457 if (td == NULL) { 2458 load_dr0(dbregs->dr[0]); 2459 load_dr1(dbregs->dr[1]); 2460 load_dr2(dbregs->dr[2]); 2461 load_dr3(dbregs->dr[3]); 2462 load_dr6(dbregs->dr[6]); 2463 load_dr7(dbregs->dr[7]); 2464 } else { 2465 /* 2466 * Don't let an illegal value for dr7 get set. Specifically, 2467 * check for undefined settings. Setting these bit patterns 2468 * result in undefined behaviour and can lead to an unexpected 2469 * TRCTRAP or a general protection fault right here. 2470 * Upper bits of dr6 and dr7 must not be set 2471 */ 2472 for (i = 0; i < 4; i++) { 2473 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2474 return (EINVAL); 2475 if (td->td_frame->tf_cs == _ucode32sel && 2476 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2477 return (EINVAL); 2478 } 2479 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2480 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2481 return (EINVAL); 2482 2483 pcb = td->td_pcb; 2484 2485 /* 2486 * Don't let a process set a breakpoint that is not within the 2487 * process's address space. If a process could do this, it 2488 * could halt the system by setting a breakpoint in the kernel 2489 * (if ddb was enabled). Thus, we need to check to make sure 2490 * that no breakpoints are being enabled for addresses outside 2491 * process's address space. 2492 * 2493 * XXX - what about when the watched area of the user's 2494 * address space is written into from within the kernel 2495 * ... wouldn't that still cause a breakpoint to be generated 2496 * from within kernel mode? 2497 */ 2498 2499 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2500 /* dr0 is enabled */ 2501 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2502 return (EINVAL); 2503 } 2504 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2505 /* dr1 is enabled */ 2506 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2507 return (EINVAL); 2508 } 2509 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2510 /* dr2 is enabled */ 2511 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2512 return (EINVAL); 2513 } 2514 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2515 /* dr3 is enabled */ 2516 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2517 return (EINVAL); 2518 } 2519 2520 pcb->pcb_dr0 = dbregs->dr[0]; 2521 pcb->pcb_dr1 = dbregs->dr[1]; 2522 pcb->pcb_dr2 = dbregs->dr[2]; 2523 pcb->pcb_dr3 = dbregs->dr[3]; 2524 pcb->pcb_dr6 = dbregs->dr[6]; 2525 pcb->pcb_dr7 = dbregs->dr[7]; 2526 2527 set_pcb_flags(pcb, PCB_DBREGS); 2528 } 2529 2530 return (0); 2531} 2532 2533void 2534reset_dbregs(void) 2535{ 2536 2537 load_dr7(0); /* Turn off the control bits first */ 2538 load_dr0(0); 2539 load_dr1(0); 2540 load_dr2(0); 2541 load_dr3(0); 2542 load_dr6(0); 2543} 2544 2545/* 2546 * Return > 0 if a hardware breakpoint has been hit, and the 2547 * breakpoint was in user space. Return 0, otherwise. 2548 */ 2549int 2550user_dbreg_trap(void) 2551{ 2552 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2553 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2554 int nbp; /* number of breakpoints that triggered */ 2555 caddr_t addr[4]; /* breakpoint addresses */ 2556 int i; 2557 2558 dr7 = rdr7(); 2559 if ((dr7 & 0x000000ff) == 0) { 2560 /* 2561 * all GE and LE bits in the dr7 register are zero, 2562 * thus the trap couldn't have been caused by the 2563 * hardware debug registers 2564 */ 2565 return 0; 2566 } 2567 2568 nbp = 0; 2569 dr6 = rdr6(); 2570 bp = dr6 & 0x0000000f; 2571 2572 if (!bp) { 2573 /* 2574 * None of the breakpoint bits are set meaning this 2575 * trap was not caused by any of the debug registers 2576 */ 2577 return 0; 2578 } 2579 2580 /* 2581 * at least one of the breakpoints were hit, check to see 2582 * which ones and if any of them are user space addresses 2583 */ 2584 2585 if (bp & 0x01) { 2586 addr[nbp++] = (caddr_t)rdr0(); 2587 } 2588 if (bp & 0x02) { 2589 addr[nbp++] = (caddr_t)rdr1(); 2590 } 2591 if (bp & 0x04) { 2592 addr[nbp++] = (caddr_t)rdr2(); 2593 } 2594 if (bp & 0x08) { 2595 addr[nbp++] = (caddr_t)rdr3(); 2596 } 2597 2598 for (i = 0; i < nbp; i++) { 2599 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2600 /* 2601 * addr[i] is in user space 2602 */ 2603 return nbp; 2604 } 2605 } 2606 2607 /* 2608 * None of the breakpoints are in user space. 2609 */ 2610 return 0; 2611} 2612 2613#ifdef KDB 2614 2615/* 2616 * Provide inb() and outb() as functions. They are normally only available as 2617 * inline functions, thus cannot be called from the debugger. 2618 */ 2619 2620/* silence compiler warnings */ 2621u_char inb_(u_short); 2622void outb_(u_short, u_char); 2623 2624u_char 2625inb_(u_short port) 2626{ 2627 return inb(port); 2628} 2629 2630void 2631outb_(u_short port, u_char data) 2632{ 2633 outb(port, data); 2634} 2635 2636#endif /* KDB */ 2637