machdep.c revision 263006
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 263006 2014-03-11 10:15:25Z royger $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_mp_watchdog.h" 55#include "opt_perfmon.h" 56#include "opt_platform.h" 57#include "opt_sched.h" 58 59#include <sys/param.h> 60#include <sys/proc.h> 61#include <sys/systm.h> 62#include <sys/bio.h> 63#include <sys/buf.h> 64#include <sys/bus.h> 65#include <sys/callout.h> 66#include <sys/cons.h> 67#include <sys/cpu.h> 68#include <sys/eventhandler.h> 69#include <sys/exec.h> 70#include <sys/imgact.h> 71#include <sys/kdb.h> 72#include <sys/kernel.h> 73#include <sys/ktr.h> 74#include <sys/linker.h> 75#include <sys/lock.h> 76#include <sys/malloc.h> 77#include <sys/memrange.h> 78#include <sys/msgbuf.h> 79#include <sys/mutex.h> 80#include <sys/pcpu.h> 81#include <sys/ptrace.h> 82#include <sys/reboot.h> 83#include <sys/rwlock.h> 84#include <sys/sched.h> 85#include <sys/signalvar.h> 86#ifdef SMP 87#include <sys/smp.h> 88#endif 89#include <sys/syscallsubr.h> 90#include <sys/sysctl.h> 91#include <sys/sysent.h> 92#include <sys/sysproto.h> 93#include <sys/ucontext.h> 94#include <sys/vmmeter.h> 95 96#include <vm/vm.h> 97#include <vm/vm_extern.h> 98#include <vm/vm_kern.h> 99#include <vm/vm_page.h> 100#include <vm/vm_map.h> 101#include <vm/vm_object.h> 102#include <vm/vm_pager.h> 103#include <vm/vm_param.h> 104 105#ifdef DDB 106#ifndef KDB 107#error KDB must be enabled in order for DDB to work! 108#endif 109#include <ddb/ddb.h> 110#include <ddb/db_sym.h> 111#endif 112 113#include <net/netisr.h> 114 115#include <machine/clock.h> 116#include <machine/cpu.h> 117#include <machine/cputypes.h> 118#include <machine/intr_machdep.h> 119#include <x86/mca.h> 120#include <machine/md_var.h> 121#include <machine/metadata.h> 122#include <machine/mp_watchdog.h> 123#include <machine/pc/bios.h> 124#include <machine/pcb.h> 125#include <machine/proc.h> 126#include <machine/reg.h> 127#include <machine/sigframe.h> 128#include <machine/specialreg.h> 129#ifdef PERFMON 130#include <machine/perfmon.h> 131#endif 132#include <machine/tss.h> 133#ifdef SMP 134#include <machine/smp.h> 135#endif 136#ifdef FDT 137#include <x86/fdt.h> 138#endif 139 140#ifdef DEV_ATPIC 141#include <x86/isa/icu.h> 142#else 143#include <x86/apicvar.h> 144#endif 145 146#include <isa/isareg.h> 147#include <isa/rtc.h> 148#include <x86/init.h> 149 150/* Sanity check for __curthread() */ 151CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 152 153extern u_int64_t hammer_time(u_int64_t, u_int64_t); 154 155extern void printcpuinfo(void); /* XXX header file */ 156extern void identify_cpu(void); 157extern void panicifcpuunsupported(void); 158 159#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 160#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 161 162static void cpu_startup(void *); 163static void get_fpcontext(struct thread *td, mcontext_t *mcp, 164 char *xfpusave, size_t xfpusave_len); 165static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 166 char *xfpustate, size_t xfpustate_len); 167SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 168 169/* Preload data parse function */ 170static caddr_t native_parse_preload_data(u_int64_t); 171 172/* Default init_ops implementation. */ 173struct init_ops init_ops = { 174 .parse_preload_data = native_parse_preload_data, 175}; 176 177/* 178 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 179 * the physical address at which the kernel is loaded. 180 */ 181extern char kernphys[]; 182#ifdef DDB 183extern vm_offset_t ksym_start, ksym_end; 184#endif 185 186struct msgbuf *msgbufp; 187 188/* Intel ICH registers */ 189#define ICH_PMBASE 0x400 190#define ICH_SMI_EN ICH_PMBASE + 0x30 191 192int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 193 194int cold = 1; 195 196long Maxmem = 0; 197long realmem = 0; 198 199/* 200 * The number of PHYSMAP entries must be one less than the number of 201 * PHYSSEG entries because the PHYSMAP entry that spans the largest 202 * physical address that is accessible by ISA DMA is split into two 203 * PHYSSEG entries. 204 */ 205#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 206 207vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 208vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 209 210/* must be 2 less so 0 0 can signal end of chunks */ 211#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 212#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 213 214struct kva_md_info kmi; 215 216static struct trapframe proc0_tf; 217struct region_descriptor r_gdt, r_idt; 218 219struct pcpu __pcpu[MAXCPU]; 220 221struct mtx icu_lock; 222 223struct mem_range_softc mem_range_softc; 224 225struct mtx dt_lock; /* lock for GDT and LDT */ 226 227void (*vmm_resume_p)(void); 228 229static void 230cpu_startup(dummy) 231 void *dummy; 232{ 233 uintmax_t memsize; 234 char *sysenv; 235 236 /* 237 * On MacBooks, we need to disallow the legacy USB circuit to 238 * generate an SMI# because this can cause several problems, 239 * namely: incorrect CPU frequency detection and failure to 240 * start the APs. 241 * We do this by disabling a bit in the SMI_EN (SMI Control and 242 * Enable register) of the Intel ICH LPC Interface Bridge. 243 */ 244 sysenv = getenv("smbios.system.product"); 245 if (sysenv != NULL) { 246 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 247 strncmp(sysenv, "MacBook3,1", 10) == 0 || 248 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 249 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 250 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 251 strncmp(sysenv, "Macmini1,1", 10) == 0) { 252 if (bootverbose) 253 printf("Disabling LEGACY_USB_EN bit on " 254 "Intel ICH.\n"); 255 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 256 } 257 freeenv(sysenv); 258 } 259 260 /* 261 * Good {morning,afternoon,evening,night}. 262 */ 263 startrtclock(); 264 printcpuinfo(); 265 panicifcpuunsupported(); 266#ifdef PERFMON 267 perfmon_init(); 268#endif 269 270 /* 271 * Display physical memory if SMBIOS reports reasonable amount. 272 */ 273 memsize = 0; 274 sysenv = getenv("smbios.memory.enabled"); 275 if (sysenv != NULL) { 276 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 277 freeenv(sysenv); 278 } 279 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 280 memsize = ptoa((uintmax_t)Maxmem); 281 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 282 realmem = atop(memsize); 283 284 /* 285 * Display any holes after the first chunk of extended memory. 286 */ 287 if (bootverbose) { 288 int indx; 289 290 printf("Physical memory chunk(s):\n"); 291 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 292 vm_paddr_t size; 293 294 size = phys_avail[indx + 1] - phys_avail[indx]; 295 printf( 296 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 297 (uintmax_t)phys_avail[indx], 298 (uintmax_t)phys_avail[indx + 1] - 1, 299 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 300 } 301 } 302 303 vm_ksubmap_init(&kmi); 304 305 printf("avail memory = %ju (%ju MB)\n", 306 ptoa((uintmax_t)cnt.v_free_count), 307 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 308 309 /* 310 * Set up buffers, so they can be used to read disk labels. 311 */ 312 bufinit(); 313 vm_pager_bufferinit(); 314 315 cpu_setregs(); 316} 317 318/* 319 * Send an interrupt to process. 320 * 321 * Stack is set up to allow sigcode stored 322 * at top to call routine, followed by call 323 * to sigreturn routine below. After sigreturn 324 * resets the signal mask, the stack, and the 325 * frame pointer, it returns to the user 326 * specified pc, psl. 327 */ 328void 329sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 330{ 331 struct sigframe sf, *sfp; 332 struct pcb *pcb; 333 struct proc *p; 334 struct thread *td; 335 struct sigacts *psp; 336 char *sp; 337 struct trapframe *regs; 338 char *xfpusave; 339 size_t xfpusave_len; 340 int sig; 341 int oonstack; 342 343 td = curthread; 344 pcb = td->td_pcb; 345 p = td->td_proc; 346 PROC_LOCK_ASSERT(p, MA_OWNED); 347 sig = ksi->ksi_signo; 348 psp = p->p_sigacts; 349 mtx_assert(&psp->ps_mtx, MA_OWNED); 350 regs = td->td_frame; 351 oonstack = sigonstack(regs->tf_rsp); 352 353 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 354 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 355 xfpusave = __builtin_alloca(xfpusave_len); 356 } else { 357 xfpusave_len = 0; 358 xfpusave = NULL; 359 } 360 361 /* Save user context. */ 362 bzero(&sf, sizeof(sf)); 363 sf.sf_uc.uc_sigmask = *mask; 364 sf.sf_uc.uc_stack = td->td_sigstk; 365 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 366 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 367 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 368 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 369 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 370 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 371 fpstate_drop(td); 372 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 373 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 374 bzero(sf.sf_uc.uc_mcontext.mc_spare, 375 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 376 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 377 378 /* Allocate space for the signal handler context. */ 379 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 380 SIGISMEMBER(psp->ps_sigonstack, sig)) { 381 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 382#if defined(COMPAT_43) 383 td->td_sigstk.ss_flags |= SS_ONSTACK; 384#endif 385 } else 386 sp = (char *)regs->tf_rsp - 128; 387 if (xfpusave != NULL) { 388 sp -= xfpusave_len; 389 sp = (char *)((unsigned long)sp & ~0x3Ful); 390 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 391 } 392 sp -= sizeof(struct sigframe); 393 /* Align to 16 bytes. */ 394 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 395 396 /* Translate the signal if appropriate. */ 397 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 398 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 399 400 /* Build the argument list for the signal handler. */ 401 regs->tf_rdi = sig; /* arg 1 in %rdi */ 402 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 403 bzero(&sf.sf_si, sizeof(sf.sf_si)); 404 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 405 /* Signal handler installed with SA_SIGINFO. */ 406 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 407 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 408 409 /* Fill in POSIX parts */ 410 sf.sf_si = ksi->ksi_info; 411 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 412 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 413 } else { 414 /* Old FreeBSD-style arguments. */ 415 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 416 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 417 sf.sf_ahu.sf_handler = catcher; 418 } 419 mtx_unlock(&psp->ps_mtx); 420 PROC_UNLOCK(p); 421 422 /* 423 * Copy the sigframe out to the user's stack. 424 */ 425 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 426 (xfpusave != NULL && copyout(xfpusave, 427 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 428 != 0)) { 429#ifdef DEBUG 430 printf("process %ld has trashed its stack\n", (long)p->p_pid); 431#endif 432 PROC_LOCK(p); 433 sigexit(td, SIGILL); 434 } 435 436 regs->tf_rsp = (long)sfp; 437 regs->tf_rip = p->p_sysent->sv_sigcode_base; 438 regs->tf_rflags &= ~(PSL_T | PSL_D); 439 regs->tf_cs = _ucodesel; 440 regs->tf_ds = _udatasel; 441 regs->tf_es = _udatasel; 442 regs->tf_fs = _ufssel; 443 regs->tf_gs = _ugssel; 444 regs->tf_flags = TF_HASSEGS; 445 set_pcb_flags(pcb, PCB_FULL_IRET); 446 PROC_LOCK(p); 447 mtx_lock(&psp->ps_mtx); 448} 449 450/* 451 * System call to cleanup state after a signal 452 * has been taken. Reset signal mask and 453 * stack state from context left by sendsig (above). 454 * Return to previous pc and psl as specified by 455 * context left by sendsig. Check carefully to 456 * make sure that the user has not modified the 457 * state to gain improper privileges. 458 * 459 * MPSAFE 460 */ 461int 462sys_sigreturn(td, uap) 463 struct thread *td; 464 struct sigreturn_args /* { 465 const struct __ucontext *sigcntxp; 466 } */ *uap; 467{ 468 ucontext_t uc; 469 struct pcb *pcb; 470 struct proc *p; 471 struct trapframe *regs; 472 ucontext_t *ucp; 473 char *xfpustate; 474 size_t xfpustate_len; 475 long rflags; 476 int cs, error, ret; 477 ksiginfo_t ksi; 478 479 pcb = td->td_pcb; 480 p = td->td_proc; 481 482 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 483 if (error != 0) { 484 uprintf("pid %d (%s): sigreturn copyin failed\n", 485 p->p_pid, td->td_name); 486 return (error); 487 } 488 ucp = &uc; 489 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 490 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 491 td->td_name, ucp->uc_mcontext.mc_flags); 492 return (EINVAL); 493 } 494 regs = td->td_frame; 495 rflags = ucp->uc_mcontext.mc_rflags; 496 /* 497 * Don't allow users to change privileged or reserved flags. 498 */ 499 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 500 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 501 td->td_name, rflags); 502 return (EINVAL); 503 } 504 505 /* 506 * Don't allow users to load a valid privileged %cs. Let the 507 * hardware check for invalid selectors, excess privilege in 508 * other selectors, invalid %eip's and invalid %esp's. 509 */ 510 cs = ucp->uc_mcontext.mc_cs; 511 if (!CS_SECURE(cs)) { 512 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 513 td->td_name, cs); 514 ksiginfo_init_trap(&ksi); 515 ksi.ksi_signo = SIGBUS; 516 ksi.ksi_code = BUS_OBJERR; 517 ksi.ksi_trapno = T_PROTFLT; 518 ksi.ksi_addr = (void *)regs->tf_rip; 519 trapsignal(td, &ksi); 520 return (EINVAL); 521 } 522 523 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 524 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 525 if (xfpustate_len > cpu_max_ext_state_size - 526 sizeof(struct savefpu)) { 527 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 528 p->p_pid, td->td_name, xfpustate_len); 529 return (EINVAL); 530 } 531 xfpustate = __builtin_alloca(xfpustate_len); 532 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 533 xfpustate, xfpustate_len); 534 if (error != 0) { 535 uprintf( 536 "pid %d (%s): sigreturn copying xfpustate failed\n", 537 p->p_pid, td->td_name); 538 return (error); 539 } 540 } else { 541 xfpustate = NULL; 542 xfpustate_len = 0; 543 } 544 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 545 if (ret != 0) { 546 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 547 p->p_pid, td->td_name, ret); 548 return (ret); 549 } 550 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 551 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 552 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 553 554#if defined(COMPAT_43) 555 if (ucp->uc_mcontext.mc_onstack & 1) 556 td->td_sigstk.ss_flags |= SS_ONSTACK; 557 else 558 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 559#endif 560 561 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 562 set_pcb_flags(pcb, PCB_FULL_IRET); 563 return (EJUSTRETURN); 564} 565 566#ifdef COMPAT_FREEBSD4 567int 568freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 569{ 570 571 return sys_sigreturn(td, (struct sigreturn_args *)uap); 572} 573#endif 574 575 576/* 577 * Machine dependent boot() routine 578 * 579 * I haven't seen anything to put here yet 580 * Possibly some stuff might be grafted back here from boot() 581 */ 582void 583cpu_boot(int howto) 584{ 585} 586 587/* 588 * Flush the D-cache for non-DMA I/O so that the I-cache can 589 * be made coherent later. 590 */ 591void 592cpu_flush_dcache(void *ptr, size_t len) 593{ 594 /* Not applicable */ 595} 596 597/* Get current clock frequency for the given cpu id. */ 598int 599cpu_est_clockrate(int cpu_id, uint64_t *rate) 600{ 601 uint64_t tsc1, tsc2; 602 uint64_t acnt, mcnt, perf; 603 register_t reg; 604 605 if (pcpu_find(cpu_id) == NULL || rate == NULL) 606 return (EINVAL); 607 608 /* 609 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 610 * DELAY(9) based logic fails. 611 */ 612 if (tsc_is_invariant && !tsc_perf_stat) 613 return (EOPNOTSUPP); 614 615#ifdef SMP 616 if (smp_cpus > 1) { 617 /* Schedule ourselves on the indicated cpu. */ 618 thread_lock(curthread); 619 sched_bind(curthread, cpu_id); 620 thread_unlock(curthread); 621 } 622#endif 623 624 /* Calibrate by measuring a short delay. */ 625 reg = intr_disable(); 626 if (tsc_is_invariant) { 627 wrmsr(MSR_MPERF, 0); 628 wrmsr(MSR_APERF, 0); 629 tsc1 = rdtsc(); 630 DELAY(1000); 631 mcnt = rdmsr(MSR_MPERF); 632 acnt = rdmsr(MSR_APERF); 633 tsc2 = rdtsc(); 634 intr_restore(reg); 635 perf = 1000 * acnt / mcnt; 636 *rate = (tsc2 - tsc1) * perf; 637 } else { 638 tsc1 = rdtsc(); 639 DELAY(1000); 640 tsc2 = rdtsc(); 641 intr_restore(reg); 642 *rate = (tsc2 - tsc1) * 1000; 643 } 644 645#ifdef SMP 646 if (smp_cpus > 1) { 647 thread_lock(curthread); 648 sched_unbind(curthread); 649 thread_unlock(curthread); 650 } 651#endif 652 653 return (0); 654} 655 656/* 657 * Shutdown the CPU as much as possible 658 */ 659void 660cpu_halt(void) 661{ 662 for (;;) 663 halt(); 664} 665 666void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 667static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 668static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 669TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 670SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 671 0, "Use MONITOR/MWAIT for short idle"); 672 673#define STATE_RUNNING 0x0 674#define STATE_MWAIT 0x1 675#define STATE_SLEEPING 0x2 676 677static void 678cpu_idle_acpi(sbintime_t sbt) 679{ 680 int *state; 681 682 state = (int *)PCPU_PTR(monitorbuf); 683 *state = STATE_SLEEPING; 684 685 /* See comments in cpu_idle_hlt(). */ 686 disable_intr(); 687 if (sched_runnable()) 688 enable_intr(); 689 else if (cpu_idle_hook) 690 cpu_idle_hook(sbt); 691 else 692 __asm __volatile("sti; hlt"); 693 *state = STATE_RUNNING; 694} 695 696static void 697cpu_idle_hlt(sbintime_t sbt) 698{ 699 int *state; 700 701 state = (int *)PCPU_PTR(monitorbuf); 702 *state = STATE_SLEEPING; 703 704 /* 705 * Since we may be in a critical section from cpu_idle(), if 706 * an interrupt fires during that critical section we may have 707 * a pending preemption. If the CPU halts, then that thread 708 * may not execute until a later interrupt awakens the CPU. 709 * To handle this race, check for a runnable thread after 710 * disabling interrupts and immediately return if one is 711 * found. Also, we must absolutely guarentee that hlt is 712 * the next instruction after sti. This ensures that any 713 * interrupt that fires after the call to disable_intr() will 714 * immediately awaken the CPU from hlt. Finally, please note 715 * that on x86 this works fine because of interrupts enabled only 716 * after the instruction following sti takes place, while IF is set 717 * to 1 immediately, allowing hlt instruction to acknowledge the 718 * interrupt. 719 */ 720 disable_intr(); 721 if (sched_runnable()) 722 enable_intr(); 723 else 724 __asm __volatile("sti; hlt"); 725 *state = STATE_RUNNING; 726} 727 728/* 729 * MWAIT cpu power states. Lower 4 bits are sub-states. 730 */ 731#define MWAIT_C0 0xf0 732#define MWAIT_C1 0x00 733#define MWAIT_C2 0x10 734#define MWAIT_C3 0x20 735#define MWAIT_C4 0x30 736 737static void 738cpu_idle_mwait(sbintime_t sbt) 739{ 740 int *state; 741 742 state = (int *)PCPU_PTR(monitorbuf); 743 *state = STATE_MWAIT; 744 745 /* See comments in cpu_idle_hlt(). */ 746 disable_intr(); 747 if (sched_runnable()) { 748 enable_intr(); 749 *state = STATE_RUNNING; 750 return; 751 } 752 cpu_monitor(state, 0, 0); 753 if (*state == STATE_MWAIT) 754 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 755 else 756 enable_intr(); 757 *state = STATE_RUNNING; 758} 759 760static void 761cpu_idle_spin(sbintime_t sbt) 762{ 763 int *state; 764 int i; 765 766 state = (int *)PCPU_PTR(monitorbuf); 767 *state = STATE_RUNNING; 768 769 /* 770 * The sched_runnable() call is racy but as long as there is 771 * a loop missing it one time will have just a little impact if any 772 * (and it is much better than missing the check at all). 773 */ 774 for (i = 0; i < 1000; i++) { 775 if (sched_runnable()) 776 return; 777 cpu_spinwait(); 778 } 779} 780 781/* 782 * C1E renders the local APIC timer dead, so we disable it by 783 * reading the Interrupt Pending Message register and clearing 784 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 785 * 786 * Reference: 787 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 788 * #32559 revision 3.00+ 789 */ 790#define MSR_AMDK8_IPM 0xc0010055 791#define AMDK8_SMIONCMPHALT (1ULL << 27) 792#define AMDK8_C1EONCMPHALT (1ULL << 28) 793#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 794 795static void 796cpu_probe_amdc1e(void) 797{ 798 799 /* 800 * Detect the presence of C1E capability mostly on latest 801 * dual-cores (or future) k8 family. 802 */ 803 if (cpu_vendor_id == CPU_VENDOR_AMD && 804 (cpu_id & 0x00000f00) == 0x00000f00 && 805 (cpu_id & 0x0fff0000) >= 0x00040000) { 806 cpu_ident_amdc1e = 1; 807 } 808} 809 810void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 811 812void 813cpu_idle(int busy) 814{ 815 uint64_t msr; 816 sbintime_t sbt = -1; 817 818 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 819 busy, curcpu); 820#ifdef MP_WATCHDOG 821 ap_watchdog(PCPU_GET(cpuid)); 822#endif 823 /* If we are busy - try to use fast methods. */ 824 if (busy) { 825 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 826 cpu_idle_mwait(busy); 827 goto out; 828 } 829 } 830 831 /* If we have time - switch timers into idle mode. */ 832 if (!busy) { 833 critical_enter(); 834 sbt = cpu_idleclock(); 835 } 836 837 /* Apply AMD APIC timer C1E workaround. */ 838 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 839 msr = rdmsr(MSR_AMDK8_IPM); 840 if (msr & AMDK8_CMPHALT) 841 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 842 } 843 844 /* Call main idle method. */ 845 cpu_idle_fn(sbt); 846 847 /* Switch timers back into active mode. */ 848 if (!busy) { 849 cpu_activeclock(); 850 critical_exit(); 851 } 852out: 853 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 854 busy, curcpu); 855} 856 857int 858cpu_idle_wakeup(int cpu) 859{ 860 struct pcpu *pcpu; 861 int *state; 862 863 pcpu = pcpu_find(cpu); 864 state = (int *)pcpu->pc_monitorbuf; 865 /* 866 * This doesn't need to be atomic since missing the race will 867 * simply result in unnecessary IPIs. 868 */ 869 if (*state == STATE_SLEEPING) 870 return (0); 871 if (*state == STATE_MWAIT) 872 *state = STATE_RUNNING; 873 return (1); 874} 875 876/* 877 * Ordered by speed/power consumption. 878 */ 879struct { 880 void *id_fn; 881 char *id_name; 882} idle_tbl[] = { 883 { cpu_idle_spin, "spin" }, 884 { cpu_idle_mwait, "mwait" }, 885 { cpu_idle_hlt, "hlt" }, 886 { cpu_idle_acpi, "acpi" }, 887 { NULL, NULL } 888}; 889 890static int 891idle_sysctl_available(SYSCTL_HANDLER_ARGS) 892{ 893 char *avail, *p; 894 int error; 895 int i; 896 897 avail = malloc(256, M_TEMP, M_WAITOK); 898 p = avail; 899 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 900 if (strstr(idle_tbl[i].id_name, "mwait") && 901 (cpu_feature2 & CPUID2_MON) == 0) 902 continue; 903 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 904 cpu_idle_hook == NULL) 905 continue; 906 p += sprintf(p, "%s%s", p != avail ? ", " : "", 907 idle_tbl[i].id_name); 908 } 909 error = sysctl_handle_string(oidp, avail, 0, req); 910 free(avail, M_TEMP); 911 return (error); 912} 913 914SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 915 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 916 917static int 918idle_sysctl(SYSCTL_HANDLER_ARGS) 919{ 920 char buf[16]; 921 int error; 922 char *p; 923 int i; 924 925 p = "unknown"; 926 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 927 if (idle_tbl[i].id_fn == cpu_idle_fn) { 928 p = idle_tbl[i].id_name; 929 break; 930 } 931 } 932 strncpy(buf, p, sizeof(buf)); 933 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 934 if (error != 0 || req->newptr == NULL) 935 return (error); 936 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 937 if (strstr(idle_tbl[i].id_name, "mwait") && 938 (cpu_feature2 & CPUID2_MON) == 0) 939 continue; 940 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 941 cpu_idle_hook == NULL) 942 continue; 943 if (strcmp(idle_tbl[i].id_name, buf)) 944 continue; 945 cpu_idle_fn = idle_tbl[i].id_fn; 946 return (0); 947 } 948 return (EINVAL); 949} 950 951SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 952 idle_sysctl, "A", "currently selected idle function"); 953 954/* 955 * Reset registers to default values on exec. 956 */ 957void 958exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 959{ 960 struct trapframe *regs = td->td_frame; 961 struct pcb *pcb = td->td_pcb; 962 963 mtx_lock(&dt_lock); 964 if (td->td_proc->p_md.md_ldt != NULL) 965 user_ldt_free(td); 966 else 967 mtx_unlock(&dt_lock); 968 969 pcb->pcb_fsbase = 0; 970 pcb->pcb_gsbase = 0; 971 clear_pcb_flags(pcb, PCB_32BIT); 972 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 973 set_pcb_flags(pcb, PCB_FULL_IRET); 974 975 bzero((char *)regs, sizeof(struct trapframe)); 976 regs->tf_rip = imgp->entry_addr; 977 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 978 regs->tf_rdi = stack; /* argv */ 979 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 980 regs->tf_ss = _udatasel; 981 regs->tf_cs = _ucodesel; 982 regs->tf_ds = _udatasel; 983 regs->tf_es = _udatasel; 984 regs->tf_fs = _ufssel; 985 regs->tf_gs = _ugssel; 986 regs->tf_flags = TF_HASSEGS; 987 td->td_retval[1] = 0; 988 989 /* 990 * Reset the hardware debug registers if they were in use. 991 * They won't have any meaning for the newly exec'd process. 992 */ 993 if (pcb->pcb_flags & PCB_DBREGS) { 994 pcb->pcb_dr0 = 0; 995 pcb->pcb_dr1 = 0; 996 pcb->pcb_dr2 = 0; 997 pcb->pcb_dr3 = 0; 998 pcb->pcb_dr6 = 0; 999 pcb->pcb_dr7 = 0; 1000 if (pcb == curpcb) { 1001 /* 1002 * Clear the debug registers on the running 1003 * CPU, otherwise they will end up affecting 1004 * the next process we switch to. 1005 */ 1006 reset_dbregs(); 1007 } 1008 clear_pcb_flags(pcb, PCB_DBREGS); 1009 } 1010 1011 /* 1012 * Drop the FP state if we hold it, so that the process gets a 1013 * clean FP state if it uses the FPU again. 1014 */ 1015 fpstate_drop(td); 1016} 1017 1018void 1019cpu_setregs(void) 1020{ 1021 register_t cr0; 1022 1023 cr0 = rcr0(); 1024 /* 1025 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1026 * BSP. See the comments there about why we set them. 1027 */ 1028 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1029 load_cr0(cr0); 1030} 1031 1032/* 1033 * Initialize amd64 and configure to run kernel 1034 */ 1035 1036/* 1037 * Initialize segments & interrupt table 1038 */ 1039 1040struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1041static struct gate_descriptor idt0[NIDT]; 1042struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1043 1044static char dblfault_stack[PAGE_SIZE] __aligned(16); 1045 1046static char nmi0_stack[PAGE_SIZE] __aligned(16); 1047CTASSERT(sizeof(struct nmi_pcpu) == 16); 1048 1049struct amd64tss common_tss[MAXCPU]; 1050 1051/* 1052 * Software prototypes -- in more palatable form. 1053 * 1054 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1055 * slots as corresponding segments for i386 kernel. 1056 */ 1057struct soft_segment_descriptor gdt_segs[] = { 1058/* GNULL_SEL 0 Null Descriptor */ 1059{ .ssd_base = 0x0, 1060 .ssd_limit = 0x0, 1061 .ssd_type = 0, 1062 .ssd_dpl = 0, 1063 .ssd_p = 0, 1064 .ssd_long = 0, 1065 .ssd_def32 = 0, 1066 .ssd_gran = 0 }, 1067/* GNULL2_SEL 1 Null Descriptor */ 1068{ .ssd_base = 0x0, 1069 .ssd_limit = 0x0, 1070 .ssd_type = 0, 1071 .ssd_dpl = 0, 1072 .ssd_p = 0, 1073 .ssd_long = 0, 1074 .ssd_def32 = 0, 1075 .ssd_gran = 0 }, 1076/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1077{ .ssd_base = 0x0, 1078 .ssd_limit = 0xfffff, 1079 .ssd_type = SDT_MEMRWA, 1080 .ssd_dpl = SEL_UPL, 1081 .ssd_p = 1, 1082 .ssd_long = 0, 1083 .ssd_def32 = 1, 1084 .ssd_gran = 1 }, 1085/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1086{ .ssd_base = 0x0, 1087 .ssd_limit = 0xfffff, 1088 .ssd_type = SDT_MEMRWA, 1089 .ssd_dpl = SEL_UPL, 1090 .ssd_p = 1, 1091 .ssd_long = 0, 1092 .ssd_def32 = 1, 1093 .ssd_gran = 1 }, 1094/* GCODE_SEL 4 Code Descriptor for kernel */ 1095{ .ssd_base = 0x0, 1096 .ssd_limit = 0xfffff, 1097 .ssd_type = SDT_MEMERA, 1098 .ssd_dpl = SEL_KPL, 1099 .ssd_p = 1, 1100 .ssd_long = 1, 1101 .ssd_def32 = 0, 1102 .ssd_gran = 1 }, 1103/* GDATA_SEL 5 Data Descriptor for kernel */ 1104{ .ssd_base = 0x0, 1105 .ssd_limit = 0xfffff, 1106 .ssd_type = SDT_MEMRWA, 1107 .ssd_dpl = SEL_KPL, 1108 .ssd_p = 1, 1109 .ssd_long = 1, 1110 .ssd_def32 = 0, 1111 .ssd_gran = 1 }, 1112/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1113{ .ssd_base = 0x0, 1114 .ssd_limit = 0xfffff, 1115 .ssd_type = SDT_MEMERA, 1116 .ssd_dpl = SEL_UPL, 1117 .ssd_p = 1, 1118 .ssd_long = 0, 1119 .ssd_def32 = 1, 1120 .ssd_gran = 1 }, 1121/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1122{ .ssd_base = 0x0, 1123 .ssd_limit = 0xfffff, 1124 .ssd_type = SDT_MEMRWA, 1125 .ssd_dpl = SEL_UPL, 1126 .ssd_p = 1, 1127 .ssd_long = 0, 1128 .ssd_def32 = 1, 1129 .ssd_gran = 1 }, 1130/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1131{ .ssd_base = 0x0, 1132 .ssd_limit = 0xfffff, 1133 .ssd_type = SDT_MEMERA, 1134 .ssd_dpl = SEL_UPL, 1135 .ssd_p = 1, 1136 .ssd_long = 1, 1137 .ssd_def32 = 0, 1138 .ssd_gran = 1 }, 1139/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1140{ .ssd_base = 0x0, 1141 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1142 .ssd_type = SDT_SYSTSS, 1143 .ssd_dpl = SEL_KPL, 1144 .ssd_p = 1, 1145 .ssd_long = 0, 1146 .ssd_def32 = 0, 1147 .ssd_gran = 0 }, 1148/* Actually, the TSS is a system descriptor which is double size */ 1149{ .ssd_base = 0x0, 1150 .ssd_limit = 0x0, 1151 .ssd_type = 0, 1152 .ssd_dpl = 0, 1153 .ssd_p = 0, 1154 .ssd_long = 0, 1155 .ssd_def32 = 0, 1156 .ssd_gran = 0 }, 1157/* GUSERLDT_SEL 11 LDT Descriptor */ 1158{ .ssd_base = 0x0, 1159 .ssd_limit = 0x0, 1160 .ssd_type = 0, 1161 .ssd_dpl = 0, 1162 .ssd_p = 0, 1163 .ssd_long = 0, 1164 .ssd_def32 = 0, 1165 .ssd_gran = 0 }, 1166/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1167{ .ssd_base = 0x0, 1168 .ssd_limit = 0x0, 1169 .ssd_type = 0, 1170 .ssd_dpl = 0, 1171 .ssd_p = 0, 1172 .ssd_long = 0, 1173 .ssd_def32 = 0, 1174 .ssd_gran = 0 }, 1175}; 1176 1177void 1178setidt(idx, func, typ, dpl, ist) 1179 int idx; 1180 inthand_t *func; 1181 int typ; 1182 int dpl; 1183 int ist; 1184{ 1185 struct gate_descriptor *ip; 1186 1187 ip = idt + idx; 1188 ip->gd_looffset = (uintptr_t)func; 1189 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1190 ip->gd_ist = ist; 1191 ip->gd_xx = 0; 1192 ip->gd_type = typ; 1193 ip->gd_dpl = dpl; 1194 ip->gd_p = 1; 1195 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1196} 1197 1198extern inthand_t 1199 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1200 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1201 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1202 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1203 IDTVEC(xmm), IDTVEC(dblfault), 1204#ifdef KDTRACE_HOOKS 1205 IDTVEC(dtrace_ret), 1206#endif 1207#ifdef XENHVM 1208 IDTVEC(xen_intr_upcall), 1209#endif 1210 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1211 1212#ifdef DDB 1213/* 1214 * Display the index and function name of any IDT entries that don't use 1215 * the default 'rsvd' entry point. 1216 */ 1217DB_SHOW_COMMAND(idt, db_show_idt) 1218{ 1219 struct gate_descriptor *ip; 1220 int idx; 1221 uintptr_t func; 1222 1223 ip = idt; 1224 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1225 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1226 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1227 db_printf("%3d\t", idx); 1228 db_printsym(func, DB_STGY_PROC); 1229 db_printf("\n"); 1230 } 1231 ip++; 1232 } 1233} 1234 1235/* Show privileged registers. */ 1236DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1237{ 1238 struct { 1239 uint16_t limit; 1240 uint64_t base; 1241 } __packed idtr, gdtr; 1242 uint16_t ldt, tr; 1243 1244 __asm __volatile("sidt %0" : "=m" (idtr)); 1245 db_printf("idtr\t0x%016lx/%04x\n", 1246 (u_long)idtr.base, (u_int)idtr.limit); 1247 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1248 db_printf("gdtr\t0x%016lx/%04x\n", 1249 (u_long)gdtr.base, (u_int)gdtr.limit); 1250 __asm __volatile("sldt %0" : "=r" (ldt)); 1251 db_printf("ldtr\t0x%04x\n", ldt); 1252 __asm __volatile("str %0" : "=r" (tr)); 1253 db_printf("tr\t0x%04x\n", tr); 1254 db_printf("cr0\t0x%016lx\n", rcr0()); 1255 db_printf("cr2\t0x%016lx\n", rcr2()); 1256 db_printf("cr3\t0x%016lx\n", rcr3()); 1257 db_printf("cr4\t0x%016lx\n", rcr4()); 1258 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1259 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1260 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1261 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1262 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1263} 1264#endif 1265 1266void 1267sdtossd(sd, ssd) 1268 struct user_segment_descriptor *sd; 1269 struct soft_segment_descriptor *ssd; 1270{ 1271 1272 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1273 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1274 ssd->ssd_type = sd->sd_type; 1275 ssd->ssd_dpl = sd->sd_dpl; 1276 ssd->ssd_p = sd->sd_p; 1277 ssd->ssd_long = sd->sd_long; 1278 ssd->ssd_def32 = sd->sd_def32; 1279 ssd->ssd_gran = sd->sd_gran; 1280} 1281 1282void 1283ssdtosd(ssd, sd) 1284 struct soft_segment_descriptor *ssd; 1285 struct user_segment_descriptor *sd; 1286{ 1287 1288 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1289 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1290 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1291 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1292 sd->sd_type = ssd->ssd_type; 1293 sd->sd_dpl = ssd->ssd_dpl; 1294 sd->sd_p = ssd->ssd_p; 1295 sd->sd_long = ssd->ssd_long; 1296 sd->sd_def32 = ssd->ssd_def32; 1297 sd->sd_gran = ssd->ssd_gran; 1298} 1299 1300void 1301ssdtosyssd(ssd, sd) 1302 struct soft_segment_descriptor *ssd; 1303 struct system_segment_descriptor *sd; 1304{ 1305 1306 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1307 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1308 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1309 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1310 sd->sd_type = ssd->ssd_type; 1311 sd->sd_dpl = ssd->ssd_dpl; 1312 sd->sd_p = ssd->ssd_p; 1313 sd->sd_gran = ssd->ssd_gran; 1314} 1315 1316#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1317#include <isa/isavar.h> 1318#include <isa/isareg.h> 1319/* 1320 * Return a bitmap of the current interrupt requests. This is 8259-specific 1321 * and is only suitable for use at probe time. 1322 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1323 * It shouldn't be here. There should probably be an APIC centric 1324 * implementation in the apic driver code, if at all. 1325 */ 1326intrmask_t 1327isa_irq_pending(void) 1328{ 1329 u_char irr1; 1330 u_char irr2; 1331 1332 irr1 = inb(IO_ICU1); 1333 irr2 = inb(IO_ICU2); 1334 return ((irr2 << 8) | irr1); 1335} 1336#endif 1337 1338u_int basemem; 1339 1340static int 1341add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap, 1342 int *physmap_idxp) 1343{ 1344 int i, insert_idx, physmap_idx; 1345 1346 physmap_idx = *physmap_idxp; 1347 1348 if (length == 0) 1349 return (1); 1350 1351 /* 1352 * Find insertion point while checking for overlap. Start off by 1353 * assuming the new entry will be added to the end. 1354 */ 1355 insert_idx = physmap_idx + 2; 1356 for (i = 0; i <= physmap_idx; i += 2) { 1357 if (base < physmap[i + 1]) { 1358 if (base + length <= physmap[i]) { 1359 insert_idx = i; 1360 break; 1361 } 1362 if (boothowto & RB_VERBOSE) 1363 printf( 1364 "Overlapping memory regions, ignoring second region\n"); 1365 return (1); 1366 } 1367 } 1368 1369 /* See if we can prepend to the next entry. */ 1370 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) { 1371 physmap[insert_idx] = base; 1372 return (1); 1373 } 1374 1375 /* See if we can append to the previous entry. */ 1376 if (insert_idx > 0 && base == physmap[insert_idx - 1]) { 1377 physmap[insert_idx - 1] += length; 1378 return (1); 1379 } 1380 1381 physmap_idx += 2; 1382 *physmap_idxp = physmap_idx; 1383 if (physmap_idx == PHYSMAP_SIZE) { 1384 printf( 1385 "Too many segments in the physical address map, giving up\n"); 1386 return (0); 1387 } 1388 1389 /* 1390 * Move the last 'N' entries down to make room for the new 1391 * entry if needed. 1392 */ 1393 for (i = physmap_idx; i > insert_idx; i -= 2) { 1394 physmap[i] = physmap[i - 2]; 1395 physmap[i + 1] = physmap[i - 1]; 1396 } 1397 1398 /* Insert the new entry. */ 1399 physmap[insert_idx] = base; 1400 physmap[insert_idx + 1] = base + length; 1401 return (1); 1402} 1403 1404static void 1405add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap, 1406 int *physmap_idx) 1407{ 1408 struct bios_smap *smap, *smapend; 1409 u_int32_t smapsize; 1410 1411 /* 1412 * Memory map from INT 15:E820. 1413 * 1414 * subr_module.c says: 1415 * "Consumer may safely assume that size value precedes data." 1416 * ie: an int32_t immediately precedes smap. 1417 */ 1418 smapsize = *((u_int32_t *)smapbase - 1); 1419 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1420 1421 for (smap = smapbase; smap < smapend; smap++) { 1422 if (boothowto & RB_VERBOSE) 1423 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1424 smap->type, smap->base, smap->length); 1425 1426 if (smap->type != SMAP_TYPE_MEMORY) 1427 continue; 1428 1429 if (!add_physmap_entry(smap->base, smap->length, physmap, 1430 physmap_idx)) 1431 break; 1432 } 1433} 1434 1435/* 1436 * Populate the (physmap) array with base/bound pairs describing the 1437 * available physical memory in the system, then test this memory and 1438 * build the phys_avail array describing the actually-available memory. 1439 * 1440 * Total memory size may be set by the kernel environment variable 1441 * hw.physmem or the compile-time define MAXMEM. 1442 * 1443 * XXX first should be vm_paddr_t. 1444 */ 1445static void 1446getmemsize(caddr_t kmdp, u_int64_t first) 1447{ 1448 int i, physmap_idx, pa_indx, da_indx; 1449 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1450 u_long physmem_start, physmem_tunable, memtest; 1451 pt_entry_t *pte; 1452 struct bios_smap *smapbase; 1453 quad_t dcons_addr, dcons_size; 1454 1455 bzero(physmap, sizeof(physmap)); 1456 basemem = 0; 1457 physmap_idx = 0; 1458 1459 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1460 MODINFO_METADATA | MODINFOMD_SMAP); 1461 if (smapbase == NULL) 1462 panic("No BIOS smap info from loader!"); 1463 1464 add_smap_entries(smapbase, physmap, &physmap_idx); 1465 1466 /* 1467 * Find the 'base memory' segment for SMP 1468 */ 1469 basemem = 0; 1470 for (i = 0; i <= physmap_idx; i += 2) { 1471 if (physmap[i] == 0x00000000) { 1472 basemem = physmap[i + 1] / 1024; 1473 break; 1474 } 1475 } 1476 if (basemem == 0) 1477 panic("BIOS smap did not include a basemem segment!"); 1478 1479#ifdef SMP 1480 /* make hole for AP bootstrap code */ 1481 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1482#endif 1483 1484 /* 1485 * Maxmem isn't the "maximum memory", it's one larger than the 1486 * highest page of the physical address space. It should be 1487 * called something like "Maxphyspage". We may adjust this 1488 * based on ``hw.physmem'' and the results of the memory test. 1489 */ 1490 Maxmem = atop(physmap[physmap_idx + 1]); 1491 1492#ifdef MAXMEM 1493 Maxmem = MAXMEM / 4; 1494#endif 1495 1496 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1497 Maxmem = atop(physmem_tunable); 1498 1499 /* 1500 * The boot memory test is disabled by default, as it takes a 1501 * significant amount of time on large-memory systems, and is 1502 * unfriendly to virtual machines as it unnecessarily touches all 1503 * pages. 1504 * 1505 * A general name is used as the code may be extended to support 1506 * additional tests beyond the current "page present" test. 1507 */ 1508 memtest = 0; 1509 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1510 1511 /* 1512 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1513 * in the system. 1514 */ 1515 if (Maxmem > atop(physmap[physmap_idx + 1])) 1516 Maxmem = atop(physmap[physmap_idx + 1]); 1517 1518 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1519 (boothowto & RB_VERBOSE)) 1520 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1521 1522 /* call pmap initialization to make new kernel address space */ 1523 pmap_bootstrap(&first); 1524 1525 /* 1526 * Size up each available chunk of physical memory. 1527 * 1528 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1529 * By default, mask off the first 16 pages unless we appear to be 1530 * running in a VM. 1531 */ 1532 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1533 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1534 if (physmem_start < PAGE_SIZE) 1535 physmap[0] = PAGE_SIZE; 1536 else if (physmem_start >= physmap[1]) 1537 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1538 else 1539 physmap[0] = round_page(physmem_start); 1540 pa_indx = 0; 1541 da_indx = 1; 1542 phys_avail[pa_indx++] = physmap[0]; 1543 phys_avail[pa_indx] = physmap[0]; 1544 dump_avail[da_indx] = physmap[0]; 1545 pte = CMAP1; 1546 1547 /* 1548 * Get dcons buffer address 1549 */ 1550 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1551 getenv_quad("dcons.size", &dcons_size) == 0) 1552 dcons_addr = 0; 1553 1554 /* 1555 * physmap is in bytes, so when converting to page boundaries, 1556 * round up the start address and round down the end address. 1557 */ 1558 for (i = 0; i <= physmap_idx; i += 2) { 1559 vm_paddr_t end; 1560 1561 end = ptoa((vm_paddr_t)Maxmem); 1562 if (physmap[i + 1] < end) 1563 end = trunc_page(physmap[i + 1]); 1564 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1565 int tmp, page_bad, full; 1566 int *ptr = (int *)CADDR1; 1567 1568 full = FALSE; 1569 /* 1570 * block out kernel memory as not available. 1571 */ 1572 if (pa >= (vm_paddr_t)kernphys && pa < first) 1573 goto do_dump_avail; 1574 1575 /* 1576 * block out dcons buffer 1577 */ 1578 if (dcons_addr > 0 1579 && pa >= trunc_page(dcons_addr) 1580 && pa < dcons_addr + dcons_size) 1581 goto do_dump_avail; 1582 1583 page_bad = FALSE; 1584 if (memtest == 0) 1585 goto skip_memtest; 1586 1587 /* 1588 * map page into kernel: valid, read/write,non-cacheable 1589 */ 1590 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1591 invltlb(); 1592 1593 tmp = *(int *)ptr; 1594 /* 1595 * Test for alternating 1's and 0's 1596 */ 1597 *(volatile int *)ptr = 0xaaaaaaaa; 1598 if (*(volatile int *)ptr != 0xaaaaaaaa) 1599 page_bad = TRUE; 1600 /* 1601 * Test for alternating 0's and 1's 1602 */ 1603 *(volatile int *)ptr = 0x55555555; 1604 if (*(volatile int *)ptr != 0x55555555) 1605 page_bad = TRUE; 1606 /* 1607 * Test for all 1's 1608 */ 1609 *(volatile int *)ptr = 0xffffffff; 1610 if (*(volatile int *)ptr != 0xffffffff) 1611 page_bad = TRUE; 1612 /* 1613 * Test for all 0's 1614 */ 1615 *(volatile int *)ptr = 0x0; 1616 if (*(volatile int *)ptr != 0x0) 1617 page_bad = TRUE; 1618 /* 1619 * Restore original value. 1620 */ 1621 *(int *)ptr = tmp; 1622 1623skip_memtest: 1624 /* 1625 * Adjust array of valid/good pages. 1626 */ 1627 if (page_bad == TRUE) 1628 continue; 1629 /* 1630 * If this good page is a continuation of the 1631 * previous set of good pages, then just increase 1632 * the end pointer. Otherwise start a new chunk. 1633 * Note that "end" points one higher than end, 1634 * making the range >= start and < end. 1635 * If we're also doing a speculative memory 1636 * test and we at or past the end, bump up Maxmem 1637 * so that we keep going. The first bad page 1638 * will terminate the loop. 1639 */ 1640 if (phys_avail[pa_indx] == pa) { 1641 phys_avail[pa_indx] += PAGE_SIZE; 1642 } else { 1643 pa_indx++; 1644 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1645 printf( 1646 "Too many holes in the physical address space, giving up\n"); 1647 pa_indx--; 1648 full = TRUE; 1649 goto do_dump_avail; 1650 } 1651 phys_avail[pa_indx++] = pa; /* start */ 1652 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1653 } 1654 physmem++; 1655do_dump_avail: 1656 if (dump_avail[da_indx] == pa) { 1657 dump_avail[da_indx] += PAGE_SIZE; 1658 } else { 1659 da_indx++; 1660 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1661 da_indx--; 1662 goto do_next; 1663 } 1664 dump_avail[da_indx++] = pa; /* start */ 1665 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1666 } 1667do_next: 1668 if (full) 1669 break; 1670 } 1671 } 1672 *pte = 0; 1673 invltlb(); 1674 1675 /* 1676 * XXX 1677 * The last chunk must contain at least one page plus the message 1678 * buffer to avoid complicating other code (message buffer address 1679 * calculation, etc.). 1680 */ 1681 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1682 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1683 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1684 phys_avail[pa_indx--] = 0; 1685 phys_avail[pa_indx--] = 0; 1686 } 1687 1688 Maxmem = atop(phys_avail[pa_indx]); 1689 1690 /* Trim off space for the message buffer. */ 1691 phys_avail[pa_indx] -= round_page(msgbufsize); 1692 1693 /* Map the message buffer. */ 1694 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1695} 1696 1697static caddr_t 1698native_parse_preload_data(u_int64_t modulep) 1699{ 1700 caddr_t kmdp; 1701 1702 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1703 preload_bootstrap_relocate(KERNBASE); 1704 kmdp = preload_search_by_type("elf kernel"); 1705 if (kmdp == NULL) 1706 kmdp = preload_search_by_type("elf64 kernel"); 1707 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1708 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1709#ifdef DDB 1710 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1711 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1712#endif 1713 1714 return (kmdp); 1715} 1716 1717u_int64_t 1718hammer_time(u_int64_t modulep, u_int64_t physfree) 1719{ 1720 caddr_t kmdp; 1721 int gsel_tss, x; 1722 struct pcpu *pc; 1723 struct nmi_pcpu *np; 1724 struct xstate_hdr *xhdr; 1725 u_int64_t msr; 1726 char *env; 1727 size_t kstack0_sz; 1728 1729 thread0.td_kstack = physfree + KERNBASE; 1730 thread0.td_kstack_pages = KSTACK_PAGES; 1731 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1732 bzero((void *)thread0.td_kstack, kstack0_sz); 1733 physfree += kstack0_sz; 1734 1735 /* 1736 * This may be done better later if it gets more high level 1737 * components in it. If so just link td->td_proc here. 1738 */ 1739 proc_linkup0(&proc0, &thread0); 1740 1741 kmdp = init_ops.parse_preload_data(modulep); 1742 1743 /* Init basic tunables, hz etc */ 1744 init_param1(); 1745 1746 /* 1747 * make gdt memory segments 1748 */ 1749 for (x = 0; x < NGDT; x++) { 1750 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1751 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1752 ssdtosd(&gdt_segs[x], &gdt[x]); 1753 } 1754 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1755 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1756 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1757 1758 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1759 r_gdt.rd_base = (long) gdt; 1760 lgdt(&r_gdt); 1761 pc = &__pcpu[0]; 1762 1763 wrmsr(MSR_FSBASE, 0); /* User value */ 1764 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1765 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1766 1767 pcpu_init(pc, 0, sizeof(struct pcpu)); 1768 dpcpu_init((void *)(physfree + KERNBASE), 0); 1769 physfree += DPCPU_SIZE; 1770 PCPU_SET(prvspace, pc); 1771 PCPU_SET(curthread, &thread0); 1772 PCPU_SET(tssp, &common_tss[0]); 1773 PCPU_SET(commontssp, &common_tss[0]); 1774 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1775 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1776 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1777 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1778 1779 /* 1780 * Initialize mutexes. 1781 * 1782 * icu_lock: in order to allow an interrupt to occur in a critical 1783 * section, to set pcpu->ipending (etc...) properly, we 1784 * must be able to get the icu lock, so it can't be 1785 * under witness. 1786 */ 1787 mutex_init(); 1788 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1789 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1790 1791 /* exceptions */ 1792 for (x = 0; x < NIDT; x++) 1793 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1794 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1795 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1796 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1797 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1798 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1799 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1800 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1801 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1802 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1803 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1804 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1805 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1806 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1807 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1808 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1809 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1810 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1811 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1812 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1813#ifdef KDTRACE_HOOKS 1814 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1815#endif 1816#ifdef XENHVM 1817 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1818#endif 1819 1820 r_idt.rd_limit = sizeof(idt0) - 1; 1821 r_idt.rd_base = (long) idt; 1822 lidt(&r_idt); 1823 1824 /* 1825 * Initialize the i8254 before the console so that console 1826 * initialization can use DELAY(). 1827 */ 1828 i8254_init(); 1829 1830 /* 1831 * Initialize the console before we print anything out. 1832 */ 1833 cninit(); 1834 1835#ifdef DEV_ISA 1836#ifdef DEV_ATPIC 1837 elcr_probe(); 1838 atpic_startup(); 1839#else 1840 /* Reset and mask the atpics and leave them shut down. */ 1841 atpic_reset(); 1842 1843 /* 1844 * Point the ICU spurious interrupt vectors at the APIC spurious 1845 * interrupt handler. 1846 */ 1847 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1848 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1849#endif 1850#else 1851#error "have you forgotten the isa device?"; 1852#endif 1853 1854 kdb_init(); 1855 1856#ifdef KDB 1857 if (boothowto & RB_KDB) 1858 kdb_enter(KDB_WHY_BOOTFLAGS, 1859 "Boot flags requested debugger"); 1860#endif 1861 1862 identify_cpu(); /* Final stage of CPU initialization */ 1863 initializecpu(); /* Initialize CPU registers */ 1864 initializecpucache(); 1865 1866 /* doublefault stack space, runs on ist1 */ 1867 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1868 1869 /* 1870 * NMI stack, runs on ist2. The pcpu pointer is stored just 1871 * above the start of the ist2 stack. 1872 */ 1873 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1874 np->np_pcpu = (register_t) pc; 1875 common_tss[0].tss_ist2 = (long) np; 1876 1877 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1878 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1879 IOPAGES * PAGE_SIZE; 1880 1881 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1882 ltr(gsel_tss); 1883 1884 /* Set up the fast syscall stuff */ 1885 msr = rdmsr(MSR_EFER) | EFER_SCE; 1886 wrmsr(MSR_EFER, msr); 1887 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1888 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1889 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1890 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1891 wrmsr(MSR_STAR, msr); 1892 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1893 1894 getmemsize(kmdp, physfree); 1895 init_param2(physmem); 1896 1897 /* now running on new page tables, configured,and u/iom is accessible */ 1898 1899 msgbufinit(msgbufp, msgbufsize); 1900 fpuinit(); 1901 1902 /* 1903 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1904 * area size. Zero out the extended state header in fpu save 1905 * area. 1906 */ 1907 thread0.td_pcb = get_pcb_td(&thread0); 1908 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1909 if (use_xsave) { 1910 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1911 1); 1912 xhdr->xstate_bv = xsave_mask; 1913 } 1914 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1915 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1916 /* Ensure the stack is aligned to 16 bytes */ 1917 common_tss[0].tss_rsp0 &= ~0xFul; 1918 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1919 PCPU_SET(curpcb, thread0.td_pcb); 1920 1921 /* transfer to user mode */ 1922 1923 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1924 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1925 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1926 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1927 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1928 1929 load_ds(_udatasel); 1930 load_es(_udatasel); 1931 load_fs(_ufssel); 1932 1933 /* setup proc 0's pcb */ 1934 thread0.td_pcb->pcb_flags = 0; 1935 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 1936 thread0.td_frame = &proc0_tf; 1937 1938 env = getenv("kernelname"); 1939 if (env != NULL) 1940 strlcpy(kernelname, env, sizeof(kernelname)); 1941 1942 cpu_probe_amdc1e(); 1943 1944#ifdef FDT 1945 x86_init_fdt(); 1946#endif 1947 1948 /* Location of kernel stack for locore */ 1949 return ((u_int64_t)thread0.td_pcb); 1950} 1951 1952void 1953cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1954{ 1955 1956 pcpu->pc_acpi_id = 0xffffffff; 1957} 1958 1959void 1960spinlock_enter(void) 1961{ 1962 struct thread *td; 1963 register_t flags; 1964 1965 td = curthread; 1966 if (td->td_md.md_spinlock_count == 0) { 1967 flags = intr_disable(); 1968 td->td_md.md_spinlock_count = 1; 1969 td->td_md.md_saved_flags = flags; 1970 } else 1971 td->td_md.md_spinlock_count++; 1972 critical_enter(); 1973} 1974 1975void 1976spinlock_exit(void) 1977{ 1978 struct thread *td; 1979 register_t flags; 1980 1981 td = curthread; 1982 critical_exit(); 1983 flags = td->td_md.md_saved_flags; 1984 td->td_md.md_spinlock_count--; 1985 if (td->td_md.md_spinlock_count == 0) 1986 intr_restore(flags); 1987} 1988 1989/* 1990 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1991 * we want to start a backtrace from the function that caused us to enter 1992 * the debugger. We have the context in the trapframe, but base the trace 1993 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1994 * enough for a backtrace. 1995 */ 1996void 1997makectx(struct trapframe *tf, struct pcb *pcb) 1998{ 1999 2000 pcb->pcb_r12 = tf->tf_r12; 2001 pcb->pcb_r13 = tf->tf_r13; 2002 pcb->pcb_r14 = tf->tf_r14; 2003 pcb->pcb_r15 = tf->tf_r15; 2004 pcb->pcb_rbp = tf->tf_rbp; 2005 pcb->pcb_rbx = tf->tf_rbx; 2006 pcb->pcb_rip = tf->tf_rip; 2007 pcb->pcb_rsp = tf->tf_rsp; 2008} 2009 2010int 2011ptrace_set_pc(struct thread *td, unsigned long addr) 2012{ 2013 td->td_frame->tf_rip = addr; 2014 return (0); 2015} 2016 2017int 2018ptrace_single_step(struct thread *td) 2019{ 2020 td->td_frame->tf_rflags |= PSL_T; 2021 return (0); 2022} 2023 2024int 2025ptrace_clear_single_step(struct thread *td) 2026{ 2027 td->td_frame->tf_rflags &= ~PSL_T; 2028 return (0); 2029} 2030 2031int 2032fill_regs(struct thread *td, struct reg *regs) 2033{ 2034 struct trapframe *tp; 2035 2036 tp = td->td_frame; 2037 return (fill_frame_regs(tp, regs)); 2038} 2039 2040int 2041fill_frame_regs(struct trapframe *tp, struct reg *regs) 2042{ 2043 regs->r_r15 = tp->tf_r15; 2044 regs->r_r14 = tp->tf_r14; 2045 regs->r_r13 = tp->tf_r13; 2046 regs->r_r12 = tp->tf_r12; 2047 regs->r_r11 = tp->tf_r11; 2048 regs->r_r10 = tp->tf_r10; 2049 regs->r_r9 = tp->tf_r9; 2050 regs->r_r8 = tp->tf_r8; 2051 regs->r_rdi = tp->tf_rdi; 2052 regs->r_rsi = tp->tf_rsi; 2053 regs->r_rbp = tp->tf_rbp; 2054 regs->r_rbx = tp->tf_rbx; 2055 regs->r_rdx = tp->tf_rdx; 2056 regs->r_rcx = tp->tf_rcx; 2057 regs->r_rax = tp->tf_rax; 2058 regs->r_rip = tp->tf_rip; 2059 regs->r_cs = tp->tf_cs; 2060 regs->r_rflags = tp->tf_rflags; 2061 regs->r_rsp = tp->tf_rsp; 2062 regs->r_ss = tp->tf_ss; 2063 if (tp->tf_flags & TF_HASSEGS) { 2064 regs->r_ds = tp->tf_ds; 2065 regs->r_es = tp->tf_es; 2066 regs->r_fs = tp->tf_fs; 2067 regs->r_gs = tp->tf_gs; 2068 } else { 2069 regs->r_ds = 0; 2070 regs->r_es = 0; 2071 regs->r_fs = 0; 2072 regs->r_gs = 0; 2073 } 2074 return (0); 2075} 2076 2077int 2078set_regs(struct thread *td, struct reg *regs) 2079{ 2080 struct trapframe *tp; 2081 register_t rflags; 2082 2083 tp = td->td_frame; 2084 rflags = regs->r_rflags & 0xffffffff; 2085 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2086 return (EINVAL); 2087 tp->tf_r15 = regs->r_r15; 2088 tp->tf_r14 = regs->r_r14; 2089 tp->tf_r13 = regs->r_r13; 2090 tp->tf_r12 = regs->r_r12; 2091 tp->tf_r11 = regs->r_r11; 2092 tp->tf_r10 = regs->r_r10; 2093 tp->tf_r9 = regs->r_r9; 2094 tp->tf_r8 = regs->r_r8; 2095 tp->tf_rdi = regs->r_rdi; 2096 tp->tf_rsi = regs->r_rsi; 2097 tp->tf_rbp = regs->r_rbp; 2098 tp->tf_rbx = regs->r_rbx; 2099 tp->tf_rdx = regs->r_rdx; 2100 tp->tf_rcx = regs->r_rcx; 2101 tp->tf_rax = regs->r_rax; 2102 tp->tf_rip = regs->r_rip; 2103 tp->tf_cs = regs->r_cs; 2104 tp->tf_rflags = rflags; 2105 tp->tf_rsp = regs->r_rsp; 2106 tp->tf_ss = regs->r_ss; 2107 if (0) { /* XXXKIB */ 2108 tp->tf_ds = regs->r_ds; 2109 tp->tf_es = regs->r_es; 2110 tp->tf_fs = regs->r_fs; 2111 tp->tf_gs = regs->r_gs; 2112 tp->tf_flags = TF_HASSEGS; 2113 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2114 } 2115 return (0); 2116} 2117 2118/* XXX check all this stuff! */ 2119/* externalize from sv_xmm */ 2120static void 2121fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2122{ 2123 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2124 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2125 int i; 2126 2127 /* pcb -> fpregs */ 2128 bzero(fpregs, sizeof(*fpregs)); 2129 2130 /* FPU control/status */ 2131 penv_fpreg->en_cw = penv_xmm->en_cw; 2132 penv_fpreg->en_sw = penv_xmm->en_sw; 2133 penv_fpreg->en_tw = penv_xmm->en_tw; 2134 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2135 penv_fpreg->en_rip = penv_xmm->en_rip; 2136 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2137 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2138 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2139 2140 /* FPU registers */ 2141 for (i = 0; i < 8; ++i) 2142 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2143 2144 /* SSE registers */ 2145 for (i = 0; i < 16; ++i) 2146 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2147} 2148 2149/* internalize from fpregs into sv_xmm */ 2150static void 2151set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2152{ 2153 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2154 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2155 int i; 2156 2157 /* fpregs -> pcb */ 2158 /* FPU control/status */ 2159 penv_xmm->en_cw = penv_fpreg->en_cw; 2160 penv_xmm->en_sw = penv_fpreg->en_sw; 2161 penv_xmm->en_tw = penv_fpreg->en_tw; 2162 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2163 penv_xmm->en_rip = penv_fpreg->en_rip; 2164 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2165 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2166 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2167 2168 /* FPU registers */ 2169 for (i = 0; i < 8; ++i) 2170 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2171 2172 /* SSE registers */ 2173 for (i = 0; i < 16; ++i) 2174 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2175} 2176 2177/* externalize from td->pcb */ 2178int 2179fill_fpregs(struct thread *td, struct fpreg *fpregs) 2180{ 2181 2182 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2183 P_SHOULDSTOP(td->td_proc), 2184 ("not suspended thread %p", td)); 2185 fpugetregs(td); 2186 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2187 return (0); 2188} 2189 2190/* internalize to td->pcb */ 2191int 2192set_fpregs(struct thread *td, struct fpreg *fpregs) 2193{ 2194 2195 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2196 fpuuserinited(td); 2197 return (0); 2198} 2199 2200/* 2201 * Get machine context. 2202 */ 2203int 2204get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2205{ 2206 struct pcb *pcb; 2207 struct trapframe *tp; 2208 2209 pcb = td->td_pcb; 2210 tp = td->td_frame; 2211 PROC_LOCK(curthread->td_proc); 2212 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2213 PROC_UNLOCK(curthread->td_proc); 2214 mcp->mc_r15 = tp->tf_r15; 2215 mcp->mc_r14 = tp->tf_r14; 2216 mcp->mc_r13 = tp->tf_r13; 2217 mcp->mc_r12 = tp->tf_r12; 2218 mcp->mc_r11 = tp->tf_r11; 2219 mcp->mc_r10 = tp->tf_r10; 2220 mcp->mc_r9 = tp->tf_r9; 2221 mcp->mc_r8 = tp->tf_r8; 2222 mcp->mc_rdi = tp->tf_rdi; 2223 mcp->mc_rsi = tp->tf_rsi; 2224 mcp->mc_rbp = tp->tf_rbp; 2225 mcp->mc_rbx = tp->tf_rbx; 2226 mcp->mc_rcx = tp->tf_rcx; 2227 mcp->mc_rflags = tp->tf_rflags; 2228 if (flags & GET_MC_CLEAR_RET) { 2229 mcp->mc_rax = 0; 2230 mcp->mc_rdx = 0; 2231 mcp->mc_rflags &= ~PSL_C; 2232 } else { 2233 mcp->mc_rax = tp->tf_rax; 2234 mcp->mc_rdx = tp->tf_rdx; 2235 } 2236 mcp->mc_rip = tp->tf_rip; 2237 mcp->mc_cs = tp->tf_cs; 2238 mcp->mc_rsp = tp->tf_rsp; 2239 mcp->mc_ss = tp->tf_ss; 2240 mcp->mc_ds = tp->tf_ds; 2241 mcp->mc_es = tp->tf_es; 2242 mcp->mc_fs = tp->tf_fs; 2243 mcp->mc_gs = tp->tf_gs; 2244 mcp->mc_flags = tp->tf_flags; 2245 mcp->mc_len = sizeof(*mcp); 2246 get_fpcontext(td, mcp, NULL, 0); 2247 mcp->mc_fsbase = pcb->pcb_fsbase; 2248 mcp->mc_gsbase = pcb->pcb_gsbase; 2249 mcp->mc_xfpustate = 0; 2250 mcp->mc_xfpustate_len = 0; 2251 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2252 return (0); 2253} 2254 2255/* 2256 * Set machine context. 2257 * 2258 * However, we don't set any but the user modifiable flags, and we won't 2259 * touch the cs selector. 2260 */ 2261int 2262set_mcontext(struct thread *td, const mcontext_t *mcp) 2263{ 2264 struct pcb *pcb; 2265 struct trapframe *tp; 2266 char *xfpustate; 2267 long rflags; 2268 int ret; 2269 2270 pcb = td->td_pcb; 2271 tp = td->td_frame; 2272 if (mcp->mc_len != sizeof(*mcp) || 2273 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2274 return (EINVAL); 2275 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2276 (tp->tf_rflags & ~PSL_USERCHANGE); 2277 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2278 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2279 sizeof(struct savefpu)) 2280 return (EINVAL); 2281 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2282 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2283 mcp->mc_xfpustate_len); 2284 if (ret != 0) 2285 return (ret); 2286 } else 2287 xfpustate = NULL; 2288 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2289 if (ret != 0) 2290 return (ret); 2291 tp->tf_r15 = mcp->mc_r15; 2292 tp->tf_r14 = mcp->mc_r14; 2293 tp->tf_r13 = mcp->mc_r13; 2294 tp->tf_r12 = mcp->mc_r12; 2295 tp->tf_r11 = mcp->mc_r11; 2296 tp->tf_r10 = mcp->mc_r10; 2297 tp->tf_r9 = mcp->mc_r9; 2298 tp->tf_r8 = mcp->mc_r8; 2299 tp->tf_rdi = mcp->mc_rdi; 2300 tp->tf_rsi = mcp->mc_rsi; 2301 tp->tf_rbp = mcp->mc_rbp; 2302 tp->tf_rbx = mcp->mc_rbx; 2303 tp->tf_rdx = mcp->mc_rdx; 2304 tp->tf_rcx = mcp->mc_rcx; 2305 tp->tf_rax = mcp->mc_rax; 2306 tp->tf_rip = mcp->mc_rip; 2307 tp->tf_rflags = rflags; 2308 tp->tf_rsp = mcp->mc_rsp; 2309 tp->tf_ss = mcp->mc_ss; 2310 tp->tf_flags = mcp->mc_flags; 2311 if (tp->tf_flags & TF_HASSEGS) { 2312 tp->tf_ds = mcp->mc_ds; 2313 tp->tf_es = mcp->mc_es; 2314 tp->tf_fs = mcp->mc_fs; 2315 tp->tf_gs = mcp->mc_gs; 2316 } 2317 if (mcp->mc_flags & _MC_HASBASES) { 2318 pcb->pcb_fsbase = mcp->mc_fsbase; 2319 pcb->pcb_gsbase = mcp->mc_gsbase; 2320 } 2321 set_pcb_flags(pcb, PCB_FULL_IRET); 2322 return (0); 2323} 2324 2325static void 2326get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2327 size_t xfpusave_len) 2328{ 2329 size_t max_len, len; 2330 2331 mcp->mc_ownedfp = fpugetregs(td); 2332 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2333 sizeof(mcp->mc_fpstate)); 2334 mcp->mc_fpformat = fpuformat(); 2335 if (!use_xsave || xfpusave_len == 0) 2336 return; 2337 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2338 len = xfpusave_len; 2339 if (len > max_len) { 2340 len = max_len; 2341 bzero(xfpusave + max_len, len - max_len); 2342 } 2343 mcp->mc_flags |= _MC_HASFPXSTATE; 2344 mcp->mc_xfpustate_len = len; 2345 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2346} 2347 2348static int 2349set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2350 size_t xfpustate_len) 2351{ 2352 struct savefpu *fpstate; 2353 int error; 2354 2355 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2356 return (0); 2357 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2358 return (EINVAL); 2359 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2360 /* We don't care what state is left in the FPU or PCB. */ 2361 fpstate_drop(td); 2362 error = 0; 2363 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2364 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2365 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2366 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2367 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2368 } else 2369 return (EINVAL); 2370 return (error); 2371} 2372 2373void 2374fpstate_drop(struct thread *td) 2375{ 2376 2377 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2378 critical_enter(); 2379 if (PCPU_GET(fpcurthread) == td) 2380 fpudrop(); 2381 /* 2382 * XXX force a full drop of the fpu. The above only drops it if we 2383 * owned it. 2384 * 2385 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2386 * drop. Dropping only to the pcb matches fnsave's behaviour. 2387 * We only need to drop to !PCB_INITDONE in sendsig(). But 2388 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2389 * have too many layers. 2390 */ 2391 clear_pcb_flags(curthread->td_pcb, 2392 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2393 critical_exit(); 2394} 2395 2396int 2397fill_dbregs(struct thread *td, struct dbreg *dbregs) 2398{ 2399 struct pcb *pcb; 2400 2401 if (td == NULL) { 2402 dbregs->dr[0] = rdr0(); 2403 dbregs->dr[1] = rdr1(); 2404 dbregs->dr[2] = rdr2(); 2405 dbregs->dr[3] = rdr3(); 2406 dbregs->dr[6] = rdr6(); 2407 dbregs->dr[7] = rdr7(); 2408 } else { 2409 pcb = td->td_pcb; 2410 dbregs->dr[0] = pcb->pcb_dr0; 2411 dbregs->dr[1] = pcb->pcb_dr1; 2412 dbregs->dr[2] = pcb->pcb_dr2; 2413 dbregs->dr[3] = pcb->pcb_dr3; 2414 dbregs->dr[6] = pcb->pcb_dr6; 2415 dbregs->dr[7] = pcb->pcb_dr7; 2416 } 2417 dbregs->dr[4] = 0; 2418 dbregs->dr[5] = 0; 2419 dbregs->dr[8] = 0; 2420 dbregs->dr[9] = 0; 2421 dbregs->dr[10] = 0; 2422 dbregs->dr[11] = 0; 2423 dbregs->dr[12] = 0; 2424 dbregs->dr[13] = 0; 2425 dbregs->dr[14] = 0; 2426 dbregs->dr[15] = 0; 2427 return (0); 2428} 2429 2430int 2431set_dbregs(struct thread *td, struct dbreg *dbregs) 2432{ 2433 struct pcb *pcb; 2434 int i; 2435 2436 if (td == NULL) { 2437 load_dr0(dbregs->dr[0]); 2438 load_dr1(dbregs->dr[1]); 2439 load_dr2(dbregs->dr[2]); 2440 load_dr3(dbregs->dr[3]); 2441 load_dr6(dbregs->dr[6]); 2442 load_dr7(dbregs->dr[7]); 2443 } else { 2444 /* 2445 * Don't let an illegal value for dr7 get set. Specifically, 2446 * check for undefined settings. Setting these bit patterns 2447 * result in undefined behaviour and can lead to an unexpected 2448 * TRCTRAP or a general protection fault right here. 2449 * Upper bits of dr6 and dr7 must not be set 2450 */ 2451 for (i = 0; i < 4; i++) { 2452 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2453 return (EINVAL); 2454 if (td->td_frame->tf_cs == _ucode32sel && 2455 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2456 return (EINVAL); 2457 } 2458 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2459 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2460 return (EINVAL); 2461 2462 pcb = td->td_pcb; 2463 2464 /* 2465 * Don't let a process set a breakpoint that is not within the 2466 * process's address space. If a process could do this, it 2467 * could halt the system by setting a breakpoint in the kernel 2468 * (if ddb was enabled). Thus, we need to check to make sure 2469 * that no breakpoints are being enabled for addresses outside 2470 * process's address space. 2471 * 2472 * XXX - what about when the watched area of the user's 2473 * address space is written into from within the kernel 2474 * ... wouldn't that still cause a breakpoint to be generated 2475 * from within kernel mode? 2476 */ 2477 2478 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2479 /* dr0 is enabled */ 2480 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2481 return (EINVAL); 2482 } 2483 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2484 /* dr1 is enabled */ 2485 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2486 return (EINVAL); 2487 } 2488 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2489 /* dr2 is enabled */ 2490 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2491 return (EINVAL); 2492 } 2493 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2494 /* dr3 is enabled */ 2495 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2496 return (EINVAL); 2497 } 2498 2499 pcb->pcb_dr0 = dbregs->dr[0]; 2500 pcb->pcb_dr1 = dbregs->dr[1]; 2501 pcb->pcb_dr2 = dbregs->dr[2]; 2502 pcb->pcb_dr3 = dbregs->dr[3]; 2503 pcb->pcb_dr6 = dbregs->dr[6]; 2504 pcb->pcb_dr7 = dbregs->dr[7]; 2505 2506 set_pcb_flags(pcb, PCB_DBREGS); 2507 } 2508 2509 return (0); 2510} 2511 2512void 2513reset_dbregs(void) 2514{ 2515 2516 load_dr7(0); /* Turn off the control bits first */ 2517 load_dr0(0); 2518 load_dr1(0); 2519 load_dr2(0); 2520 load_dr3(0); 2521 load_dr6(0); 2522} 2523 2524/* 2525 * Return > 0 if a hardware breakpoint has been hit, and the 2526 * breakpoint was in user space. Return 0, otherwise. 2527 */ 2528int 2529user_dbreg_trap(void) 2530{ 2531 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2532 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2533 int nbp; /* number of breakpoints that triggered */ 2534 caddr_t addr[4]; /* breakpoint addresses */ 2535 int i; 2536 2537 dr7 = rdr7(); 2538 if ((dr7 & 0x000000ff) == 0) { 2539 /* 2540 * all GE and LE bits in the dr7 register are zero, 2541 * thus the trap couldn't have been caused by the 2542 * hardware debug registers 2543 */ 2544 return 0; 2545 } 2546 2547 nbp = 0; 2548 dr6 = rdr6(); 2549 bp = dr6 & 0x0000000f; 2550 2551 if (!bp) { 2552 /* 2553 * None of the breakpoint bits are set meaning this 2554 * trap was not caused by any of the debug registers 2555 */ 2556 return 0; 2557 } 2558 2559 /* 2560 * at least one of the breakpoints were hit, check to see 2561 * which ones and if any of them are user space addresses 2562 */ 2563 2564 if (bp & 0x01) { 2565 addr[nbp++] = (caddr_t)rdr0(); 2566 } 2567 if (bp & 0x02) { 2568 addr[nbp++] = (caddr_t)rdr1(); 2569 } 2570 if (bp & 0x04) { 2571 addr[nbp++] = (caddr_t)rdr2(); 2572 } 2573 if (bp & 0x08) { 2574 addr[nbp++] = (caddr_t)rdr3(); 2575 } 2576 2577 for (i = 0; i < nbp; i++) { 2578 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2579 /* 2580 * addr[i] is in user space 2581 */ 2582 return nbp; 2583 } 2584 } 2585 2586 /* 2587 * None of the breakpoints are in user space. 2588 */ 2589 return 0; 2590} 2591 2592#ifdef KDB 2593 2594/* 2595 * Provide inb() and outb() as functions. They are normally only available as 2596 * inline functions, thus cannot be called from the debugger. 2597 */ 2598 2599/* silence compiler warnings */ 2600u_char inb_(u_short); 2601void outb_(u_short, u_char); 2602 2603u_char 2604inb_(u_short port) 2605{ 2606 return inb(port); 2607} 2608 2609void 2610outb_(u_short port, u_char data) 2611{ 2612 outb(port, data); 2613} 2614 2615#endif /* KDB */ 2616